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Posts Tagged ‘vias’

Multibeam Patents Direct Deposition & Direct Etch

Monday, November 14th, 2016

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By Ed Korczynski, Sr. Technical Editor

Multibeam Corporation of Santa Clara, California recently announced that its e-beam patent portfolio—36 filed and 25 issued—now includes two innovations that leverage the precision placement of electrons on the wafer to activate chemical processes such as deposition and etch. As per the company’s name, multi-column parallel processing chambers will be used to target throughputs usable for commercial high-volume manufacturing (HVM) though the company does not yet have a released product. These new patents add to the company’s work in developing Complementary E-Beam Lithography (CEBL) to reduce litho cost, Direct Electron Writing (DEW) to enhance device security, and E-Beam Inspection (EBI) to speed defect detection and yield ramp.

The IC fab industry’s quest to miniaturize circuit features has already reached atomic scales, and the temperature and pressure ranges found on the surface of our planet make atoms want to move around. We are rapidly leaving the known era of deterministic manufacturing, and entering an era of stochastic manufacturing where nothing is completely determined because atomic placements and transistor characteristics vary within distributions. In this new era, we will not be able to guarantee that two adjacent transistors will function the same, which can lead to circuit failures. Something new is needed. Either we will have to use new circuit design approaches that require more chip area such as “self-healing” or extreme redundancy, or the world will have to inspect and repair transistors within the billions on every HVM chip.

In an exclusive interview with Solid State Technology, David K. Lam, Multibeam Chairman, said, “We provide a high-throughput platform that uses electron beams as an activation mechanism. Each electron-beam column integrates gas injectors, as well as sensors, which enable highly localized control of material removal and deposition. We can etch material in a precise location to a precise depth. Same with deposition.” Lam (Sc.D. MIT) was the founder and first CEO of Lam Research where he led development and market penetration of the IC fab industry’s first fully automated plasma etch system, and was inducted into the Silicon Valley Engineering Hall of Fame in 2013.

“Precision deposition using miniature-column charged particle beam arrays” (Patent #9,453,281) describes patterning of IC layers by either creating a pattern specified by the design layout database in its entirety or in a complementary fashion with other patterning processes. Reducing the total number of process steps and eliminating lithography steps in localized material addition has the dual benefit of reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Furthermore, highly localized, precision material deposition allows for controlled variation of deposition rate and enables creation of 3D structures such as finFETs and NanoWire (NW) arrays.

Deposition can be performed using one or more multi-column charged particle beam systems using chemical vapor deposition (CVD) alone or in concert with other deposition techniques. Direct deposition can be performed either sequentially or simultaneously by multiple columns in an array, and different columns can be configured and/or optimized to perform the same or different material depositions, or other processes such as inspection and metrology.

“Precision substrate material removal using miniature-column charged particle beam arrays” (Patent #9,466,464) describes localized etch using activation electrons directed according to the design layout database so that etch masks are no longer needed. Figure 1 shows that costs are reduced and edge placement accuracy is improved by eliminating or reducing errors associated with photomasks, litho steps, and hard masks. With highly localized process control, etch depths can vary to accommodate advanced 3D device structures.

Fig.1: Comparison of (LEFT) the many steps needed to etch ICs using conventional wafer processing and (RIGHT) the two simple steps needed to do direct etching. (Source: Multibeam)

“We aren’t inventing new etch chemistries, precursors or reactants,” explained Lam. “In direct etch, we leverage developments in reactive ion etching and atomic layer etch. In direct deposition, we leverage work in atomic layer deposition. Several research groups are also developing processes specifically for e-beam assisted etch and deposition.”

The company continues to invent new hardware, and the latest critical components are “kinetic lens” which are arrangements of smooth and rigid surfaces configured to reflect gas particles. When fixed in position with respect to a gas injector outflow opening, gas particles directed at the kinetic lens are collimated or redirected (e.g., “focused”) towards a wafer surface or a gas detector. Generally, surfaces of a kinetic lens can be thought of as similar to optical mirrors, but for gas particles. A kinetic lens can be used to improve localization on a wafer surface so as to increase partial pressure of an injected gas in a target area. A kinetic lens can also be used to increase specificity and collection rate for a gas detector within a target frame.

Complementary Lithography

Complementary lithography is a cost-effective variant of multi-patterning where some other patterning technology is used with 193nm ArF immersion (ArFi) to extend the resolution limit of the latter. The company’s Pilot™ CEBL Systems work in coordination with ArFi lithography to pattern cuts (of lines in a “1D lines-and-cuts” layout) and holes (i.e., contacts and vias) with no masks. These CEBL systems can seamlessly incorporate multicolumn EBI to accelerate HVM yield ramps, using feedback and feedforward as well as die-to-database comparison.

Figure 2 shows that “1D” refers to 1D gridded design rule. In a 1D layout, optical pattern design is restricted to lines running in a single direction, with features perpendicular to the 1D optical design formed in a complementary lithography step known as “cutting”. The complementary step can be performed using a charged particle beam lithography tool such as Multibeam’s array of electrostatically-controlled miniature electron beam columns. Use of electron beam lithography for this complementary process is also called complementary e-beam lithography, or CEBL. The company claims that low pattern-density layers such as for cuts, one multi-column chamber can provide 5 wafers-per-hour (wph) throughput.

Fig.2: Complementary E-Beam Lithography (CEBL) can be used to “cut” the lines within a 1D grid array previously formed using ArF-immersion (ArFi) optical steppers. (Source: Multibeam)

Direct deposition can be used to locally interconnect 1D lines produced by optical lithography. This is similar in design principle to complementary lithography, but without using a resist layer during the charged particle beam phase, and without many of the steps required when using a resist layer. In some applications, such as restoring interconnect continuity, the activation electrons are directed to repair defects that are detected during EBI.

—E.K.

New Applied PVD system targets TiN hardmasks for 10nm, 7nm chips

Tuesday, May 19th, 2015

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By Jeff Dorsch, Contributing Editor

Applied Materials today introduces the Applied Endura Cirrus HTX PVD, a physical vapor deposition system for creating titanium nitride hardmask films that could be used in fabricating 10-nanometer and 7nm chips.

“Titanium nitride is the metal hardmask of choice,” harder than copper and nearly as hard as diamond, says Sree Kesapragada, Applied’s global product manager for Metal Deposition Products.

“Patterning plays key role in defining the interconnect,” Kesapragada says. “Perfect via alignment is critical for device yield. Hardmask ensures the perfect via alignment critical for yield.”

The hardmasks created with the Endura Cirrus HTX TiN system strike the required balance between neutral stress and film density hardness, he asserts. The TiN hardmask, meant to resist the erosion of etching, helps ensure that via etches land where they are supposed to, and not too close to neighboring vias, which can creates shorts.

Metal hardmask layer manages alignment errors.

Applied has worked with customers at multiple sites in developing the new PVD system over the past two to three years, according to Kesapragada. He emphasizes that the Cirrus HTX TiN system offers “precision control over TiN crystal growth,” as the process chamber is “designed for tensile high-density TiN films.” The new PVD system enables high density, tensile films thanks to a high level of ionization during deposition made possible by a high frequency source.

High film desnity is needed to prevent erosion, and a neutral-to-tensile stress is needed for pattern fidelity. CVD/ALD films have tensile stress, but are low density. Traditionally deposited TiN films have good density, but compressive stress.

The formation of “islands” of TiN crystals is almost like chemical vapor deposition, “layer by layer,” Kesapragada says, “in a PVD chamber.”

In the process chamber, the first of its kind, titanium atoms are reactively sputtered in a nitrogen-based plasma, allowing for tunable composition, according to Applied. This chamber can be used for high-volume manufacturing of semiconductors with 7nm features, covering two process-node generations, Kesapragada says.

There is also “very established integration” with chemical mechanical planarization equipment, he adds.

Applied is the market leader in TiN PVD systems, with more than 200 systems shipped, according to Kesapragada. Those PVD systems have more than 700 process chambers, he adds.

The Endura Cirrus HTX TiN PVD system is being formally introduced this week at the IEEE’s 2015 International Interconnect Technology Conference in Grenoble, France.