By Mark LaPedus
Qualcomm has the highest market share for baseband solutions in handsets, resulting in a position far out in front of its competitors. ST-Ericsson has strong products on the market with competitive features. But one analyst at ABI Research questions why ST-Ericsson was broken up just as it finally came out with a highly competitive product, which was based on FD-SOI.

The worldwide semiconductor foundry market totaled $34.6 billion in 2012, a 16.2% increase from 2011, according to final results by Gartner. TSMC maintained the No. 1 spot in the rankings in 2012. Strong performance on 32nm yields and the availability of sub-45nm wafer capacity at the Dresden, Germany, fabs allowed GlobalFoundries to advance to the No. 2 position in 2012. UMC‘s market share decreased due to reduced wafer shipments. Driven by the wafers consumed by Apple, Samsung moved up four spots to the No. 5 position with 175.5% growth in 2012.

At this year’s Symposium on VLSI Technology, Intel will report technical details of its embedded DRAM with 22nm technology on bulk silicon wafers. Intel realized a 0.029mm2 DRAM cell capable of meeting >100us retention at 95 C. In the DC-DC converter session, Intel will present a switched capacitor step-down converter designed in a 22nm tri-gate CMOS technology. The VLSI Symposium is slated for June 11–14 in Kyoto, Japan.

At the VLSI event, STMicroelectronics and CEA-LETI will report six transistor SRAM (6T-SRAM) cells for high-density and low-voltage. The technology is fabricated at the 28nm node using FD-SOI technology for the first time.

At the VLSI Symposium, IBM and GlobalFoundries will report a SiGe channel tri-gate pFET with aggressively scaled fin width and gate length dimensions. It is fabricated using SiGe on an insulator substrate. Excellent electrostatic control down to Lg= 18nm and Wfin<18nm has been reported.

At the event, IMEC and GlobalFoundries will present the first demonstration of strained germanium channel pFETs fabricated on SiGe strain relaxed buffers, which is surrounded by STI region. Also, they introduced raised SiGe source/drain structures (Ge concentration= 75%) with an implant-free quantum well, replacement metal-gate process and germanide in contacts to solve void issues.

In addition, STMicrolectronics, Samsung, GlobalFoundries and IBM will report a 64nm pitch BEOL integration and material strategy. A self-aligned-via (SAV) approach was exploited for single pattern via extendibility, enabling via placement at CPP with a single mask.

SEMI reported that for the quarter ending Dec. 31, 2012, the worldwide photovoltaic manufacturing equipment book-to-bill ratio remained well below parity, at 0.45, for the seventh consecutive quarter. Booking levels continue to be low as PV manufacturers grapple with oversupply across the supply chain.

Khaled Juffali Company (KJC), a Saudi Arabian investment company, and Soitec, signed a memorandum of understanding (MOU) to cooperate in driving solar industry growth in Saudi Arabia and the Middle East. Under the MOU, the two companies will create a joint venture to market and sell concentrator photovoltaic (CPV) systems in the Kingdom of Saudi Arabia.

Hwa Chong Institution emerged as the winner of the Applied Materials Clean Tech Competition in Singapore. The project focused on utilizing calcium carbonate found in clam shells to remove toxic metal ions from waste water.

The separate hardware and software teams in companies are notorious for not being on the same page, thereby putting product development times and cost at risk. Mentor Graphics CEO Walden Rhines outlined some new and practical solutions to the problem.

Mentor Graphics announced the release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon. The tool provides a tighter connection between hardware and software co-development, but allows software developers to use existing programming tools with extensions.

Cadence announced results for the first quarter of fiscal year 2013. Cadence also completed its previously announced acquisition of Tensilica.

Advantest will acquire W2BI, a provider of system level test automation software focusing on wireless communications.

Shipments of smart glasses may rise to as high 6.6 million units in 2016, up from just 50,000 in 2012, for a total of 9.4 million units for the five-year period, according to an upside forecast from IMS Research.

The worldwide mobile phone market grew 4% year over year in the seasonally slow first quarter of 2013 as smart phones out-shipped feature phones for the first time, according to IDC. Nokia, BlackBerry and HTC have dropped out of the top rankings.

By Jeff Chappell
There may have been a time when AMD founder Jerry Sanders famous quote: “real men (i.e., real companies) have their own fabs” rang true, but in today’s business climate it seems quaint at best.

Fabless or fab-lite business models are more popular than ever today, while some IDMs have turned back the clock, so to speak, looking to improve capacity utilization and revenues by offering foundry services—Intel and Samsung among them. Then there is the fact that the third-largest chipmaker in 2012, in terms of revenue, was a pure-play foundry.

As the 28nm node capacity ramp continues in the foundry market in 2013, following unexpected demand and capacity bottlenecks in 2012, today’s foundry market is the end result of market trends and forces with old roots. But those trends and forces have been compounded in modern times by extreme financial and market necessities, not to mention technology.

In one sense, however, at its core, the foundry market hasn’t changed since Taiwan Semiconductor Manufacturing Co. (TSMC) launched as the industry’s first pure-play foundry in 1987: Chip companies look to foundries, either as a customer or as a provider, to maximize productivity and thereby minimize costs. That part of the game hasn’t changed, whether it involves a component supplier designing power modules with 0.18-micron design rules for manufacturing on 200mm wafers, or one of the two GPU giants producing their next-generation graphics processors based on the latest technology.

The trend for years now has been fabless or fab-lite; even Sanders’ own AMD spun out its manufacturing arm several years ago to create one of the world’s largest pure-play foundries, GlobalFoundries. This has naturally in turn spawned the growth of the pure-play foundry market from its birth some 26 years ago.

Indeed, last year the overall foundry market enjoyed revenues of $29.6 billion, managing year-over-year growth of 12%, which is three times that of the chip industry over all in 2012. That growth caught everyone by surprise including the foundries themselves; 28nm capacity was tight for much of the year, even as yields improved dramatically—so much so that it reportedly impacted some capital equipment purchases, in spite of tight foundry capacity.

But that illustrates the biggest and most obvious change in the foundry industry in modern times: The foundries themselves are involved directly with developing leading-edge semiconductor technology. In fact, with the industry looking at the end of planar CMOS at the leading edge for some devices with the advent of 3D transistor architectures and the high-k materials they require, leading foundries no longer can rely on a mix of conventional scaling, publicly available data and equipment and process technology suppliers to get their jobs done. Research and development now must be within their purview, at least for those playing at the leading edge.

“Historically foundries don’t do R&D, their clients do it,” noted Dean Freeman, a research vice president at Gartner Research. That’s not so, today.

Nothing illustrates that fact better than TSMC’s R&D budget. In 2012 the company spent 33.8 billion NT, or about $1.13 billion, on R&D—a quarter of its revenue. This year the company plans to spend 40.4 billion NT, or about $1.35 billion, which includes adding some 500 people to its employee headcount, bolstering its R&D staff from 3,400 people to 3,900.

Indeed, leading foundries have joined the leading IDMs and technology consortia as purveyors of—not just manufacturers of—advanced technology.

While TSMC and its foundry brethren in the first tier of the pure-play market—Globalfoundries and United Microelectronics Corp. (UMC)—continue to build out 28nm capacity, they are also hard at work on the 20nm node and the subsequent hybrid 14/16nm finFET based on a 20nm back-end of line process. In fact, TSMC just announced first tapeouts of an ARM A-57 processor, based on the 64-bit ARMv8 processor series and built with 16nm transistor technology, including finFETs. This followed their rival’s announcement of a few months earlier. In February, GlobalFoundries announced a “first implementation” of a dual-core ARM A9 processor using the company’s 14nm-XM FinFET transistor architecture.

Follow the money
Being on the very leading edge of technology is driving growth among the first-tier foundries.

Like many others in the industry, TSMC and its chairman and CEO, Morris Chang, are quite bullish on the continued demand for 28nm technology as well as the development of 20nm technology. In general, 28nm designs, with their combination of lower power consumption and speedier transistors, have consequently proven cost-effective for a chip industry currently driven by mobile devices—smartphones, tablets and ultra lightweight notebooks. During TSMC’s review of its 2012 results earlier this year, Chang said the company will continue to aggressively grow its 28nm capacity and output; 2013 capacity and output will triple that of 2012, he said.

“It’s all about lower power with functionality and no sacrifice on the power requirements,” observed Kathryn Ta, managing director of strategic marketing for Applied Materials’ Silicon Systems Group. The equipment and process technology supplier’s foundry customers are seeing a need to move to 3D transistor architectures with minimal leakage, she said, because of those power requirements.

Development will continue at 20nm and 16nm as well at TSMC and its rivals. This year, 88% of the 9 billion NT that TSMC will spend on capital expenditures will go to 28nm, 20nm and 16nm capacity; an additional 5% will be spent on additional R&D equipment. Chang predicted that by Q3 of this year high-k metal gate production will surpass that of standard oxynitride gates, a gap that naturally will widen in Q4 and beyond.

“Enough discussions have taken place with enough customers … to lead us to believe that in both its first and second year of production (2014 and 2015, respectively) the volume of 20nm SoCs will be larger than that of 28nm in its first and second years of production (2012 and 2013),” Chang said.

He further noted that this represented the state of the art, and not just for the foundry industry, but for the industry as whole. This may indeed prove to be true in a few years as those 20nm and 16nm/14nm SoC devices move into production. It’s a far cry from the days when foundries were traditionally technological also-rans.

But then the first-tier foundries at the leading edge are still playing catch-up in the meantime with those IDMs at the leading edge, namely Intel. The world’s biggest chipmaker has kept Moore’s Law on track on the CPU side of the ITRS roadmap, last year having brought its Ivy Bridge processors to market. These feature 22nm transistors replete with finFETs; Intel’s own roadmap calls for 14nm designs to be in production in 2014; in terms of mobile SoCs like those the foundries are talking about, the company has promised its 22nm Atom SoCs will be in production in 2015.

“Intel seems to be able to continue to shrink because they spend a fortune on R&D,” said Gartner’s Freeman. “The foundries are pushing hard to catch up,” He noted that while both GlobalFoundries and TSMC have 16nm/14nm chips featuring finFETs in development, they are taking a shortcut, so to speak, by employing 20nm metal interconnects. “It’s close to what Intel is doing. Intel’s design may be more sophisticated, but the lithography is the same.”

Plenty of room, and business, at the trailing end
But not everybody in the foundry market is playing at the leading edge. The same market and industry forces that have induced the bigger pure-play foundries to move beyond their historical roles also have created a two-tiered pure-play foundry market. In the first tier are those that have the deep pockets to play in this space: TSMC, Globalfoundries, UMC, and to a lesser extent China’s Semiconductor Manufacturing International Corp. (SMIC).

Then there are the second-tier companies, those that are still fulfilling a traditional foundry role—at trailing edge processes, but nevertheless needed or even essential semiconductor manufacturing technology and capacity. Indeed, many second-tier foundries do quite well with their particular market niches and technologies. In the world of mobile consumer gadgets, including but not limited to smartphones and tablets, there are still many components fabricated on established, trailing-edge technology, such as sensors, microcontrollers and power components.

Even in 2013, where CPUs with 22nm transistors and mobile SoCs with 28nm transistors represent the current state of the art, some 40% of all silicon used to manufacture chips goes into mature devices fabricated on 200mm wafers. That’s typically 0.18-micron designs or larger. And much, if not most, of that is coming from pure-play foundries.

At the top of that second-tier foundry market, Israel’s TowerJazz, for example, has found a relatively comfortable niche making high-speed devices for a broad range consumer applications utilizing 0.13-micron designs and larger. It also makes CMOS image sensors with 0.16- and 0.11-micron design rules. In terms of financials, this has translated to record revenues: last year TowerJazz posted revenues of $638.8 million, an increase of 5% over the previous year.

Freeman suggested there are plenty of opportunities for these second-tier foundries. The so-called “Internet of Things,” for example, is a major driver behind sensor applications, as it is for the controllers needed to coordinate the data these sensors produce—data that can be managed via mobile Internet devices. These supplemental and complementary applications typically don’t need cutting-edge technology.

As has always been the case in the foundry industry, as leading-edge technology becomes trailing-edge, there will be new opportunities for second-tier foundries, as well. Some of the larger second-tier foundries eventually may have the opportunity to compete with first-tier companies head-to-head with 28nm capacity if they have deep-enough pockets to invest.

In the bifurcated smartphone market, for example, low-end smartphones that originally utilized chips manufactured with 40nm technology soon will migrate to chips with 28nm technology, as capacity ramps and it becomes even more cost effective, said Applied’s Ta. Even as the leading-edge players are driven beyond the 28nm node and the adoption of 3D gate architectures, the industry could very well see an extended 28nm node, driven by this market for lower-end smartphones and other mobile devices, she said.

But What About …
Things rarely ever prove to be so clearly defined in the chip industry. With players such as Samsung, Intel and IBM among others flirting with the foundry business, and some of the larger first-tier foundries suffering the same financial headaches that have plagued the IDMs in the past—problems that drove some of them to a fabless model in the fist place—there are some significant unknowns.

While 3D, high-k metal gate architectures, i.e, finFETs and the like, seem to be the wave of the near future, there are still those in the industry that tout the efficacy of fully depleted silicon-on-insulator (FD-SOI) as either an alternative to complement to 3D gate technology, for example.

IBM and its technology alliance partners have considered FD-SOI as a possible outcome of the semiconductor technology roadmap in the near future, Ta noted. “We see most of the effort on the finFET/Intel approach, but some of our customers are still talking about SOI,” perhaps used in some combination with finFETs, she added.

Gartner’s Freeman noted that Intel’s finFET devices are already fully depleted devices, although SOI could conceivably provide a bit less leakage; as such it may be an option at future nodes. Given the transistor speed and power usage achieved by its 22nm Atom processors, which are manufactured on top of bulk silicon technology, that seems unlikely though for Intel and those choosing to follow its lead. Freeman further observed that GlobalFoundries, once a proponent of FD-SOI, has backed off somewhat, although some of its largest customers remain committed to an FD-SOI strategy for the foreseeable future. IBM, for one, has publicly stated it will use FD-SOI, finFETs and stacked die together at future nodes.

But what does this mean for the leading-edge foundries? As always they will have to be able to manufacture what their customers want. It may be that some chipmakers will choose to go the FD-SOI route and that could prove a competitive opportunity for any foundry.

Another wild card that the top-tier foundries will need to take into account is the overlapping of technology nodes, which may become more pronounced with the extension of the 28nm node coupled with the rush to get 20nm devices into production. “It’s happening faster than previous node transitions have happened,” Applied’s Ta, noting that it’s driven by the low-power promise of finFETs. In the past node transitions typically took two to 2.5 years; “This time we may see a 1.5 year transition to finFETs,” she added.

Another question mark in the foundry market itself is SMIC. While most would still classify the Chinese foundry as a top-tier foundry, it is in a very real way straddling the gap between first and second tier. The company, once relatively close behind TSMC and UMC, has foundered in red ink and legal woes in recent years. While it has subsequently experienced an impressive turnaround financially under the helm of current CEO Tzu-Yin Chiu in 2012, it’s capital expenditures fell dramatically, even as capacity utilization hit 95% in Q2, and it is well behind its rivals in terms of technology.

Customer tapeouts of 28nm devices won’t take place until the end of this year; One of SMIC’s largest domestic customers, Spreadtrum, already has been forced to move to rival TSMC to meet its current plans for 28nm devices.

SMIC’s Chiu has said that the company’s 28nm technology will include both standard polysilicon oxynitride devices and high-k metal gates, and that it has plans to manufacture finFET devices at the 20nm node. In the meantime, it has found a saving grace in applications typically manufactured by second-tier players: smart cards, CMOS image sensors and power management chips.

Which way will SMIC go? Will it continue its impressive turn around by abandoning the leading edge or will it continue to play technological catch up? Or perhaps a little bit of both?

Time will tell. But it’s certainly an interesting time for the foundry business, and certain that for the foreseeable future the pure-play foundries will have to work hard at the cutting edge of semiconductor technology.

By Mark LaPedus
For years, Brazil has been trying to get a semiconductor industry off the ground. A government-backed entity called Ceitec operates a small-scale fab in Brazil. There are also several IC design centers in that nation. Last November, SIX Semiconductors emerged and announced plans to build a fab in Brazil. The venture includes a partnership between IBM and SIX Soluções Inteligentes, a technology company of EBX Group, and others. The group will invest R$1 billion, or US$513 million, to a fab in Ribeirão Neves. Recently, the group was on a job-recruiting mission in the United States. In total, there are 300 job positions available at SIX Semiconductors in Brazil.

Starboard Value LP, together with its affiliates, currently owns 7.4% of the outstanding common shares of chip-packaging IP provider Tessera. The investment firm wants to shake up the board and oust the CEO. This follows allegations that Tessera’s CEO may have been engaged in inappropriate behavior.

Front-end fab equipment spending is expected to be flat in 2013, remaining around $31.7 billion, according to SEMI. Front-end fab equipment spending is projected to hit $39.3 billion in 2014, a 24% increase, according to SEMI.

Semiconductor industry growth drivers and European market strategies were featured topics at the recent SEMI Industry Strategy Symposium (ISS) Europe 2013. In one area of growth, NXP believes that by 2022, about 20% to 25% of global passenger vehicles will be connected to intelligent traffic management infrastructure and/or in-vehicle networks.

The flexible and printed electronics community reports encouraging progress in the materials and process ecosystem needed for commercial production, according to SEMI.

RDA Microelectronics has begun volume shipments of its GPS LNAs for use in Samsung’s 3G handsets. Developed on silicon-on-insulator (SOI) CMOS process technology, RDA’s GPS LNA is a high-gain, small-size amplifier ideally suited for GPS, Galileo and GLONASS applications in 2G and 3G handsets.

RF chipmaker Skyworks Solutions said that its SOI switching technology is now being utilized by European, Japanese, Korean and North American car manufacturers for advanced infotainment systems.

Peregrine Semiconductor will collaborate with Murata on a multisource arrangement for RF switches and other components based on Peregrine’s UltraCMOS technology. UltraCMOS is based on a variant of SOI.

Cadence introduced design and verification IP supporting the new Mobile PCI Express (M-PCIe) specification.

Mentor Graphics announced several new capabilities for its Flowmaster simulation software solution for thermo-fluid systems. Mentor also intends to pay an annual cash dividend of $0.18 per share on its common stock.

Applied Materials has approved an 11% increase in the quarterly cash dividend from $0.09 to $0.10 per share, payable on June 13.

Spansion and United Microelectronics Corp. announced the joint development of a 40nm process that integrates UMC’s 40nm LP logic process with Spansion’s embedded charge trap flash memory technology. As part of the non-exclusive agreement, UMC is licensed to manufacture products based on this technology for Spansion.

Cortus, a provider of 32-bit processor IP, and speciality foundry Dongbu HiTek are teaming up to offer platform solutions. The design platforms will be based on the Dongbu HiTek 0.13-micron eFlash technology and Cortus APS3R processor and peripheral IP.

IDT has transferred the assets and design team of its smart-metering IC product lines to Atmel in an all-cash transaction.

Significant reductions in capital equipment spending among DRAM makers are expected to stabilize DRAM prices at a minimum, but more likely will help drive prices further upward throughout the balance of the year, according to IC Insights.

Capex budgets are also being trimmed for NAND flash (though not nearly as much as DRAM), and that, along with ongoing unit demand, has put upward pressure on ASPs for these memory devices as well.

By Mark LaPedus
Altera has entered into an agreement for the future manufacturing of its FPGAs based on Intel’s 14nm tri-gate transistor technology. Intel will provide foundry services for the FPGA giant. That puts the processor giant on a collision course in the foundry business against the likes of GlobalFoundries, Samsung, TSMC and UMC

The Altera-Intel deal could change the landscape in the foundry business, in which Intel will likely become a much bigger player in the arena. But does Intel have staying power to remain in the foundry business? Added John Vinh, an analyst from Pacific Crest Securities: Altera’s “foundry agreement with Intel is exclusive for the foreseeable future. We believe Altera will have exclusive access versus Xilinx at 14nm and effectively have the right of first refusal at 10nm. Strategically, we believe this is likely the most significant aspect of this agreement in that it prevents Xilinx from having access.”

At SPIE, ASML Holding disclosed various milestones with its extreme ultraviolet (EUV) lithography technology. ASML’s EUV production tool, dubbed the NXE:3300B, has demonstrated resolutions of 13nm for lines and spaces and 18nm contact holes. In addition, ASML demonstrated a 40-Watt source with dose control and under good collector protection conditions in six 1-hour runs. It also demonstrated a 55-Watt source in a 1 hour run. But that’s a far cry from the eventual goal. By 2015, ASML hopes to deliver a 250-Watt source for the NXE:3300B, thereby enabling a throughput of 126 wafers an hour.

With the help of self-aligned double patterning (SADP), sometimes called spacer, ASML’s NXE:3300B also demonstrated the ability to print lines and spaces down to 9nm. The work was done in conjunction with ASML, Applied Materials and Imec.

At the International Semiconductor Strategy Symposium in Europe (ISS Europe) on Feb. 24-26, the European semiconductor industry discussed 450mm fabs and other chip topics. In addition, European Commissioner Neelie Kroes floated the idea of creating an “Airbus for chips,” a European initiative for the semiconductor industry comparable to the launch of the Airbus in the aviation industry.

Also at ISS Europe, Malcolm Penn, chairman and CEO of Future Horizons, said that the decline of the major European chip makers has been a result of a defeatist attitude, not necessarily fundamental structural issues. He suggests European chip makers should build a 450mm fab jointly and operate it as a foundry.

SEMI has announced the release of “Global Trade War and Peace: Unified Approaches to a Global Solar Energy Solution,” a white paper containing recommendations to move beyond trade litigation and encourage an accelerated path towards dispute resolution.

In case your calendar has turned into a blur, take note: Semicon is near! SEMI, in collaboration with leading investment groups, has announced the Silicon Innovation Forum (SIF). The forum will bridge funding gaps for new and early-stage companies with manufacturing and technology solutions. SIF will be held in conjunction with Semicon West, on July 9 at the Moscone Center in San Francisco.

At the Mobile World Congress in Barcelona, Peregrine Semiconductor rolled out its latest version of its UltraCMOS process technology, dubbed Semiconductor Technology Platform 8 (STeP8). UltraCMOS is a variant of silicon-on-insulator (SOI) technology called silicon-on-sapphire (SoS).

Also in Spain, Skyworks Solutions said it is ramping several antenna-tuning products with leading smartphone manufacturers. The tuning devices are based on SOI technology.

The RATP Group, the fifth-largest urban transport operator worldwide, has awarded Soitec and Philips/Step an LED lighting contract for its metro and network stations.

Soitec and Medina College of Technology have signed a cooperative agreement for concentrating photovoltaic technology in Saudi Arabia.

GT Advanced Technologies has entered into a development and licensing agreement with Soitec to develop and commercialize a hydride vapor phase epitaxy (HVPE) system for producing GaN template substrates.

Mentor Graphics announced record financial results for the company’s fiscal fourth quarter and year ended Jan. 31.

During a conference call, Walden Rhines, chairman and CEO of Mentor, said the quarter was an all-time revenue and EPS record. Rhines also has a mixed forecast for the overall IC industry in 2013. “For next year, the analysts project mid-single-digit growth, but the general attitude is less positive,” he said.

Mentor Graphics rolled out the Kronos Cell Characterization and Analysis platform.

A blogger discusses Applied Materials, saying the company is at the cyclical trough and its prospects should improve with an increase in equipment spending.

Applied Materials announced that Bob Halliday has been named senior vice president and chief financial officer. Halliday previously was executive vice president and chief financial officer of Varian Semiconductor Equipment Associates prior to Applied’s acquisition of the company in November 2011.

Micron Technology announced the Tokyo District Court’s issuance of an order approving Elpida’s plan of reorganization. Elpida’s plan of reorganization calls for Micron to acquire Elpida. In addition, mixed-signal foundry specialist LFoundry has acquired Micron’s fab in Italy.

Whatever happened to Conexant Systems? The chipmaker recently went private to avoid a takeover. Now, the company this week implemented a restructuring agreement. As part of the plan, Conexant voluntarily filed protection under Chapter 11 of the United States Bankruptcy Code.

Photomask maker Photronics has announced its intent to acquire the shares of its majority-owned Taiwan subsidiary, PSMC.

After a loss and a proxy battle, Aetrium is considering options that may include a sale or other disposition of one or both of its reliability test and test handler product groups.

According to IHS, the competitive landscape of the cell-phone integrated circuits business has completely transformed over the past five years, with Qualcomm and Samsung capitalizing on the rise of smartphones and 4G.

By Mark LaPedus

In a major move, Intel is expanding its efforts in the foundry business. Altera has entered into an agreement for the future manufacturing of its FPGAs, based on Intel’s 14nm tri-gate transistor technology. Intel will provide foundry services for the FPGA giant.

Until now, Intel has been a bit player in the foundry business. Now, the chip giant is on a direct collision course in the foundry business against the likes of GlobalFoundries, Samsung, TSMC and UMC.

Intel has been ramping up its 22nm tri-gate technology for some time, with plans to deliver its 14nm process by year’s end. The chip giant has yet to describe the details about its 14nm tri-gate technology.

Altera elected to skip Intel’s existing 22nm process. Instead, the company will move directly to Intel’s 14nm finFET technology, thereby leapfrogging its competition, namely Xilinx.

The move also represents a major switch in strategy at Altera. Prior to today’s agreement, Altera was exclusively procuring foundry wafers from Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). But TSMC and other foundries are lagging behind Intel in finFET development. In fact, Intel has a two- to three-year lead over its rivals in finFETs, prompting Altera to look at Intel as a foundry partner. Others could also follow suit.

Still, TSMC is Altera’s primary foundry, according to Altera. TSMC will continue to supply a wide array of processes to fulfill Altera’s product portfolio, including the soon-to-be-released 20nm products, existing mainstream products, and long-lived legacy components. Altera is fully engaged with TSMC on developing products based on next-generation process technologies.

But now, Altera is reaching out to Intel to get a jump in the finFET race. “Altera’s FPGAs using Intel 14nm technology will enable customers to design with the most advanced, highest-performing FPGAs in the industry,” said John Daane, president, CEO and chairman of Altera. “In addition, Altera gains a tremendous competitive advantage at the high end in that we are the only major FPGA company with access to this technology.”

Patrick Dorsey, senior director of product marketing for Altera, said the FPGA chip maker decided to skip Intel’s 22nm tri-gate process, because Intel’s 14nm technology represents a “better match” for Altera’s future product roll out. “This represents a giant leap in terms of capabilities,” Dorsey said.

Analysts agreed. “In our view, the move is mutually beneficial to Altera and Intel,” said Doug Freedman, an analyst with RBC Capital Markets.  “On the Altera side, the company is now on-track to reach sub-20nm before competitor Xilinx.”

Freedman added: “On the Intel side, we believe this is the first in what is likely to be more tier-one customer announcements in the future.” Indeed, Intel is talking to Apple about a similar arrangement.

“We look forward to collaborating with Altera on manufacturing leading-edge FPGAs, leveraging Intel’s leadership in process technology,” said Brian Krzanich, chief operating officer at Intel.  “Next-generation products from Altera require the highest performance and most power-efficient technology available, and Intel is well positioned to provide the most advanced offerings.”

Until now, Intel was only working with smaller fabless companies in the foundry business. For example, Achronix Semiconductor last week officially began shipping the first in a family of devices based on Intel’s 22nm finFET technology. Achronix’ FPGAs are built on a foundry basis by Intel, as part of a major agreement announced in 2010. Another company, Tabula, will also have its 22nm FPGAs made on a foundry basis by Intel.  And flow processor vendor, Netronome, is also having its 22nm products built by Intel.

Intel recently announced capital spending of $13 billion in 2013, including $2 billion for 450mm development.

By Mark LaPedus
A year ago, chipmakers were reeling from a severe shortage of 28nm foundry capacity, prompting foundries to ramp up their fabs at a staggering pace.

At the time, foundries were unable to keep up with huge and unforeseen demand for mobile chips. The shortfall was also caused by low yields and the overall lack of installed 28nm capacity.

Today, the 28nm crunch is largely over. The foundries have caught up with the demand and customers no longer are feeling the pinch. And as it turns out, 28nm is a sweet spot for many devices and the technology will remain a long-lasting node.

However, the overzealous foundries may have expanded too fast. In fact, there are some signs of a possible foundry glut, and falling fab utilization rates, for 28nm and other processes in 2013. “I don’t see a shortage problem,” said Samuel Wang, an analyst at Gartner. “But overall utilization rates for advanced technologies will go down this year.”

Mobile chipmakers represent the biggest customers for foundries, but pockets of the business are cooling off to some degree. So, unless there is a steep upturn in the near term, the foundry market may quickly turn into a buyers’ market in 2013. Average selling prices for wafers could steadily drop, putting a squeeze on foundry margins.

Besides 28nm, foundries are simultaneously developing 20nm planar and 14nm-class finFETs. In doing so, foundries are moving toward the long-awaited “virtual IDM” model, where vendors and customers collaborate more closely under the same roof.

The shift towards the “virtual IDM” model is easier said than done, however. “The foundries will have some obstacles,” said Robert Bruck, vice president and general manager of the Technology Manufacturing Engineering Group at Intel. “Design, process technology, development and equipment costs are going up.”

As the costs and challenges mount, there are signs that the leading-edge foundry business is ripe for a shakeout. Currently, there are six companies that provide leading-edge foundry services in one form or another: GlobalFoundries, IBM, Intel, Samsung, TSMC and UMC.

28nm glut?
In total, the IC market is expected to increase 6% in 2013, compared to a drop of 1% in 2012, said Bill McClean, president of IC Insights. Capital spending is expected to fall 10% in 2013, but foundry CapEx will remain flat this year, he added.

For 28nm alone, the foundries had a total capacity of 200,000 wafer starts per month (wspm) by the end of 2012, according to Barclays Capital. In 2013, the foundries are expected to add an additional capacity of 75,000 to 100,000 wspm for 28nm, according to Mike Splinter, chairman and chief executive of Applied Materials.

And at 20nm, the foundries are expected to have a total capacity of 25,000 wspm in 2013, Splinter said in a recent conference call. Most of that capacity will be added in the second half of 2013, he said.

Splinter projects that the worldwide wafer fab equipment (WFE) market will be flat to minus 10% in 2013, up from minus 5% to minus 15% from his previous forecast. “We think the foundries will be down, but not as low as we expected,” he said.

CapEx race
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is showing no signs of a slowdown. The world’s largest foundry vendor has increased its capital spending from $8.3 billion in 2012 to $9 billion or more in 2013.

For 28nm, TSMC is expanding its capacity threefold in 2013 over 2012, said Morris Chang, chairman and chief executive of TSMC. In 2012, the polysilicon version of 28nm represented 100% of TSMC’s output. TSMC is expanding its 28nm high-k/metal-gate technology, which will reach the crossover point in the third quarter of 2013, he said.

The company also sees strong demand for 20nm. Apple will have its upcoming 20nm A7 application processors made on a foundry basis by TSMC, according to Barclays Capital, which noted that Apple is switching foundry vendors from Samsung to TSMC.

Meanwhile, GlobalFoundries, the world’s second largest foundry vendor, has set its capital spending budget at $3.5 billion in 2013, said Ajit Manocha, chief executive of GlobalFoundries. In 2012, GlobalFoundries’ capital spending hit $3.2 billion, according to Barclays.

The spending will help GlobalFoundries’ efforts to become more of a “virtual IDM.” In January, GlobalFoundries announced plans to build a multi-billion dollar R&D facility at its Fab 8 campus in Saratoga County, N.Y. The company’s new Technology Development Center (TDC) will help accelerate its 10nm and 7nm process development.

The TDC will also house part of GlobalFoundries’ stacked-die packaging and advanced photomask efforts. As photomask complexities soar, “some customers want a turnkey solution,” Manocha said.

Within its new 300mm fab in New York, the company has begun ramping up 28nm and 20nm processes. In 2013, Fab 8 is expected to expand from 10,000 to 30,000 wafers a month. “That’s still on plan,” he said. “We are also expanding our fab production in Dresden and Singapore.”

In total, GlobalFoundries will offer five technology platforms: bulk planar, bulk finFET, super-steep retrograde well (SSRW), FD-SOI (minimum) and FD-SOI (maximum). Customer tapeouts for its 14nm-class finFETs are expected in 2013, with production slated for 2014.

The maximum version of FD-SOI is tuned for specific applications, said Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries. Meanwhile, the minimum version is a simple and an “out of the box” FD-SOI technology, Kengeri said.

The company will provide FD-SOI wafers on a foundry basis for STMicroelectronics and other customers. GlobalFoundries’ 28nm FD-SOI process will move into risk production in the fourth quarter of 2013, with production slated for the first quarter of 2014.

Meanwhile, amid the apparent loss of a major customer in Apple, Samsung has cut its logic capital spending from 8 trillion Korean won in 2012 to between 4 trillion and 4.5 trillion Korean won in 2013, according to Barclays. Apple accounts for roughly one-third of Samsung’s logic capacity.

Samsung’s main logic/foundry fab is called S1, which is in Korea. S1 is making 28nm devices and is capable of low-volume finFET production. “S1 has more than doubled its size over the last year,” said Ana Hunter, vice president of foundry services at Samsung Semiconductor.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, has been a dedicated foundry plant for Apple. The other fab in Austin was previously a NAND facility. Last year, Samsung converted that fab from NAND into a 28nm logic/foundry plant.

In 2012, the company put on the brakes on its new S3 fab, a 300mm plant in Korea. “S3 resumed construction at the end of January,” said Christian Gregor Dieseldorff, an analyst at SEMI. “Equipment may begin to move in by mid-year. I think this may be the earliest.”

The S3 fab, which is expected to ramp up in 2014, will manufacture 20nm planar devices and 14nm-class finFETs. With process design kits available today, Samsung is expected to sample finFETs in 2014. In addition, the company has deployed “training teams” to help customers with their finFET designs, Samsung’s Hunter said.

The complexity of new and advanced designs will require more handholding between the foundries and their customers. “The collaboration has to get deeper with customers,” she added.

In moving towards the virtual IDM model, the foundries face some challenges. “There are very large investments that are required,” Intel’s Bruck said. “How do you accelerate the yield learning? What about the IP issues? Another aspect in terms of the foundry model is the delay that we are seeing in terms of revenue on the leading-edge.”

All chipmakers, including Intel, face the same challenge: How to keep up with the soaring R&D costs associated with the new and emerging technologies? “R&D is weighing on every level on the supply chain in this industry,” he added.

Foundry companies are keeping a close eye on Intel. To date, Intel is only providing foundry services to a limited customer base, and shows no signs of expanding the offering to a broader audience. So far, the chip maker is providing its 22nm finFET technology on a foundry basis to flow processor supplier Netronome and two FPGA vendors, Achronix and Tabula. In addition, Intel recently announced capital spending of $13 billion in 2013, including $2 billion for 450mm development.

Meanwhile, Taiwan foundry vendor United Microelectronics Corp. (UMC) continues to fall behind, as the company said it is having yield issues with its 28nm process. In addition, UMC recently said it will move directly from 28nm to 14nm finFETs, thereby skipping the 20nm node.

By Mark LaPedus
In New York, Saratoga County is booming. Saratoga counts on several growth engines, including semiconductors. In the county, GlobalFoundries is ramping up a new fab and recently announced an R&D center. In addition, there is a new push to build casinos in the county to further boost the local economy. But the local mayor is apparently against the idea, according to reports.

Samsung overtook Apple as the top worldwide semiconductor buyer in 2012, according to Gartner.

In 2012, Samsung almost doubled its foundry sales and surpassed UMC to become the third-largest IC foundry in the world, according to IC Insights. IC Insights believes that Samsung will challenge GlobalFoundries for the No. 2 spot in the rankings in 2013.

Synopsys announced immediate availability of its EDA solutions for finFET-based semiconductor designs. GlobalFoundries and Samsung are collaborating with Synopsys in the arena.

Soitec announced its results for the third quarter. The mobility-driven markets continue to offset PC segment weakness.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.92 in December, up from 0.79 in November, according to SEMI. “Both bookings and billings increased in December, but remain below figures reported one year ago,” said Denny McGuirk, president and CEO of SEMI. “While uncertainty remains regarding the 2013 equipment outlook, the foundry and advanced packaging segments are the key investment drivers at the beginning of the year.”

SEMI announced that Rudy Kellner, vice president of the Industry Group at FEI, has joined the SEMI North American Advisory Board (NAAB).

The new edition of the International Technology Roadmap for PV (ITRPV) will be presented and published at the upcoming PV Fab Managers Forum, according to SEMI.

The Chinese end market dominated shipments of solar photovoltaic (PV) panels during the final quarter of 2012 with 33% of global end-market demand, according to NPD Solarbuzz.

Solar PV equipment spending was $3.6 billion for 2012, a 72% decline from the peak of $12.9 billion in 2011, according to NPD Solarbuzz. Finlay Colville, vice president at NPD Solarbuzz, said: “Spending for 2013 is forecast to decline even further to $2.2 billion, levels not seen in the industry since 2006.”

Mentor Graphics announced a hardware emulation solution for ARM Cortex-A9 MPCore processor-based system-on-chip (SoC) designs.

After two straight years of contraction, the global DRAM market has the opportunity to rebound to double-digit growth in 2013, according to IHS iSuppli.

A new generation of lower-cost and more appealing ultrabooks is expected to help cause global shipments of solid-state drives (SSDs) to more than double in 2013, according to IHS iSuppi.

With emerging economies such as China and India slowing down, the Southeast Asian nations are emerging as key destinations for multinational companies, both as markets for their products as well as a source for new technologies, according to Lux Research.

By Mark LaPedus
The first wave of 2.5D chips using silicon interposers are trickling out in the marketplace.
FPGA vendor Xilinx was the first chipmaker to ship a 2.5D device, and Altera, Cisco, Huawei and IBM recently have talked about their respective 2.5D chip developments.

Generally, Altera and Xilinx have taken a somewhat identical and straightforward approach. The two companies are separately developing 2.5D FPGAs, initially based more on homogenous devices. Both are also using Taiwan Semiconductor Manufacturing Co. Ltd.’s turnkey solution to integrate all or part of their 2.5D FPGAs.

Huawei is taking a different avenue, which is arguably more representative of the complex approach that many may take in their 2.5D efforts. The Chinese networking equipment giant is developing a heterogeneous 2.5D device that combines an FPGA from Altera and stacked DRAM from Tezzaron. The interposer comes from Singapore’s Institute of Microelectronics (IME). And fabless ASIC vendor eSilicon is handling the supply chain and integration process.

Putting the pieces together is expected to be a herculean effort. But having explored a multitude of options, Huawei decided to move down an arduous path—and for good reason. “The memory wall is a very serious problem,” said Anwar Mohammed, a senior staff scientist at Huawei. “The gap is becoming wider and wider. And all of the solutions we have for solving the problem are not working anymore.”

For the high-end networking space, Huawei sees a clear but challenging path to solve the problem. “We have to punch a tunnel through the memory wall,” Mohammed said. “For networking applications, 2.5D is the preferred solution.”

The roadblocks
The memory bottleneck and resistivity problems in planar devices have fueled the development of stacked 2.5D and 3D chips using through-silicon vias (TSVs), whether those TSVs run through a die or a separate interposer die in 2.5D designs.

Mike Splinter, chairman and chief executive of Applied Materials, said the 2.5D/3D chip market represents a promising segment for the IC industry, but the business will take some time before it reaches mass production. “We’ve always said there will be a slow deployment of 2.5D,” Splinter said.

The 2.5D chip market is progressing somewhat faster than 3D. Several foundries and IC-packaging houses currently provide interposers and workable manufacturing flows to enable 2.5D designs. There are still some gaps in the technology, however.

“2.5D depends on having a stacked memory solution,” said E. Jan Vardaman, president of TechSearch International, a research firm. “The inability to obtain a memory stack is a gating factor. Some people also say the cost for 2.5D is too expensive.”

Test is also an important but sometimes overlooked part of the flow. “The test challenges for 2.5D are very similar to 3D. For die stacking, it is crucial to have each die pre-tested for KGD,” said Bassilios Petrakis, product marketing director at Cadence Design Systems.

“In the case of the interposer, the question often comes up as to whether it needs to be tested for connectivity upfront prior to bonding with other dies. There is also consideration for how to test partially populated interposers as well as multiple die stacks,” Petrakis said. “An example of that would be a logic die that talks to a Wide I/O DRAM and another logic die on top. If the bottom die of the interposer is the most expensive die, you may only want to attach it to an interposer with all other die attached that have been tested good so far. This may be the most economical way to produce good modules. Finally, all dies on interposers must have some form of a wrapper with boundary scan. We prefer the use of IEEE 1500-style wrappers, but we are also able to accommodate the simpler Wide I/O style boundary scan. Special I/O wrap test before die stacking/bounding can detect possible TSV shorts but not opens.”

Another challenge is to find a suitable manufacturing partner. In general, there are two schools of thought—turnkey versus a hybrid approach. TSMC and Samsung provide a turnkey solution, in which the companies provide both the front- and back-end work. In contrast, GlobalFoundries and UMC are sticking with their hybrid approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Both approaches have their advantages and disadvantages. In the turnkey approach, the foundry can assume the responsibility of the supply chain, thereby keeping costs and quality under strict control. The problem with the turnkey method is that some customers are nervous about handing over their sensitive front-end, assembly and test intellectual-property (IP) to a foundry, said Ajit Manocha, chief executive of GlobalFoundries. “We are not a closed fab,” Manocha said. “Customers prefer to take their proprietary information to the OSATS. We are not going to force customers to do the assembly with us.”

Taking the right path
As it turns out, each customer will choose its own path. To simplify its respective supply chains, Altera and Xilinx are working with a limited set of partners. Most others may end up dealing with a more complex supply chain.

Huawei, for example, is working with separate chipmakers, interposer suppliers, foundries, assembly houses and integrators. At present, Huawei is developing its 2.5D ASIC/FPGA device at IME, a Singapore R&D organization. IME has set up a complete front-end production flow using fab gear from Applied Materials. IME also developed its own interposer technology. IME is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR).

Huawei declined to comment on which foundry it will use once it moves into production, but the challenges are obvious. “This could be a logistics nightmare,” said Ron Leckie, president of Infrastructure Advisors, a consulting firm.

Unfazed by the challenges, Huawei believes it must move in a new and radical direction to address the memory bottleneck in the network. “At one time, when you went to a new node, your gains were pretty sharp,” said Huawei’s Mohammed. “Now, every time we go to the next node, the power becomes a challenge and you have to go with larger and larger die sizes.”

The current line of specialized networking memory chips and other components are unable to keep pace. “Commodity memory cannot handle it,” he said. “Serdes was able to help with the bandwidth at one time. But now, the gains are flatter.”

To solve the problem, the company evaluated several options. “A company like Huawei doesn’t jump into a technology. We have to go through many doors before we decide this is a technology we go after,” he said.

Last year, for example, Huawei looked at combining an ASIC and RLDRAMs in a 64mm x 64mm package, he said. After dropping that idea, the company looked at integrating those devices in larger substrates or smaller packages. Those options were scrapped. Then, it looked at combining a bare die FPGA and packaged memory in a $25 module. “It was not leading-edge technology,” he said. “Any one of our competitors could have picked it up.”

Finally, the company decided on 2.5D. 3D is more suited for mobile applications. “The size of our line cards is constant. We want to put more and more items on the line card to make it more functional and effective. 2.5D is a very powerful enabler for that,” he said. “Initially, this is going to be more expensive. But if you combined enough items, there is a strong potential for cost reduction. It also allows us a faster time to market.”

In Huawei’s proposed design, the FPGA from Altera and the memory stack from Tezzaron are situated on a silicon interposer. “Instead of 10 or 20 DDR DRAMs, all of this can be replaced by one Wide IO memory,” he said. “DDR memory performance is so slow. All of this goes away with Wide IO memory, which is only 12mm x 12mm.”

In total, the company’s proposed 2.5D device occupies less space. The bandwidth per watt is at least 30 times better than conventional approaches, he said.

To realize its design, the world’s largest networking equipment company must overcome some major hurdles, namely the KGD issues, the lack of EDA tools and the supply chain. “Hopefully, we can obtain known good dies and bare dies,” he said. “There is good work going on at Cadence, Mentor and others, but this is still an area of concern. There are also some business concerns like who’s responsible and who’s not responsible?”

Ultimately, to make 2.5D/3D a viable solution in the overall market, Huawei advocates another critical piece to the puzzle–collaboration. “We are advocating pre-competitive collaboration. Let’s makes sure the technology succeeds. When the technology can take care of itself, let’s start competing,” he added.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss 3D device challenges and applications with John Lau, a fellow at the Industrial Technology Research Institute (ITRI), a research organization in Taiwan.

SMD: What is ITRI doing in 3D TSVs?
Lau: At ITRI we have developed the world’s first Applied Materials’ 300mm (3D TSV) integration line. The line was completed two years ago. We developed the process from the very beginning to the end. We don’t have products. We are demonstrating the feasibility for 3D TSVs.

SMD: What else is ITRI doing in the arena?
Lau: We also have a consortium call Ad-STAC (Advanced Stacked-System and Application Consortium). We have more than 22 members. We just develop the necessary technologies for 3D integration. The members are UMC, SPIL, Applied Materials, Brewer, Rambus, Cisco and others. In addition to that, we have some 80 people working on EDA. For 3D, EDA is very critical.

SMD: Where is the industry at with 3D TSVs?
Lau: For me, it’s still very early. You still have to bring the OEMs into the mix. The OEMs may say: ‘Oh, I’m interested.’ Then, you still have to wait three to five years. There are two different kinds of OEMs. One is consumer. 3D TSVs are still too expensive for them. However, it could be a different story for high-end, next-generation servers, networking and test and measurement gear.

SMD: Where is a good starting place for 3D?
Lau: Take the Hybrid Memory Cube Consortium. Several months ago, the group announced they would open up the spec by the end of this year. But that’s only for high-end servers, test and measurement, and networking. It’s for very high performance and not for the consumer. They may adopt 3D. But the Hybrid Memory Cube for mobile products? Come on. Of course, we hope 3D can be for the consumer market. In consumer, there are larger volumes.

SMD: What is the biggest challenge for 3D?
Lau: Cost. The consumer market is cost-driven. For the iPhone 5, the semiconductor bill of materials is less than $30. The ASICs and memory are less than $30. Now take Xilinx’s 2.5D FPGA. The CTO from Xilinx recently gave a keynote at Semicon West. His conclusion was that they need to reduce the cost. A 2.5D FPGA is still costly.

SMD: What are the manufacturing challenges?
Lau: Just to make the TSV is no more than 5% of the cost. But if you look at the other steps, you have temporary bonding, back grinding, and others. The biggest issue is thin wafer handling and temporary bonding/debonding. And then you need to debug it.

SMD: Who should make the TSVs? The OSATs or the foundries?
Lau: Xilinx is using 65nm technology for their 2.5D FPGAs. OSATs like ASE don’t have 65nm technology. If they did, they would become another foundry. The OSATs should not make the TSVs. I still say a dummy piece of silicon like an interposer, where the line widths are 3 microns and above, the OSATs can do that. Last year, Amkor said that they are not going to invest a penny to make TSVs. That’s the right direction.

SMD: Why is Wide I/O memory generating so much interest?
Lau: Memory bandwidth. Bandwidth is defined as the amount of data transferred per second. Typical dynamic random access memory has 4-, 8-, 16-, or 32-bit data width to communicate with CPU/logic/SoC and/or the outside world. These are called ×4-, ×8-, ×16-, or ×32-bit I/O. Wide I/O is defined as ×512-bit I/O or 512-bit data width or greater.

SMD: So memory bandwidth is the name of the game?
Lau: The memory bandwidth is proportional to memory I/O data width. For instance, the DDR3–1600 chip has a speed rating of 1600 Mb/s per I/O. If this DDR3-1600 chip has ×32-bit I/O data width, the chip would have a total memory bandwidth of 32 × 1600 = 51,200 Mb/s or 51.2-Gb/s. The larger the data width, the larger the memory bandwidth.

SMD: So where’s the bottleneck?
Lau: The data width is limited by IC packaging technology. With TSV technology, which provides very small via size (5- to 10-μm sizes are common) and pitch (20- to 40-μm pitches are common), a much wider I/O data path, such as 512-bit data width, is more than possible. On the other hand, wire-bonding technology has pad sizes and pitches that are many times larger than those of TSV. In order to achieve a 512-bit data width, the chip size, and thus the cost, has to be increased substantially. This is why TSV is so attractive for memory bandwidth. Let’s say that if we have TSVs run through a 4-DRAM stack with a ×512-bit data path, we could have the same DDR3-1600 chip with a total memory bandwidth of 102.4-GB/s. Of course, this DRAM stack has to interconnect to the logic/SoC in order to get this bandwidth.

By Mark LaPedus
Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing.

One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, Texas.

In addition, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is tweaking its 2.5D/3D foundry strategy. Last year, TSMC announced a controversial turnkey solution. The company not only provides the front-end steps, but also the back-end work traditionally handled by the IC packaging houses. Now, instead of locking in customers with its front-to-back solution, TSMC is rethinking its position.

“We prefer to do it ourselves,” said Morris Chang, chairman and chief executive of TSMC, in a recent conference call. “We have become more flexible to partner with the OSATs.”

Two other vendors, GlobalFoundries and UMC, are sticking with their collaborative approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Another foundry, IBM, has a slightly different strategy. Still to be seen, however, is what Intel and Samsung will do in the arena. And some of the IC packaging houses have given up the notion of doing fine-pitch interposers and through-silicon vias (TSVs). Instead, the OSATs are looking at doing course-pitch TSVs and interposers.

So, in general, there are two prevailing, leading-edge 2.5D/3D foundry models: TSMC’s turnkey solution and the rival collaborative approach. “I think both models will co-exist,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

Foundries go 3D
The memory bandwidth gap and resistivity problems in planar devices have fueled the development of 2.5D/3D chips. But advanced chip stacking has several challenges and is still a few years away from mass production. For example, TSMC will not see “significant revenue” in 2.5D/3D until 2015 or 2016, Chang said.

2.5D/3D technology and the associated supply chain are immature. Manufacturing costs are falling, but there is still a perception that the 3D devices will be prohibitively expensive, said Niranjan Kumar, product marketing manager for TSV programs at Applied Materials.

So far, only a few chipmakers have announced 3D chips. In 2010, Samsung rolled out one of the first 3D DRAMs using a 40nm process and TSVs. Then, last year, Samsung and Micron formed a consortium to develop a serial specification for a 3D DRAM technology called the Hybrid Memory Cube (HMC). Micron will sample HMC devices in 2013. Aimed at high-end applications, HMC will stack DRAM arrays on a logic chip. IBM is making the logic chip based on an SOI substrate.

Another 3D DRAM vendor, Tezzaron, recently has begun shipping its initial parts. But other 3D DRAM schemes, such as Wide I/O, have been delayed due to an assortment of technical issues. Still, the industry is making more progress on the 2.5D front. “The 2.5D era has arrived,” said E. Jan Vardaman, president of TechSearch International, a research firm.

To date, Altera, Cisco, IBM, Huawei and Xilinx have talked about or shipped 2.5D devices using interposers. In fact, Xilinx has shipped the Virtex-7 2000T FPGA, a product based on a 28nm process and a 65nm silicon interposer.

The device itself is built and assembled by TSMC, which refers to its 2.5D/3D turnkey solution as “Chip on Wafer on Substrate” (CoWoS). Using CoWoS, TSMC is also building a rival 2.5D FPGA for Altera. In CoWoS, the chip is attached to the substrate to form the final component. TSMC provides front-end manufacturing, TSV formation, interposers, chip-on wafer bonding, backside thinning, dicing and final test.

CoWoS has been given a lukewarm reception by the IC packaging houses, many of which believe that TSMC is taking a chunk of the backend business away from the OSATs. “For some customers, (CoWoS) works well. It doesn’t work for all customers,” Vardaman said.

TSMC has defended CoWoS, saying that the in-house, turnkey solution enables the foundry to ensure the quality of the chips and the production process. TSMC also assumes responsibility for the supply chain. “Technically, it is progressing well,” TSMC’s Chang said. “We are trying to reduce the costs.”

Beyond 2.5D FPGAs, TSMC recently taped out a Wide I/O device. To enable Wide I/O, the company requires DRAM from a third party. Originally, it was working with Elpida, which is being acquired by Micron. Now, TSMC is working with Micron and SK Hynix.

TSMC’s model may fall flat when customers ask for DRAM from Samsung. TSMC and Samsung are foundry competitors. It’s unlikely that Samsung will hand over DRAM wafers, along with its proprietary IP and test data to TSMC.

In some cases, it makes more sense to follow the collaborative model, where there are fewer conflicts. A customer can use its own logic and/or memory or buy it from a third party. The foundries do the front-end processing, while the OSATs collect and assemble the pieces.

With that scenario in mind, TSMC is warming up to the idea of working with OSATs to give customers more flexibility. TSMC also may be fending off its rivals, which are offering a collaborative approach.

More models

Others are moving full speed ahead with their strategies. Earlier this year, GlobalFoundries installed the tools to create 3D TSV devices on its 20nm platform within its fab in New York. It will handle the “via creation” steps. Then, it will hand off the traditional backend steps, such as temporary bonding/debonding, grinding and test, to the OSATs.

The foundry vendor also devised a low-volume, 2.5D line using 65nm interposers within its fab in Singapore. GlobalFoundries’ challenge is to demonstrate a smooth flow and good product yields at a competitive cost. “It’s going well,” said GlobalFoundries’ McCann. “The question is, can we make this collaborative supply chain model a one-to-one solution? We have to prove this to our customers.”

Another vendor, IBM, has been working on 2.5D/3D for years, including a specialized interposer technology. “IBM is working with Sematech to connect analog converter functions in a logic device with an interleaver IC in IBM’s BiCMOS SiGe technology,” said TechSearch’s Vardeman. “Applications are fiber optic telecom, high-performance RF, test equipment and processing for radar systems.”

The new kid on the foundry block is Tezzaron. In October, the company acquired the former SVTC fab in Austin. R&D foundry SVTC, which recently went bankrupt, originally acquired the fab from Sematech. Now, the fab operates under the name of Novati Technologies. Tezzaron is the sole shareholder in Novati. “We are going to become a 3D foundry,” said Robert Patti, chief technology officer at Tezzaron. “What we are trying to do is provide an open platform for 2.5D and 3D integration.”

Asked if Novati will compete against TSMC and GlobalFoundries, Patti said Novati can work with other foundries and will not compete against them. Novati will continue to serve SVTC’s customers. The Austin fab is a 200mm CMOS line, with 200mm/300mm backend capabilities.

As part of the plan, Tezzaron will shut down its current fab in Singapore and transfer the tools to the Austin fab by early 2013. By Q3 of next year, the company hopes to provide 3,000 wafer starts a week in Austin.

In the 2.5D/3D foundry arena, Novati will offer advanced stacking capabilities, TSVs and interposers. It can provide Tezzaron’s 3D DRAMs or procure third-party logic and memory chips. And Novati will offer both a turnkey and collaborative model. “We are willing to do a full turnkey solution,” Patti said. “I am willing to take the pieces and assemble them.”

The company prefers customers to use its so-called FaStack technology, which makes use of a proprietary bonding and tungsten process. Its 2.5D/3D technology is based on a 40nm process. By late 2013, it will offer a 28nm platform.

While the foundry landscape continues to evolve, several IC packaging houses are rethinking their plans. Some time ago, Taiwan’s Advanced Semiconductor Engineering (ASE) was looking at fine-pitch interposers and TSVs in a “via-last” production flow. “We have an interposer technology that we’ve promoted,” said Rich Rice, senior vice president of sales for North America at ASE. “We are not sure about the market acceptance.”

As it turns out, ASE discovered that leading-edge TSV and interposer work belongs in the foundries and not at the OSATs. “I think poking holes in silicon is mostly a foundry business,” he said at a recent event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

On the other hand, ASE and STATS are looking at course-pitch interposers and TSVs for niche applications like MEMS and RF. The OSATs will also play a major role in fine-pitch 2.5D/3D by offering the critical backend work.

TSMC and its turnkey model will not take all of the backend business away from the OSATs. TSMC is still going up the learning curve in the backend and may find the work a headache in the long run. “This is something we do day in and day out,” Rice added.