By Ed Sperling
After years of talking about equivalent pricing, technical advantages and consistent processes, silicon on insulator finally appears to be making significant inroads—but not necessarily in ways, places, or even at process nodes where it initially was predicted to gain ground.

What’s driving at least some of this change is the semiconductor industry’s progression toward stacked die, where commercially available die will be produced in whatever process and on whatever substrate makes the most sense for the manufacturer. What wins the socket—or at least the layer or space in the package—will be price, energy efficiency and performance, although not necessarily in that order. In most cases, however, that means new materials rather than bulk CMOS.

Consider the Hybrid Memory Cube, for example. While the majority of attention being paid to the 3D memory architecture is at the DRAM level, the logic base layer—in this case made by IBM—uses an SOI substrate. And while the initial application is for enterprise applications, where high performance and low power are critical and pricing is less of an issue, there already are discussions underway between Micron and a number of other vendors beyond just the data center.

Scott Graham, general manager of hybrid memory at Micron, said the next generation of the HMC will be in production by the end of next year, with volume applications using 3D-ICs with TSVs in 2015 or 2016. But he said the existing HMC architecture also can be attached to FPGAs, either in a vertical stack or in a 2.5D configuration. The result is that SOI becomes an integral part of 2.5D and 3D stacks, even if some of the other pieces use different materials.

“You can attach the cubes to each other or to FPGAs,” said Graham. “We’re looking at a variety of flexible architectures and protocols.”

Having an additional layer of insulation is a bonus in that architectural arrangement, as well, to buffer against a variety of physical effects ranging from noise to heat—as long as the heat doesn’t get trapped inside a device. So far, the existing architectures allow for heat to escape through exposed sides of the device. In stacked die, getting the heat out requires a variety of architectural approaches ranging from using TSVs as chimneys to using more exotic and expensive approaches such as liquid cooling within a die with microfluidics.

From planar to stacked die
SOI—as well as other substrate materials—are showing up in planar devices, as well. Companies wrestling with a compendium of physical effects at the leading edge of Moore’s Law say that for most applications new materials will be necessary going forward.

Intel remains the poster child of bulk CMOS. It steadfastly has resisted changing from bulk CMOS. But Intel’s architecture also is much more regular and redundant than most others being developed in the IC world. Systems on chip have many more irregular subsystems, which may or may not be on at any given time, and which frequently generate heat, electromagnetic interference and noise in an inconsistent manner that in some cases is determined by user preferences. That causes some parts of the chip to heat up while others remain cool, and with gate oxides now measured in Angstroms additional insulation is considered a very good thing.

Solving all of those problems with guardbanding, the necessary architectural changes, and being able to obtain sufficient yield are difficult, time-consuming and expensive.

“The cost issue is a tough one to deal with from a technology point of view,” said Chenming Hu, professor at UC Berkeley who is considered the father of the finFET. “I believe the world be willing to pay more if none of the semiconductor companies can continue to slash prices. And from a performance/power consumption perspective, I feel quite confident this industry will continue to grow. In the immediate future, finFETS and UTB/ET/FD-SOI are very exciting technologies.”

STMicroelectronics already has begun productizing FD-SOI at 28nm. “We are in the low-power SoC space, and particularly with our subsidiary ST-Ericsson in the mobile computing space, we were looking for a solution that could provide differentiation in terms of efficiency,” said Philippe Magarshack, ST’s corporate vice president of design enablement and services. “We identified planar SOI as the next step going forward. We also identified with our customers what would be the sweet spot for our customers. We had working test chips earlier this year that confirmed our decision to move forward. Our decision was to put a product on the market as soon as possible for the next-generation applications processor.”

He said that one significant advantage of using SOI is the ability to polarize the back edge. “There is more design involved, but we get a 20% boost in efficiency right off the bat. With back-gate biasing you get 30% to 35% boost at high Vdd, and 80% boost at low Vdd. We have use cases in cell phones where the battery life is extended by 30% to 40%. This is a significant benefit.”

IBM holds a similar view, particularly at 20nm.

“We see this really addressing two areas in the SoC space,” said Gary Patton, vice president of IBM’s Semiconductor Research and Development Center “One is that the cost of migrating designs into the next technology node is becoming extremely expensive. The ability to take 28nm technology and do a fairly straightforward migration to FD-SOI and get an immediate performance boost is extremely attractive. But the value proposition of 20nm planar technology has been disappointing for many customers both in terms of cost, because of double patterning, as well performance. Being able to apply FD-SOI to 20nm significantly enhances that value proposition.”

The future
The combination of finFETS plus different substrates provides a couple knobs to turn to reduce leakage and minimize heat. Add that to stacked die, where bigger pipes require less power to drive signals over shorter distances, and the picture becomes even more appealing.

As Micron’s Graham noted, SOI is just a first step in what will likely be a much more rational use of materials to solve very specific problems in stacked die. SOI is an important material, but it is just one of many now under consideration. Nevertheless, it does solve problems for at least a couple more process nodes and in stacked configurations, and at this point most leading edge companies say it is the least-expensive proven solution.

By Mark LaPedus
The semiconductor industry is currently making a major transition from conventional planar transistors to finFETs starting at 22nm.

The question is what’s next? In the lab, IBM, Intel and others have demonstrated the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of steam, there are no less than 18 different next-generation candidates that could one day replace today’s CMOS-based finFET transistors.

But even the large companies with deep pockets don’t have the time or resources to work on all technologies. “We can’t pick 18,” said Mike Mayberry, vice president and director of components research in the Technology and Manufacturing Group at Intel Corp. “We will develop only a few of them.”

Mayberry said the eventual winners and losers in the next-generation transistor race will be determined by cost, manufacturability and functionality. “The best device is the one you can manufacture,” he said.

In fact, the IC industry is already weeding out the candidates. In 2005, the Semiconductor Research Corp. (SRC), a chip R&D consortium, launched the Nanoelectronics Research Initiative (NRI), a group that is researching futuristic devices capable of replacing the CMOS transistor in the 2020 timeframe. NRI member companies include GlobalFoundries, IBM, Intel, Micron and TI.

So far, the NRI has narrowed down and identified a handful of serious contenders: gate-all-around, silicon nanowires, tunnel field-effect transistors (TFETs), carbon nanotubes, graphene devices, and bilayer pseudo-spin field-effect transistors (BiSFETs).

It’s still too early to determine which future transistor candidate will prevail, said Steven Hillenius, executive vice president of the SRC. “There is still no consensus,” Hillenius said, “but we’ve gone from 20 or so potential devices down to less than 10.”

The finFET and beyond
For now, the industry is banking on the finFET transistor to enable IC scaling for the foreseeable future. The current thinking is that today’s finFET will likely scale at least two generations down to 10nm, said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V or other materials to provide a mobility boost, Kengeri said. It’s too early to predict a winner, as “nothing has been settled,” he added.

Indeed, the future is cloudy at and beyond 10nm. According to the 2011 ITRS roadmap, there are a dizzying array of next-generation transistor options on the table: III-V channel replacement finFETs, carbon nanotube FETs, graphene nanoribbon FETs, nanowire FETs, tunnel FETs, spin FETs, IMOS, negative gate capacitance FETs, NEMS switches, atomic switches, MOTT FETs, spin wave devices, nanomagnetic logic, excitonic FETs, BiSFETs, spin torque majority logic gate and all spin logic.

The futuristic candidates likely will require new materials, manufacturing flows and design methodologies. At the SRC, there is one basic criterion to help narrow down the playing field: “The promising new structures are the ones you can put in the current manufacturing flow. The new materials would be used in conjunction with what we are using now,” said SRC’s Hillenius.

For that reason, one transistor candidate has emerged as the favorite in the race. “At this point, the tunnel FET looks like the best option,” said Chenming Calvin Hu, professor of microelectronics at the University of California at Berkeley. Using III-V materials for the channels, TFETs potentially could extend CMOS. Claiming eight times the performance of today’s MOSFETs, TFETs enable a steeper sub-threshold slope less than 60 mV/decade. In TFET, a tunnel barrier is created at the source- channel contact in order to increase the drive current of the transistor.

“It’s likely that the industry will stay with finFETs or tri-gates for the 22nm and 14nm nodes. The earliest introduction of III-V MOSFETs is likely is at the 10nm node. This implies that III-V TFETs will appear no sooner than the 7nm technology node,” said Suman Datta, professor of electrical engineering at Pennsylvania State University.

In the lab, Intel has shown TFETs based on III-V materials like InGaAs. “Penn St. and Notre Dame have been able to use staggered and broken gap tunnel junctions in In(Ga)As/Ga(As)Sb TFETs to demonstrate competitive on-current in experimental devices. These TFETs have all been n-channel demonstrations. Very little work has been toward p-channel TFETs and the next challenge would be the demonstration of steep switching p-channel TFET for complementary TFET logic,” Datta said.

“The biggest barrier is the introduction of III-V compound semiconductors within a state-of-the-art silicon fab. III-V islands need to be grown selectively on 300mm, or by that time on 450mm substrates, with low defect count using a high volume manufacturing technique,” Datta said.

Besides TFETs, silicon nanowires also could be classified as “an extension to the finFET,’’ said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. Silicon nanowire field-effect transistors (FETs) are structures in which the conventional channel is replaced with tiny nanowires.

Nanowires also enable what’s considered to be the ultimate solution in the IC industry: gate-all-around (GAA) finFETs. GAA FETs can have two or more gates, which are wrapped around by a nanowire channel. In a recent paper, Harvard University and Purdue University demonstrated a gate-all-around III-V MOSFET. The device itself boasts 1, 4, 9 or 19 nanowire channels. One of the key fabrication steps is a controlled release process, which is used to form the InGaAs nanowire channels.

“We would likely see GAA devices two to three generations after tri-gate/finFET technology,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “The biggest challenge for GAA devices with III-V channels is how to fabricate ultra-small nanowires with high mobility surfaces and low interface trap densities by a top-down technology. Other challenges include how to form low resistance contacts to these nanowires and how to reduce variations of the GAA devices.”

Carbon nanotubes and graphene
TFETs, nanowire FETs and GAA are arguably the most straightforward extensions to CMOS. Two other options, carbon nanotubes and graphene-based devices, are promising but more exotic approaches. Carbon nanotubes are grown on full wafers and aligned in one direction. They are subsequently transferred to a target substrate multiple times. IBM, for one, has demonstrated sub-10nm carbon nanotubes.

Carbon nanotube FETs (CNFETs) are “the only FET that is projected to outperform the 11nm node ITRS target,” said H. S. Philip Wong, professor of electrical engineering at Stanford University, in a recent paper. CNFETs, according to Wong, face three major challenges: aligned density; stable p- and n-type doping on the same wafer; and low resistance metal to contact at short contact lengths.

In contrast, graphene consists of one-atom-thick planar sheets, which are packed in honeycomb crystal lattice structures. The technology is expensive and difficult to put into manufacturing. And it doesn’t have a band gap, meaning it can’t be turned off in a system.

Still, there is interest in using graphene as a channel replacement material. IBM, for one, is looking at analog and RF applications for graphene FETs (GFETs). The company has demonstrated a GFET running at 155-GHz with 40nm channel lengths.

In another approach, the University of Texas at Austin has been developing the BiSFET, which is said to have 1,000 times lower power consumption than CMOS. In this device, a p- and an n-type layer of graphene are separated by a dielectric tunnel barrier. Each graphene layer has a metallic contact and is electrostatically coupled to a gate electrode.

“The device is still in an R&D phase. While we have theoretically shown that it should work, we are still struggling to demonstrate functionality in the lab. So at this point, it is premature to think of large scale production,” said Sanjay Banerjee, professor of electrical and computer engineering and director of the Microelectronics Research Center at the University of Texas at Austin.

Researchers are also looking at other technologies. For example, all spin logic (ASL) is gaining interest. ASL uses magnets to represent non-volatile binary data, while the communication between magnets is achieved using spin currents.

Despite the promising research for spin logic and other futuristic devices, the industry faces many challenges to find the right candidate. “Predicting what lies ahead is fraught with peril as our ability to see is dependent on where and how we look,” Intel’s Mayberry said.

New materials to herd photons
Used in communication systems, optical networks employ isolators to keep light from reflecting backwards. Isolators also absorb photons, thereby reducing a signal in a system.

All of that may be unnecessary in the future, however. MIT, Zhejiang University in China, and the University of Texas at Austin have devised a new “metamaterial” that keeps photons moving in only one direction. This, in turn, could pave the way toward chips that move data with light.

To prevent microwaves passing through it from reflecting backward, a new 'metamaterial' uses antennas of alternating orientations (top) that are connected by amplifier circuits (bottom). Source: MIT

Electromagnetic materials that lack so-called local time-reversal symmetry could enable these types of chips. Gyrotropic materials, for one, are the most promising.

Using such materials, researchers have devised a “metamaterial.” They also have made use of antennas of alternating orientations, which are connected by amplifier circuits. The antennas are embedded in a pair of circuit boards. The direction of current flow through the circuits determines the direction of the electromagnetic waves.

Electron interactions spotted in graphene
Graphene, a promising material for future transistors, consists of one-atom-thick planar sheets that are packed in honeycomb crystal lattice structures. But graphene is complex and doesn’t have a band gap, meaning it can’t be turned off in a system.

Researchers with the U.S. Department of Energy’s Lawrence Berkeley National Laboratory and the University of California at Berkeley are claiming a new breakthrough in this arena— they have demonstrated the electron interactions in graphene.

Using a scanning tunneling microscope (STM), researchers observed gated devices consisting of a graphene layer deposited atop boron nitride flakes. The flakes were placed on a silicon dioxide substrate.

The response of ultrarelativistic electrons in graphene to Coulomb potentials created by cobalt trimers was observed to be signficantly different the response of non-relativistic electrons in traditional atomic and impurity systems. Source: Lawrence Berkeley National Laboratory.

Researchers observed how electrons and holes respond to a charged impurity placed on a gated graphene device. The charged impurities were cobalt trimers constructed on graphene.

“Theorists have predicted that compared with other materials, electrons in graphene are pulled into a positively-charged impurity either too weakly, the subcritical regime; or too strongly, the supercritical regime,” said Michael Crommie, a physicist who holds joint appointments with Berkeley Lab’s Materials Sciences Division and UC Berkeley’s Physics Department.

“In our study, we verified the predictions for the subcritical regime and found the value for the dielectric to be small enough to indicate that electron–electron interactions contribute significantly to graphene properties. This information is fundamental to our understanding of how electrons move through graphene,” he added.

SWAN dives into study of molecules
Researchers from Iowa State University and Ames Laboratory have developed a new microscope technology that enables the study of single biological molecules.

Called standing wave axial nanometry (SWAN), the technology combines atomic force and optical microscope technologies. SWAN is able to image the axial location of a single nanoscale fluorescent object down to 3.7nm.

A standing wave, generated by positioning an atomic force microscope tip over a focused laser beam, is used to excite the fluorescence of an object. The axial position is determined from the phase of the emission intensity.

Researchers used SWAN to measure the orientation of single DNA molecules of different lengths. The technology can be used in the medical and other fields.

—Mark LaPedus

By Mark LaPedus
As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model.

Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the foundries are not only manufacturing partners, but there is a deeper collaboration within a customer’s design team.

In fact, given the variability challenges with finFETs, there is a school of thought that chipmakers must reside at the same physical location as their foundry partners’ fabs to ensure that design and manufacturing are on the same page. Otherwise, according to some experts, the chances for first-silicon success are shaky.

For this reason and others, Taiwan Semiconductor Manufacturing Co. (TSMC) may take the “virtual IDM” model a step further. TSMC is considering a plan to build separate fabs for individual companies. And as part of its strategy, TSMC has accelerated its finFET roadmap.

Rival GlobalFoundries is considering a plan to offer dedicated modules within a fab for customers. And taking another approach, United Microelectronics Corp. has floated an equity placement under which companies can buy a 10% stake in UMC. UMC also has licensed IBM’s 20nm and finFET technologies.

Another foundry vendor, Samsung Electronics Co, has perhaps set the tone for the industry: It has already built a dedicated fab for Apple. And separately, in a surprise move, fabless chipmaker Qualcomm is considering the idea of building its own fab to gain better control of the manufacturing process.

Qualcomm CEO “Paul Jacobs has discussed it openly of late,” said G. Dan Hutcheson, president of VLSI Research. “Qualcomm certainly has the revenues to build its own fab and start making its own wafers. The chance of success is still low. It would cost at least three times, and possibly as much as five times, to successfully get your first fab to viable production, or approximately $15 billion to $25 billion. In other words, it would be an out-of-body experience for the management team that tries it.”

Sea of change
In any case, there could be a sea of change taking place in the traditional fabless-foundry model. “The traditional foundry model, where you throw a GDS2 file over the wall, no longer works,” said Mojy Chian, senior vice president of design enablement at GlobalFoundries. “We have to work closer with the fabless guys. New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market. In fact, the collaboration should start two to two-and-a-half years ahead of tape out.”

In the late 1980s, the pure-play foundries emerged, which spawned a plethora of fabless companies. One of the drawbacks with the fabless-foundry model is that the design houses and foundries sometimes work in silos and do not cooperate. In some cases, fabless vendors will throw a clunky design “over the wall” to the foundries, which are still expected to make the chip on time. This brute-force methodology has experienced mixed success.

The fabless and foundry firms began to change their ways at the 130nm node amid soaring IC design and manufacturing costs. “130nm is when process and design began to be recoupled. The result was the rise of DFM, which didn’t exist before then,” said VLSI’s Hutcheson.

Then, starting in the early part of this decade, several foundries billed themselves as “virtual IDMs,” claiming they would work more closely with customers. But some of those efforts have fallen short of expectations. “The leading fabless suppliers got hurt badly when the leading foundries hadn’t dealt well with variability at 40nm, and more recently, with design-manufacturing interactive yield losses at 28nm,” Hutcheson said.

Now, as the IC industry moves toward the 20nm node and beyond, the foundries have become more serious about embracing the “virtual IDM” model and for good reason: The stakes are higher. At 130nm, a fab was $1.45 billion, process R&D costs were $250 million, and design costs were $15 million. But at 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million.

Simply put, the traditional foundry model must evolve. “You can’t do it in silos,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “The key is to have a tighter integration between product design and manufacturing.”

This is especially true in the finFET era. Intel has moved finFETs into production at 22nm. Given the variability issues, the foundries face challenges to put finFETs into production at 14nm.

Intel and the foundries are in the bulk finFET camp. But to make the finFET transition easier, the foundries should look at silicon-on-insulator (SOI) technology, said Chenming Calvin Hu, professor of electrical engineering at the University of California at Berkeley. “We are going to see (both bulk and SOI finFETs) in volume manufacturing,” Hu said. “[SOI] is easier. The supply chain is the one thing that manufacturers need to be assured of.”

New business models
On the business side, the industry could take one of two routes: Maintain the fabless-foundry status quo or move toward a “virtual IDM” model. Morris Chang, chairman and chief executive of TSMC, sees yet another model: Build dedicated fabs or joint-venture fabs for larger customers.

“We made our mark serving many customers (in multiple fabs). We will retain that capability,” Chang said during a recent conference call. “There are going to be larger customers. So it makes complete sense to have one dedicated fab, or more than one fab, for one customer.”

GlobalFoundries, meanwhile, is considering a slightly different model. “This is hypothetical,” said GlobalFoundries’ Kengeri. “Within a fab, we have modules. If one of our customers wants a dedicated module, it’s open for discussion.”

In that arrangement, a chipmaker may have to share the risk and cost. And it must make economic sense. Clearly, though, Apple is one candidate for a dedicated fab. In fact, Samsung already has built a dedicated fab for Apple in Austin, Texas.

Altera, Broadcom, Nvidia, Qualcomm and Xilinx are also possible candidates to occupy part or all of a fab. Qualcomm, for one, has the volumes and already is sourcing parts from all of the leading-edge foundries to keep up with 28nm demand.

Qualcomm’s multi-foundry sourcing strategy “is a very expensive approach today, as designs don’t port to multiple foundries like they used to,” said VLSI’s Hutcheson. “Yields are far more difficult to obtain at these advanced nodes, and splitting production across multiple fabs means either less relevant data per learning cycle or longer learning cycle times. That results in longer time-to-money and higher costs, making going the IDM route seem more attractive.”

It’s unlikely that Qualcomm will build its own fab, but it is possible it will end up with a joint venture fab with a foundry. In addition, Qualcomm and others would like the foundries to speed up their process roadmaps. The foundries are falling behind Intel, which also offers foundry services on a limited basis.

TSMC, for one, plans to accelerate its finFET efforts. Originally, TSMC planned to introduce finFETs at 14nm by late 2014. Now, the company has no plans to brand its finFETs at 14nm, but rather it will introduce the technology at 16nm. TSMC’s finFET “risk production” is slated for the end of 2013 or early 2014, with production scheduled for the second half of 2015, Chang said.

TSMC is not banking on extreme ultraviolet (EUV) lithography for 16nm. “We are very confident we can make 16nm finFETs without EUV,” he said. “I think EUV will come in at 10nm.”

To accelerate 450mm fabs and EUV in the market, Intel recently inked a deal with ASML. ASML has also enabled customers to take a 25% stake in the company. Intel plans to acquire up to a 15% stake in ASML.

TSMC and Samsung are also negotiating with ASML to take separate stakes in ASML. Taking a page from the ASML-Intel deal, UMC separately floated private equity shares under which strategic partners can take up to a 10% stake in UMC.

This represents a change for UMC. The company has developed its own processes and has shied away from forming strategic alliances. UMC has controlled its own destiny, but it also has fallen behind its rivals.

To jumpstart its process roadmap, UMC recently licensed 20nm and finFET technology from IBM. UMC’s finFET technology is reportedly a 14nm or 16nm front-end, with 20nm backend. “For UMC to do a finFET from scratch is very challenging,” said Shih-Wei Sun, chief executive of UMC, in a recent conference call. “This will kick start our finFET efforts.”

GlobalFoundries and Samsung have yet to change their finFET strategies. GlobalFoundries still plans to roll out a finFET at the 14nm node in the fourth quarter of 2014 or first quarter of 2015, according to Kengeri.

Researchers study behavior of ferroelectrics
Today’s memories based on ferroelectric materials are difficult to scale and are mainly used for niche applications like SRAM replacements in battery-backed systems.

The U.S. Department of Energy’s Brookhaven National Laboratory, Lawrence Berkeley National Laboratory and others have revealed details about the atomic structure and behavior of ferroelectric materials. This could lead the way to next-generation or universal memories based on ferroelectric materials.

Brookhaven has devised a technique called electron holography to capture images of the electric fields created by the ferroelectric materials’ atomic displacement. The laboratory also demonstrated a method for identifying the behavior and stability of ferroelectrics.

Direct polarization images of individual ferroelectric nano cubes captured with electron holography. The fringing field, or “footprint” of electric polarization, can be seen clearly in (a), but it vanishes when the material is subjected to high temperatures (b). The lower images show that no fringing field can be observed before application of electricity (c), but a clear field emanates after current is applied (d).

Understanding the atomic-scale properties will help guide implementation of these particles. “Electron holography is an interferometry technique using coherent electron waves,” said Brookhaven physicist Myung-Geun Han. “When electron waves pass through a ferroelectric sample, they are influenced by local electric fields, yielding a so-called phase-shift. The interference pattern between the electrons that pass through electric fields and those that don’t creates what’s called an electron hologram, which allows us to directly ‘see’ those local electric fields around individual ferroelectric nano particles.”

With this technique, researchers revealed that the electric polarity could remain stable for individual ferroelectric materials. This means that each nanoparticle can be used as a data bit.
“Properly used, ferroelectrics could ramp up memory density and store an unparalleled multiple terabytes of information on just one square inch of electronics,” Han said. “This brings us closer to engineering such devices.”

The ferroelectric nanoparticles tested, semiconducting germanium telluride and insulating barium titanate, were engineered at Lawrence Berkeley National Laboratory. They were brought to Brookhaven Lab for the electron holography experiments. Additional experiments using x-ray diffraction were conducted at Argonne National Laboratory’s Advanced Photon Source.

The University of California at Berkeley, the University of New Orleans and Central Michigan University also collaborated with the work. The research was funded by Department of Energy’s Office of Science. The research will be published in Nature Materials.

Researchers devise molecular spintronic devices
A molecular switch can be used to store information in a single molecule. Adding spin functionality to molecular switches is a key technology to enable a next-generation memory device.
The research was conducted by Karlsruhe Institute of Technology, Institut de Physique et Chimie des Matériaux de Strasbourg, Chiba University and Synchrotron SOLEIL.

To enable these devices, researchers devised spin-crossover complexes. This consists of a transition metal ion that can be switched between a low-spin (LS) and a high-spin (HS) state by external stimuli. The two configurations may lead to different conductances.

As part of the process, researchers made use of individual Fe-phen molecules at low temperature with high lateral and energy resolution. The Fe-phen molecules, which were adsorbed onto a copper surface, exhibited the coexistence of HS and LS states.

But the strong coupling of the materials to the substrate prevents a spin state from being written electrically. Introducing an interfacial copper nitride layer allows switching between the HS and the LS state. The combined changes in conductance and spin state demonstrate how to confer memristive to spintronic properties, realizing multifunctional spintronic capacity in single molecules.

The paper has been published in Nature Communications.

—Mark LaPedus