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Posts Tagged ‘tungsten’

Applied Materials Fields Cobalt Solution for MOL

Thursday, June 7th, 2018


By Pete Singer, Editor-in-Chief

Applied Materials has introduced a set of processes that enable cobalt to be used instead of tungsten and copper for contacts and middle-of-line interconnects. Higher levels of metal, which typically have wider dimensions, will still employ copper as the material of choice, but at more advanced nodes, cobalt will likely be the best option as linewidths continue to shrink. Tungsten will still be used at the gate contact level.

To enable the use of cobalt, Applied has combined several materials engineering steps – pre-clean, PVD, ALD and CVD – on the Endura® platform. Moreover, Applied has defined an integrated cobalt suite that includes anneal on the Producer® platform, planarization on the Reflexion® LK Prime CMP platform and e-beam inspection on the PROVision™ platform. The process flow is shown in FIGURE 1.

While challenging to integrate, cobalt brings significant benefits to chips and chip making: lower resistance and variability at small dimensions; improved gapfill at very fine dimensions; and improved reliability. The move to cobalt, which is underway at Intel, GlobalFoundries and other semiconductor manufacturing companies, is the first major change in materials used as conductors since copper dual damascene replaced aluminum in 1997. “You don’t see inflections this large very often,” said Jonathan Bakke, global product manager, Metal Deposition Products at Applied Materials. “This is a complete metallization change.”

At IEDM last year, Intel said it would use cobalt for its 10nm logic process for several of the lower metal levels, including a cobalt fill at the trench contacts and cobalt M0 and M1 wiring levels. The result was much-improved resistivity– a 60 percent reduction in line resistance and a 1.5X reduction in contact resistance – and improved reliability.

Today, critical dimensions of contacts and interconnects are about 20 nm, plus or minus a few nanometers depending on the customer and how it’s defined. “As you get smaller – and you typically get about 30% smaller with each node — you’re running out of room for tungsten. Copper is also facing challenges in both gap fill and electromigration,” Bakke said.

As shown in FIGURE 2, cobalt has advantages over copper when dimensions shrink to about 10nm. They are presently at 30 nm. It’s not yet clear when that cross-over point will arrive, but decisions will be based on how much resistivity and electromigration improvement can be gained.

Applied Materials started developing cobalt-based processes in the mid-2000s, and released the Volta CVD Cobalt system in 2013, which was designed to encapsulate copper interconnects in cobalt, which helped improve gap fill and electromigration. “It was shortly thereafter that we started depositing thick CVD cobalt films for metalization. We quickly realized that there’s a lot of challenges with doing this kind of metalization using cobalt because of its unique properties,” Bakke said. Cobalt can be reflowed and recrystallized, which eliminates seams and leads to larger grain sizes, which reduces resistivity. “We started looking at things like interfaces, adhesion and microstructure of the cobalt to make sure that it was an efficient material and it had very low resistance and high yield for in-device manufacturers,” he added. One perfected, it took several years before the processes were fully qualified at customers. “This year is when we start to see proliferation and expect HDM manufacturing of real devices with cobalt,” Bakke said.

Leti’s CoolCube 3D Transistor Stacking Improves with Qualcomm Help

Wednesday, April 27th, 2016

By Ed Korczynski, Sr. Technical Editor

As previously covered by Solid State Technology CEA-Leti in France has been developing monolithic transistor stacking based on laser re-crystallization of active silicon in upper layers called “CoolCube” (TM). Leading mobile chip supplier Qualcomm has been working with Leti on CoolCube R&D since late 2013, and based on preliminary results have opted to continue collaborating with the goal of building a complete ecosystem that takes the technology from design to fabrication.

“The Qualcomm Technologies and Leti teams have demonstrated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.” As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs to accelerate adoption.

Olivier Faynot, micro-electronic component section manager of CEA-Leti, in an exclusive interview with Solid State Technology and SemiMD explained, “Today we have a strong focus on CMOS over CMOS integration, and this is the primary integration that we are pushing. What we see today is the integration of NMOS over PMOS is interesting and suitable for new material incorporation such as III-V and germanium.”

Table: Critical thermal budget steps summary in a planar FDSOI integration and CoolCube process for top FET in 3DVLSI. (Source: VLSI Symposium 2015)

The Table shows that CMOS over CMOS integration has met transistor performance goals with low-temperature processes, such that the top transistors have at least 90% of the performance compared to the bottom. Faynot says that recent results for transistors are meeting specification, while there is still work to be done on inter-tier metal connections. For advanced ICs there is a lot of interconnect routing congestion around the contacts and the metal-1 level, so inter-tier connection (formerly termed the more generic “local interconnect”) levels are needed to route some gates at the bottom level for connection to the top level.

“The main focus now is on the thermal budget for the integration of the inter-tier level,” explained Faynot. “To do this, we are not just working on the processing but also working closely with the designers. For example, depending on the material chosen for the metal inter-tier there will be different limits on the metal link lengths.” Tungsten is relatively more stable than copper, but with higher electrical resistance for inherently lower limits on line lengths. Additional details on such process-design co-dependencies will be disclosed during the 2016 VLSI Technology Symposium, chaired by Raj Jammy.

When the industry decides to integrate III-V and Ge alternate-channel materials in CMOS, the different processing conditions for each should make NMOS over PMOS CoolCube a relatively easy performance extension. “Three-fives and germanium are basically materials with low thermal budgets, so they would be most compatible with CoolCube processing,” reminded Faynot. “To me, this kind of technology would be very interesting for mobile applications, because it would achieve a circuit where the length of the wires would be shortened. We would expect to save in area, and have less of a trade-off between power-consumption and speed.”

“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological development in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”


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