Posts Tagged ‘transistor’
By Ed Korczynski, Sr. Technical Editor
As previously covered by Solid State Technology CEA-Leti in France has been developing monolithic transistor stacking based on laser re-crystallization of active silicon in upper layers called “CoolCube” (TM). Leading mobile chip supplier Qualcomm has been working with Leti on CoolCube R&D since late 2013, and based on preliminary results have opted to continue collaborating with the goal of building a complete ecosystem that takes the technology from design to fabrication.
“The Qualcomm Technologies and Leti teams have demonstrated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.” As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs to accelerate adoption.
Olivier Faynot, micro-electronic component section manager of CEA-Leti, in an exclusive interview with Solid State Technology and SemiMD explained, “Today we have a strong focus on CMOS over CMOS integration, and this is the primary integration that we are pushing. What we see today is the integration of NMOS over PMOS is interesting and suitable for new material incorporation such as III-V and germanium.”
The Table shows that CMOS over CMOS integration has met transistor performance goals with low-temperature processes, such that the top transistors have at least 90% of the performance compared to the bottom. Faynot says that recent results for transistors are meeting specification, while there is still work to be done on inter-tier metal connections. For advanced ICs there is a lot of interconnect routing congestion around the contacts and the metal-1 level, so inter-tier connection (formerly termed the more generic “local interconnect”) levels are needed to route some gates at the bottom level for connection to the top level.
“The main focus now is on the thermal budget for the integration of the inter-tier level,” explained Faynot. “To do this, we are not just working on the processing but also working closely with the designers. For example, depending on the material chosen for the metal inter-tier there will be different limits on the metal link lengths.” Tungsten is relatively more stable than copper, but with higher electrical resistance for inherently lower limits on line lengths. Additional details on such process-design co-dependencies will be disclosed during the 2016 VLSI Technology Symposium, chaired by Raj Jammy.
When the industry decides to integrate III-V and Ge alternate-channel materials in CMOS, the different processing conditions for each should make NMOS over PMOS CoolCube a relatively easy performance extension. “Three-fives and germanium are basically materials with low thermal budgets, so they would be most compatible with CoolCube processing,” reminded Faynot. “To me, this kind of technology would be very interesting for mobile applications, because it would achieve a circuit where the length of the wires would be shortened. We would expect to save in area, and have less of a trade-off between power-consumption and speed.”
“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological development in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”
By Ed Korczynski, Sr. Technical Editor, Solid State Technology/SemiMD
In the spring meeting of the Materials Research Society held recently in San Francisco, Symposium A: Emerging Silicon Science and Technology included presentations on controlling the structure of crystalline spheres and thin-films. Such structures could be used in future complementary metal-oxide semiconductor (CMOS) devices and in photonic circuits built using silicon.
Alexander Gumennik, et al., from the Massachusetts Institute of Technology, presented on “Extraordinary Stress in Silicon Spheres via Anomalous In-Fiber Expansion” as a way to control the bandgap of silicon and thus enable the use of silicon for photodetection at higher wavelengths. A silica fiber with a crystalline silicon core is fed through a flame yielding spherical silicon droplets via capillary instabilities. Upon cooling the spheres solidify and expand against the stiff silica cladding generating high stress conditions. Band gap shifts of 0.05 eV to the red (in Si) are observed, corresponding to internal stress levels. These stress levels exceed the surface stress as measured through birefringence measurements by an order of magnitude, thus hinting at a pressure-focusing mechanism. The effects of the solidification kinetics on the stress levels reached inside the spheres were explored, and the experimental results were found to be in agreement with a pressure-focusing mechanism arising from radial solidification of the spheres from the outer shell to the center. The simplicity of this approach presents compelling opportunities for the achievement of unusual phases and chemical reactions that would occur under high-pressure high-temperature conditions, which therefore opens up a pathway towards the realization of new in-fiber optoelectronic devices.
Fabio Carta and others from Columbia University working with researchers from IBM showed results on “Excimer Laser Crystallization of Silicon Thin Films on Low-K Dielectrics for Monolithic 3D Integration.” This research supports the “Monolithic 3D” (M3D) approach to 3D CMOS integration as popularized by CEA-LETI, as opposed to the used of Through Silicon Vias (TSV). M3D requires processing temperature below 400°C if copper interconnects and low-k dielectric will be used in the bottom layer. Excimer laser crystallization (ELC) takes advantage of a short laser pulse to fully melt the amorphous silicon layer without allowing excessive time for the heat to spread throughout the structure, achieving large grain polycrystalline layer on top of temperature sensitive substrates. The team crystallized 100nm thick amorphous silicon layers on top of SiO2 and SiCOH (low-k) dielectrics. SEM micrographs show that post-ELC polycrystalline silicon is characterized by micron-long grains with an average width of 543 nm for the SiO2 sample and 570 nm for the low-k samples. A 1D simulation of the crystallization process on a back end of line structure shows that interconnect lines experience a maximum temperature lower than 70°C for the 0.5 μm dielectric, which makes ELC on low-k a viable pathway for achieving monolithic integration.
Seiji Morisaki, et al., from Hiroshima Univ, showed results for “Micro-Thermal-Plasma-Jet Crystallization of Amorphous Silicon Strips and High-Speed Operation of CMOS Circuit.” The researchers used micro-thermal-plasma-jet (µ-TPJ) for zone melting recrystallization (ZMR) of amorphous silicon (a-Si) films to form lateral grains larger than 60 µm. By applying ZMR on a-Si strip patterns with widths <3 µm, single liquid-solid interfaces move inside the strips and formation of random grain boundaries (GBs) are significantly suppressed. Applying such strip patterns to active channels of thin-film-transistors (TFTs) results in a demonstrated field effect mobility (µFE) higher than 300 cm2/V*s because they contain minimal grain-boundaries. These a-Si strip pattern were then used to characteristic variability of n- and p-channel TFTs and CMOS ring oscillators. The strip patterns showed improved uniformities and defect densities, in general. A 9-stage ring oscillator fabricated with conventional TFTs had a maximum frequency (Fmax) of operation of 58 MHz under supply voltage (Vdd) of 5V which corresponds to a 1-stage delay (τ) of 0.94 ns, while strip channel TFTs demonstrated 108 MHz Fmax and τ decreased to 0.52 ns.
Ebrahim Najafi, et al., from the California Institute of Technology, showed how “Ultrafast Imaging of Carrier Dynamics at the p-n Junction Interface” based on scanning ultrafast electron microscopy (SUEM) combines the spatial resolution of an electron probe with the temporal resolution of an optical pulse to enable unprecedented studies of carrier dynamics in spatially complex geometries. Observing the behavior of carriers in both space and time provides direct imaging of carrier excitation, transport, and recombination in the silicon p-n junction and the ability to follow their spatiotemporal behavior. Carrier separation on the surface of the p-n junction extends tens of microns beyond the depletion layer, as explained by a model using a ballistic-type transport. With the invention of SUEM, it should now be possible to study density profiles and electric potentials at surfaces and interfaces at the ultrafast time scale with the spatial resolution of the electron probe.
As a reminder, the Call For Paper for the MRS Fall 2015 meeting closes on June 18.
By Ed Korczynski, Sr. Technical Editor
At IEDM 2014 last month in San Francisco, Applied Materials sponsored an evening panel discussion on the theme of “How do we continue past 7nm?” Given that leading fabs are now ramping 14nm node processes, and exploring manufacturing options for the 10nm node, “past 7nm” means 5nm node processing. There are many device options possible, but cost-effective manufacturing at this scale will require Extreme Ultra-Violet (EUV) lithography to avoid the costs of quadruple-patterning.
Figure 1 shows the panel being moderated by Professor Mark Rodwell of the University of California Santa Barbara, composed of the following industry experts:
- Karim Arabi, Ph.D. – vice president, engineering, Qualcomm,
- Michael Guillorn, Ph.D. – research staff member, IBM,
- Witek Maszara, Ph.D. – distinguished member of technical staff, GLOBALFOUNDRIES,
- Aaron Thean, Ph.D. – vice president, logic process technologies, imec, and
- Satheesh Kuppurao, Ph.D. – vice president, front end products group, Applied Materials.
Arabi said that from the design perspective the overarching concern is to keep “innovating at the edge” of instantaneous and mobile processing. At the transistor level, the 10nm node process will be similar to that at the 14nm node, though perhaps with alternate channels. The 7nm node will be an inflection point with more innovation needed such as gate-all-around (GAA) nanowires in a horizontal array. By the 5nm node there’s no way to avoid tunnel FETs and III-V channels and possibly vertical nanowires, though self-heating issues could become very challenging. There’s no shortage of good ideas in the front end and lots of optimism that we’ll be able to make the transistors somehow, but the situation in the backend of on-chip metal interconnect is looking like it could become a bottleneck.
Guillorn extolled the virtues of embedded-memory to accelerate logic functions, as a great example of co-optimization at the chip level providing a real boost in performance at the system level. The infection at 7nm and beyond could lead to GAA Carbon Nano-Tube (CNT) as the minimum functional device. It’s limited to think about future devices only in terms of dimensional shrinks, since much of the performance improvement will come from new materials and new device and technology integration. In addition to concerns with interconnects, maintaining acceptable resistance in transistor contacts will be very difficult with reduced contact areas.
Maszara provided target numbers for a 5nm node technology to provide a 50% area shrink over 7nm: gate pitch of 30nm, and interconnect level Metal 1 (M1) pitch of 20nm. To reach those targets, GLOBALFOUNDRIES’ cost models show that EUV with ~0.5 N.A. would be needed. Even if much of the lithography could use some manner of Directed Self-Assembly (DSA), EUV would still be needed for cut-masks and contacts. In terms of device performance, either finFET or nanowires could provide desired off current but the challenge then becomes how to get the on current for intended mobile applications? Alternative channels with high mobility materials could work but it remains to be seen how they will be integrated. A rough calculation of cost is the number of mask layers, and for 5nm node processing the cost/transistor could still go down if the industry has ideal EUV. Otherwise, the only affordable way to go may be stay at 7nm node specs but do transistor stacking.
Thein detailed why electrostatic scaling is a key factor. Parasitics will be extraordinary for any 5nm node devices due to the intrinsically higher number of surfaces and junctions within the same volume. Just the parasitic capacitances at 7nm are modeled as being 75% of the total capacitance of the chip. The device trend from planar to finFET to nanowires means proportionally increasing relative surface areas, which results in inherently greater sensitivity to surface-defects and interface-traps. Scaling to smaller structures may not help you if you loose most of the current and voltage in non-useful traps and defects, and that has already been seen in comparisons of III-V finFETs and nanowires. Also, 2D scaling of CMOS gates is not sustainable, and so one motivation for considering vertical transistors for logic at 5nm would be to allow for 20nm gates at 30nm pitch.
Kappurao reminded attendees that while there is still uncertainty regarding the device structures beyond 7nm, there is certainty in 4 trends for equipment processes the industry will need:
- everything is an interface requiring precision materials engineering,
- film depositions are either atomic-layer or selective films or even lattice-matched,
- pattern definition using dry selective-removal and directed self-assembly, and
- architecture in 3D means high aspect-ratio processing and non-equilibrium processing.
An example of non-equilibrium processing is single-wafer rapid-thermal-annealers (RTA) that today run for nanoseconds—providing the same or even better performance than equilibrium. Figure 2 shows that a cobalt-liner for copper lines along with a selective-cobalt cap provides a 10x improvement in electromigration compared to the previous process-of-record, which is an example of precision materials engineering solving scaling performance issues.
“We have to figure out how to control these materials,” reminded Kappurao. “At 5nm we’re talking about atomic precision, and we have to invent technologies that can control these things reliably in a manufacturable manner.” Whether it’s channel or contact or gate or interconnect, all the materials are going to change as we keep adding more functionality at smaller device sizes.
There is tremendous momentum in the industry behind density scaling, but when economic limits of 2D scaling are reached then designers will have to start working on 3D monolithic. It is likely that the industry will need even more integration of design and manufacturing, because it will be very challenging to keep the cost-per-function decreasing. After CMOS there are still many options for new devices to arrive in the form of spintronics or tunnel-FETs or quantum-dots.
However, Arabi reminded attendees as to why the industry has stayed with CMOS digital synchronous technology leading to design tools and a manufacturing roadmap in an ecosystem. “The industry hit a jackpot with CMOS digital. Let’s face it, we have not even been able to do asynchronous logic…even though people tried it for many years. My prediction is we’ll go as far as we can until we hit atomic limits.”
By Bill Martin, President and VP of Engg, E-System Design
In the late 1940’s, three physicists (Bardeen, Brattain and Shockley) invented the first transistor and were later awarded the Nobel Prize in 1956 (Figure 1). Texas Instruments commercialized the integrate silicon transistor (IC) in 1954 revolutionizing consumer products. The IC invention and commercialization came at a perfect point in history1,2.
During 1950-1970s, the US population grew by 33% (Figure 2), income grew 170% and disposable spending increased 259% (Figure 3). Disposable income was aided by increasing income but also by significant changes to our marginal tax rates. (Figure 4). Consumer demand for better IC based products and their spending $s provided a perfect Petri dish to hone a new technology requiring new processes (silicon, packaging and pcb); supply chains and high tech marketing for future IC based technologies3,4.
In this period, Moore’s Law was ‘coined’ and quickly drove and guided silicon manufacturers to prove their processing prowess. It also drove product companies and their marketing staffs to harness the guaranteed 2x density, improved performance and less expensive next generation silicon technology within their products. Like an atomic clock, the market expected and received the new capabilities every 18-24 months.
The IC treadmill was at full speed replacing older, larger, slower, higher maintenance products with ICs. As ‘they’ conquered existing products, new uses from the significant (medical devices), to the trivial (musical greeting cards) were developed to capture the growing disposable income. In the early days, it was cheap to create any type of product to test market acceptance.
Since the 1970’s the environment has significantly improved:
US population is over 330 million, annual income is over $50K, disposable spending is approaching 50% and the tax rates continue to fall. In addition, the entire world, 7 billion strong and growing, many wanting to have the latest products. Today’s product success benchmark has elevated to a million or more units purchased during a product’s life span. Some very well designed and marketed products attain this volume on the initial day of sale (iPhone)!
Cracks in the foundation: Inflection omen?
But there were cracks in the foundation starting to appear. More resources, more time and additional physical effects that had to be analyzed and resolved. But engineers are very good at solving these issues that arise with each new generation. One aspect that has not been addressed and is racing out of control is a design’s silicon mask costs. Masks allow silicon foundries to build up ICs one layer at a time and define all geometries required for an IC to work. Each physical layer may require 1 or 2 masks. Until the mid 1990’s, mask costs were manageable. But as the industry continued to drive toward smaller geometries, 90nm silicon mask costs passed $1M per design5. Process engineers had accomplished their goals of producing smaller geometries but this caused an escalation in the required number of masks per layer and the finer geometries increased the cost to create and inspect each mask. Both factors led to a geometric impact on mask costs. Once past the $1M per mask set, the next process’ mask prices quickly escalated to $3-4M for a 65nm set. This is just for the masks and does not include other product development costs, wafer/assembly/test manufacturing costs, marketing or sales costs. Quick math: a product with 1 million units of sales that contains one 65 nm integrate circuit will attribute $3-4 dollars to pay back ONLY the mask set expense. FPGA, as a design platform, is one solution but this assumes that your design can be implemented in an FPGA. Many high volume parts still want a dedicated, non-FPGA solution due to per unit costs. Think what the end product’s sale’s price must be for a decent return on investment (ROI). Economics used to be a friend of silicon linear scaling but we might be at the economic inflection point for linear scaling. A recent SemiWiki post by Paul McLellan highlights the complexity and change required to continue the silicon scaling6:
“The problem with double patterning is that it is possible to design layouts that cannot be split into two masks…
To make things worse, this is not a local phenomenon…
The introduction of both multi-patterning and FinFETs has a huge impact …
…the entire place and route flow needs to be completely revamped.”
Economics drive the inflection
Will all these technology issues get resolved? Scientists and engineers have conquered most of what they focus on (flying, space, ocean, medical, etc). In time, all of the technical issues can be resolved but what will be the cost to use these ‘solutions’? Economics on the product development side (development vs. revenues generated) will cause many product developers to search for alternative solutions or cancel projects that are ROI infeasible.
Moore’s Law V1.0 was based upon manufacturing unit learning curves. Each doubling of volume helped decrease the costs to produce the next unit by improving yields. Improving yields allowed designers to create larger die with more transistors and functionality but at a higher cost (at least they could get >0% yield). But this higher cost drove product companies to search for the next generation silicon node that shrunk the die to improve costs: a perfect circular system re-enforcing itself.
Time for Moore’s Law 2.0 (Figure 6: More than Moore modified)
Changing to another solution requires persistence, energy and small successes to gain inertia for Moore’s Law 2.0. Packaging becomes the focus on Moore’s Law 2.0: 2.5D and 3D allow the mixing and matching of many building blocks into miniaturized systems. Blocks already designed, proven with known histories, costs and suppliers: significantly reducing risks and development costs.
Homogeneous silicon will never be able to integrate all into a single piece of silicon but must always be available. Too many compromises in the homogeneous processing will reduce the effectiveness of a given function (ie AMS/RF or memory or MEMS or…) and the cost of: tools, masks and processing complexity will quickly cancel any products looking for a positive ROI.
Maybe not a secret any longer….
Secrets are hard to keep when more and more people start to talk. In recent months, increasing articles and press releases discuss companies that are exploring and/or using 2.5/3D packaging for impressive gains. Many of these efforts have been hidden for either keeping a competitive edge or for fear of public failure. But like many trends, once a trend gains momentum, it is difficult to stop. Moore’s Law V1.0 is a perfect example.
If your company is on the Moore’s Law V2.0 bandwagon, continue to re-examine old thoughts with a fresh perspective.
If your company is not investigating Moore’s Law V2.0, you might want to ask why not?
1 First transistor picture. http://www.bluekep.com/insanoglunun-en-buyuk-kesfi/ and http://en.wikipedia.org/wiki/History_of_the_transistor.
3 “100 Years of U.S. Consumer Spending”, U.S. Departments of Labor and Statistics, May 2006.
4 Annenberg Learner website: http://www.learner.org/courses/envsci/unit/text.php?unit=5&secNum=4.
5 C.R. Helms, Past President & CEO International SEMATECH, “Semiconductor Technology Research, Development, & Manufacturing: Status, Challenges, & Solutions” p16, http://www.nist.gov/pml/div683/conference/upload/Helms_2003.pdf, 2003.
6 Place & Route with FinFETs and Double Patterning, Paul McLellan, Sept 29, 2014, https://www.semiwiki.com/forum/content/3883-place-route-finfets-double-patterning.html.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.