By Mark LaPedus
It’s the tale of two promising and separate 3D chip architectures. One technology is slowly taking root, while the other one is heating up.

3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and SK Hynix are accelerating their efforts in the arena.

Presently, NAND vendors are on the 2xnm or 1xnm nodes. The prevailing thought was that vendors would scale existing planar NAND at three distinct points down the 1xnm node. Typically, NAND vendors denote those points as 1x, 1y and 1z. Then, after the so-called 1z or 1znm node, planar NAND supposedly would hit the scaling wall, forcing vendors to migrate to 3D NAND.

In fact, 2D NAND will have difficulties scaling beyond 10nm. This is because the critical structure in NAND—the floating gate—is seeing an increase in the dreaded cell-to-cell interference in the word lines.

SanDisk still plans to scale NAND for two more generations until 2016, and then, it will debut 3D NAND. But in what appears to be a switch in strategy, Samsung and SK Hynix plan to develop 2D NAND at the 1x and 1y nodes. Then, “it appears that Samsung is bypassing 1z, similar to SK Hynix,” said Doug Freedman, an analyst with RBC Capital Markets.

Instead of going to 1z, Samsung and Hynix will move directly to 3D NAND. In fact, Samsung will begin sampling parts in the second half of 2013, with production slated for 2014, Freedman said.

“As there is maybe one more shrink left for planar NAND, some manufacturers are making the transition earlier to 3D NAND,” said Greg Wong, an analyst with Forward Insights. “Scaling of planar NAND is nearing its end, and 3D NAND is seen as the way to continue density increases and cost reductions for NAND flash memory.”

With 3D NAND, memory vendors also will move from a costly lithography-centric production environment to a less-expensive etch/deposition flow, said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “The overall cost of the tools will be cheaper with 3D NAND,” Lee said “This is mainly driven by the difference in the number of critical lithography and double-patterning steps.”

3D NAND contenders
Samsung will bring out 3D NAND first, followed in order by SK Hynix, Toshiba and Micron, Forward Insights’ Wong said. In 3D NAND, Samsung hopes to leapfrog the competition and grab the early profits with its so-called terabit cell array transistor (TCAT) architecture.

In TCAT, NAND layers are stacked using an oxide and nitride deposition process. Then, the nitride is removed by an etch process. Finally, the bit and word lines are created using a tungsten fill. TCAT and other 3D NAND architectures are different than 2.5D/3D stack-die technologies, where devices are stacked and connected using TSVs.

Another NAND vendor, SanDisk, has a different strategy. “SanDisk is planning to remain planar until 2016, while competitors begin to develop and produce 3D (NAND) into the market late this year and early next,” said RBC’s Freedman. “SanDisk’s (3D NAND) solutions are being judiciously developed to cater to the high-performance market. The high-performance side of the market will not be ready to qualify 3D for another two to three years.”

Using 193nm immersion lithography, the SanDisk-Toshiba duo is producing 19nm planar NAND with a 19- x 26-nm cell size. Then, at 1y, SanDisk’s goal is to devise planar NAND with a 19- x 19.5nm cell size, with production slated by the end of this year.

Then, unlike Samsung and SK Hynix, SanDisk will scale planar at 1z. “There is no need to rush into 3D” until it is cost effective, said Ritu Shrivastava, vice president of technology at SanDisk. In reality, 2D NAND will remain the mainstream technology for some time. Over time, 3D NAND will move into high-end applications, like solid-state storage.

By 2016, SanDisk hopes to debut the Bit Cost Scalable (BiCS) technology, a 3D NAND technology that was originally conceived by Toshiba. BiCS makes use of a “punch-and plug” structure. Toshiba has fabricated a prototype 32-Gbit BiCS test array, with a 16-layer memory cell based on 60nm design rules.

The advantage of 3D NAND is that it doesn’t require leading-edge lithography. Going to 3D NAND will present some challenges, namely the development of quality parts with good read/write performance with endurance. “3D NAND will require a different equipment set,” Shrivastava said. “The burden will shift from lithography to deposition and etch.”

3D NAND process challenges
It also will present NAND vendors with some difficult decisions. First, despite their public roadmaps, vendors may be forced to migrate to 3D NAND sooner than later. “Most leading-edge producers are doing 2D NAND manufacturing at the 20nm or 19nm node, which is the last generation of self-aligned double patterning technology,” Applied’s Lee said. “By using self-align double patterning, one can pattern about 19nm or 19.5nm half-pitch.”

But for some time, the problem with 2D NAND has been apparent—it is running out of steam. “With existing planar NAND, there is not much room to squeeze in the materials for the charge-trap flash or the floating-gate,” Lee said.

In theory, NAND hits the wall at 10nm. “In order to scale NAND manufacturing beyond that, the industry must adopt self-aligned quadruple patterning or self-aligned triple pattering,” he said. “That allows for 10nm half-pitch. But doing 10nm half-pitch patterning will be extremely difficult. It will add a lot more process steps, which will increase the cost of manufacturing.”

Clearly, 3D NAND is the future based on two factors: scaling and cost. “If you compare the cost between sub-20nm planar versus 3D NAND, I believe it will be a lot cheaper to build a 3D NAND fab,” he said. “Planar is driven by litho. In 3D NAND, the bit growth is enabled by increasing the number of vertical layers. This has nothing to do with litho.”

3D NAND can be produced using existing 193nm lithography. Other expensive steps, such as self-align double-patterning etch and low-temperature atomic layer-deposition (ALD), are also eliminated. All told, 3D NAND is largely dependent on two technologies: deposition and etch.

The big challenge is to enable high-aspect ratios using new etch techniques. “There are three distinctly new etch processes in 3D NAND,” Lee said. “This includes high-aspect ratio memory hole etch, which did not exist in planar NAND. There is also a high-aspect ratio trench-line etch, which also did not exist in planar. And then another one is a so-called staircase etch. This is a very long process, which has to provide the landing pads for the contacts.”

3D NAND also introduces alternating stack deposition, which defines the vertical stack. In a 32-layer NAND device, for example, the process could involve some 64 layers of deposition, plus some dummy layers. All told, the flow requires some 70 alternating deposition steps. “The existing tools cannot provide such high productivity,” Lee said. “So that involves a new type of chamber design and technology.”

Metrology is also a critical part of the equation. “Nanometrics believes that 3D NAND will use 20% to 25% more OCD tools relative to planar NAND,” said Weston Twigg, an analyst with Pacific Crest Securities.

“In planar NAND, the gate width is defined by lithography,” added Applied’s Lee. “Now, the gate width is defined by deposition. So, the uniformity of PECVD deposition of each layer, and the quality of the films, are very critical. When we deposit several layers, it’s not a big deal. But let’s say we deposit 40, 50 or 70 layers in-situ. That means we have to control the surface of the interface very smoothly from the beginning. Otherwise, we end up with a rough surface on the top, which will not work.”

So far, Micron, Samsung, SanDisk-Toshiba and SK Hynix have yet to discuss the exact specifications for their respective 3D NAND devices. It’s unclear how many layers the initial devices will have, prompting many to ask a simple question: How far will 3D NAND scale? “I see it going for several generations,” Lee said. “But after 3D NAND, the industry will require another breakthrough.”

By Mark LaPedus
What impact will Intel have on the overall foundry business? In a research note, Weston Twigg, an analyst with Pacific Crest Securities, said: “Competition between Intel and the foundries, and the foundries and each other, should force high spending at the leading edge over the next two to three years. We remain bullish on equipment demand as long as Intel continues to play an aggressive role in the x86 versus ARM battle and its new foundry effort. We believe Intel is attempting to exploit its manufacturing technology advantage, which should pressure rivals TSMC and Samsung to maintain aggressive node transition plans.”

Staying in the leading-edge process technology race requires deep pockets. At 20nm and beyond, chipmakers will have to raise the CapEx ante to stay in the race. “Capital and production costs are rising faster than historic levels as logic and foundry producers migrate to 20nm and below,” Twigg said. “We expect equipment costs to rise 25% at the 22nm node and 28% at the 14nm node. New gate technologies, along with multiple-patterning steps and pitch-splitting techniques, are driving costs higher.”

GlobalFoundries has announced several milestones in the 2.5D/3D chip arena—a series of events that brings the technology one step closer to mass production.

In coordination with the National Academy of Sciences, GlobalFoundries helped host a conference titled, “New York’s Nanotechnology Model: Building the Innovation Economy” at the Hudson Valley Community College in Troy, N.Y.

Fabless ASIC house Socle Technology named Michael Noonen as its new chairman. Noonen is still the executive vice president of global sales and marketing at GlobalFoundries, which is an investor in Socle.

The Silicon Integration Initiative (Si2) said that the ESD Working Group of the OpenPDK Coalition has released an ESD Protection Design Flow Methodology. The ESD Working Group that developed this document included representatives from IBM, Intel, GlobalFoundries, NXP, Samsung, and STMicroelectronics.

Mentor Graphics announced availability of a comprehensive IP-to-system, UPF-based low-power verification flow.

ARM and Cadence disclosed the details behind their collaboration to implement the first ARM Cortex-A57 processor on TSMC’s 16nm finFET process.

Peregrine Semiconductor said that its UltraCMOS phase locked loop (PLL) frequency synthesizer and prescaler devices are designed into six Globalstar mobile communication satellites that were launched into orbit in February. UltraCMOS is an advanced RF silicon-on-Insulator (SOI) process.

Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials, has been named a fellow of the Institute of Electrical and Electronics Engineers (IEEE).

Sematech executive Raj Jammy has joined Intermolecular as senior vice president and general manager of the semiconductor group.

RF Micro Devices announced the appointment of James Clifford, a former executive at Qualcomm, as vice president of foundry services.

More than one quarter of installed wafer capacity worldwide is dedicated to producing IC devices using process geometries smaller than 40nm, according to IC Insights.

In 2012, Intel retained the No. 1 market share position for the 21st year in a row, according to Gartner. Qualcomm climbed from No. 6 in 2011 to No. 3, and now trails only Intel and Samsung. Texas Instruments retained its fourth-place ranking, although Toshiba slipped to fifth place.

By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss the trends in lithography with Mark Melliar-Smith, president and chief executive of Molecular Imprints Inc. (MII), a supplier of nanoimprint lithography tools.

SMD: How do you view the IC industry now?
Melliar-Smith: It’s truly incredible work that this industry continues to do. The industry will see its way for the next 10 years. But to some extent, there are storm clouds on the horizon. This incredible complexity eventually looks like it may get a little out of control. We have to see what happens.

SMD: What will drive the demand for ICs in the future?
Melliar-Smith: There is a never-ending demand for more complex capabilities coming from the consumer. For example, there is an increasing amount of memory that needs to be stored in the cloud or on a mobile system. In addition, there is an enormous demand for bandwidth.

SMD: Why are lithography costs soaring out of control?
Melliar-Smith: We are in an era of increasing complexity and cost. The complexity comes in two varieties. The first complexity comes in the restrictions placed on the designers. That makes the designs less efficient and more difficult. The other part of the complexity comes just from the fact that you are starting to do double patterning. There are more steps to do it all. The complexity, of course, always comes with increased costs.

SMD: So is lithography heading for a train wreck?
Melliar-Smith: If I take a larger view of lithography, I could charge lithography the extraneous costs, including the inefficiencies of designs. Now, you are getting to the point where the productivity is beginning to come off the tracks in terms of how many millions of transistors per dollar I get. It’s not a train wreck, but it’s more of a challenge to really get the same learning curves we had before.

SMD: Any comments on EUV?

Melliar-Smith: EUV is a very difficult technology. I admire the people and what they’ve been able to do. The challenges get exponentially more difficult every year it’s late.  It’s been so delayed now that the dimensions that people want to use it for are down to well below 20nm. And at that point, you have a tough problem. The number of photons is much less than what you have at 193nm. It’s like by a factor of 30 less. So you have these very energetic photons flying in and the chemical debris goes into different directions. So it is not easy to solve that problem at 15nm. You also worry about shot noise and line-edge roughness.

SMD: What is the progress of nanoimprint lithography?
Melliar-Smith: We are actually making good progress. Obviously, as you know, if you want to go in and turn over the existing litho technology in today’s fabs, then that’s probably the toughest challenge you could have. People are justifiably conservative. The reason why we are getting a lot of traction now is that the benefits are becoming very noticeable.

SMD: What are the benefits of nanoimprint?
Melliar-Smith: First of all, we have no wavelength imaging issues. So, we can do single imprints or single patterning down towards 10nm. Second, we have far fewer design rule restrictions. We are not in the position of giving a design rule book that is like a telephone book, with all of the things you can’t do. We also don’t use high-speed photo chemistry to image. If you are imaging on a wafer, you are shining this image down and must do some chemistry on a resist. But as you get to smaller and smaller features, the problem gets tougher. So you get shot noise and line-edge roughness problems. We don’t have any of this. We bring the potential for much lower cost.

SMD: What markets are you targeting in semiconductors?
Melliar-Smith: Our target for initial production would be the memory space, particularly flash. The resolution requirements are the most extreme.

SMD: Toshiba is one of your customers. Is Toshiba in NAND production using nanoimprint yet?

Melliar-Smith: No. They are not in production yet. You have to ask them what their plans are. But clearly, they see the potential for the technology. In the memory space, people don’t talk very much about what they are doing. It’s hard to get our customers to stand up and champion us publicly.

SMD: The knock on nanoimprint is defectivity, overlay and throughput. What’s the latest on that?

Melliar-Smith: The long pole in the tent has always been defectivity. In the last couple of years, we’ve made huge progress. We are now down to the point where we believe our defectivity is close enough, that there is significant consideration for production in memory using nanoimprint. The advantage in memory, of course, is that you have redundancy built into the device. So the acceptable defect level is much higher than it is in logic. We believe the defect issues, and the ability to make 1X masks, looks like they are well under way for a solution.

SMD: What are the other challenges?
Melliar-Smith: The only challenge we’ve got is to make these very high-resolution masks. At present, the electron-beam pattern generators that write our masks are resolution limited to about 25nm, which is not enough.

SMD: What are the solutions?

Melliar-Smith: There were a couple of papers from SPIE. One is from IMS, which is developing a multi-beam mask writer. IMS is going to bring out a 12nm beta tool in 2015. The other one is from DNP. They showed results using double patterning on the mask to imprint a mask. You do all of the expensive patterning on the master mask. And then you use the master to create a replicate mask. And then you use a replicate mask in the factory. The cost of the master mask is irrelevant in the cost-of-ownership. DNP showed 15nm master masks made by double patterning.

SMD: You are also targeting the 450mm market. You sold a 450mm nanoimprint tool to Intel, right?
Melliar-Smith: We had a 450mm tool, which was billed and accepted by a customer. The customer wants to accelerate the transition to 450mm. To do that, they’ve got to provide patterned wafers to companies like Lam, Applied and TEL.

SMD: MII also has been talking about the disk drive industry. Nanoimprint is targeted for the shift towards bit-patterned media. What’s the status on that?
Melliar-Smith: Given the dynamics of that industry like consolidation and other things, the (disk drive makers) have actually slowed their density roadmap down. So that opportunity for us has been pushed out a couple of years. It’s a matter of if and not when. Hitachi, Seagate and Western Digital all have programs with patterned media using nanoimprint.

SMD: What other markets are you looking at?

Melliar-Smith: Another area we are interested in is working with the polarizers in flat-panel displays. They use polarizers in front of the light source and after the switching matrix. Today, they use organic film polarizers. They’ve known for a long time that a so-called wide-grid polarizer is a better polarizer. That’s an aluminum film on the glass, which is etched into 15nm lines and spaces. It has better transmission. That solution plays to our strengths.

By Mark LaPedus
Gartner released its top five IT predictions for China in 2013 and beyond. In one prediction, Chinese PC maker Lenovo will become the top smartphone vendor in China by 2013. The company’s smartphone market share rose from 1.7 percent in 3Q ‘11 to 14.8% in 3Q ‘12, making it now the No. 2 smartphone brand, ahead of Apple (6.9%) and behind Samsung (16.7%).

The SOI Industry Consortium has organized a symposium that will address the world of fully-depleted SOI. The symposium will be held at the San Francisco Hilton Hotel on Dec. 10, concurrent with the IEDM 2012 Conference.

MagnaChip has expanded its foundry production for Peregrine Semiconductor’s STeP5 UltraCMOS technology, which is used for RF devices. UltraCMOS is an advanced form of silicon-on-insulator technology based on a sapphire substrate.

At the IEEE International Solid-State Circuits Conference (ISSCC), which is in San Francisco from Feb. 17 to 21, 2013, IBM will present a paper on a next-generation processor for its System z mainframe. The processor combines six 5.5 GHz processor cores and two memory chips in a ceramic MCM package. The processor has 2.75 billion transistors on a 598mm2 die. The 32nm chip makes use of a high-k/metal-gate scheme and SOI technology with 15 layers of metal. The chips are placed on a 102-layer MCM with two 192MB L4 cache ICs. This is said to achieve a total MCM bandwidth of 530GB/s.

Also at ISSCC, IBM will describe a 22nm SOI SRAM operating over a wide voltage range of 0.7V to 1.1V. It employs a fine granularity power-gating feature, which reduces bit cell leakage by 37% and also reduces peripheral circuit leakage by 40%.

During the event, AMD will describe a 28nm, 11-metal layer x86 processor. The so-called “Jaguar”quad-core processor runs at up to 1.85 GHz.

Oracle will take ISSCC to introduce its next-generation SPARC T5 processor in 28nm technology with 13 metal layers containing 1.5 billion transistors. The chip integrates 16 3.6 GHz cores and a shared 8MB L3 cache with a 9-port crossbar. Oracle also will demonstrate glueless scaling to 8 sockets, or 128 cores, to deliver a total of 1024 threads in a single system. Its new I/O system architecture enables over 5TB/s bandwidth.

At ISSCC, China’s Loongson Technology will demonstrate its latest 8-core microprocessor, dubbed the Godson-3B1500, based on a MIPS64 instruction set. Fabricated in a 32nm, high-k/metal-gate process with 10 layers of metal, the chip contains 1.14 billion transistors. The processor operates at 1.35 GHz.

On the memory side at ISSCC, SanDisk and Toshiba will present a 32 Gbit ReRAM test chip in a 24nm process with a diode as the selection device. Separately, TSMC will present a cycling-endurance optimization scheme for a 1-Mbit STT-MRAM in 40nm technology with a dynamic load balance circuit. And Micron will present the first ever 128-Gbit, 3-bit-per-cell NAND design using 20nm planar cell technology.

Mentor Graphics announced the availability of a GENIVI 3.0 specification-compliant Linux- based Infotainment product. The solution integrates graphics, communication and multimedia middleware with libraries, system infrastructure and management components on top of Linux. http://www.mentor.com/company/news/mentor-embedded-genivi-3-compliant

TSMC recently approved capital appropriations totaling approximately $2.975 billion for the purpose of expanding advanced process capacity and the construction of a 300mm GigaFab. It also approved R&D capital appropriations and 2013 sustaining capital appropriations totaling approximately $209.5 million. In addition, it approved the subscription of approximately $42.28 million in new shares to be issued by TSMC Solid State Lighting Ltd. in 2013. And finally, it approved the subscription of approximately $21.63 million in new shares to be issued by TSMC Solar Ltd. in 2013.

Creative Technology has entered into an agreement with Intel under which Intel will license certain GPU technology and patents from ZiiLABS, a subsidiary of Creative. Intel will acquire certain engineering resources and assets related to the U.K. subsidiary of ZiiLABS. The deal is worth $50 million.

MIPS Technologies has received an unsolicited and rival proposal from CEVA to acquire all of the outstanding shares of MIPS. This follows MIPS’ proposed patent sale transaction with Bridge Crossing.

Global GDP growth is now expected to expand by an estimated 2.6% in 2012, close to the global recession threshold of 2.5% and well below the long-term average growth rate of 3.5%. However, the forecast for worldwide GDP in 2013 is 3.2% growth, according to IC Insights.

Smartphones will account for a larger share of NAND flash memory usage, as compared to feature phones, according to iSuppli.

Global demand and pricing in October for solar polysilicon fell at the highest rate seen since February, indicating that supply still exceeds demand, according to the IHS Solar Polysilicon Price Index.

Three pure-play foundries, TSMC, GlobalFoundries and UMC, are expected to be in the top 20 rankings of leading semiconductor suppliers in 2012, according to IC Insights.

In the rankings, Intel is projected to remain in first place in terms of sales in 2012, followed in order by Samsung, TSMC, Qualcomm, TI, Toshiba, Renesas, SK Hynix, Micron, and ST.

The only expected movement with regard to the top 5 spots in the 2012 ranking is that fabless supplier Qualcomm is forecast to register a 30% surge in sales this year and move up three positions to replace TI as the fourth largest semiconductor supplier, according to the firm.

As a result of its performance this year, GlobalFoundries is forecast to replace Elpida and move into the top 20 ranking for the first time, rising from the 21st spot in 2011 to 15th place in 2012, according to the firm. UMC will remain in 20th place. Sales from pure-play foundry GlobalFoundries are forecast to jump by 31% while foundry giant TSMC is expected to show a 17% increase this year, according to IC Insights.

Combined, these three foundries are forecast to log a 16% increase in 2012/2011 sales, quite impressive considering the expected 2% decline in the worldwide semiconductor market this year, according to the firm.

The continued success of the fabless/foundry business model is evident when examining the top 20 semiconductor suppliers ranked by growth rate. The top five performers are expected to include three fabless companies, Qualcomm, Nvidia, and Broadcom, and two pure-play foundries, GlobalFoundries and TSMC, according to the firm.

Illustrating the difficult year faced by the majority of the top 20 semiconductor suppliers, 12 of the top 20 ranked companies are forecast to register a sales decline this year, including 7 of the top 10 largest semiconductor suppliers in the world (#1 Intel, #2 Samsung, #4 TI, #6 Toshiba, #7 Renesas, #8 SK Hynix, and #10 ST).

By Mark LaPedus
The NAND flash memory market is entering into a new and painful cycle, a period that will impact suppliers, OEMs and fab tool vendors alike.

For some time, there has been an oversupply and depressed pricing in the NAND market. In mid-2011, Micron, Samsung, SK Hynix and Toshiba put on the brakes in their capital spending plans. And in recent months, NAND suppliers in total have announced plans to cut 150,000 wafer starts per month, or about 12% of the world’s NAND capacity, amid ongoing losses and sluggish demand.

Just as suppliers moved to cut their production, spot shortages of NAND surfaced at some OEMs in early September. Most OEMs are not seeing any shortages, but that could all change. Apple, the world’s largest buyer of NAND, could cause some gyrations in the channels as it ramps up its new iPhone 5.

So what’s the outlook in the fluid and confusing NAND market? Amid a bitter legal battle with Samsung, speculation is rampant throughout the NAND industry about whether Apple will swap suppliers from Samsung to SK Hynix, Toshiba and Micron. If that happens, Samsung would face an oversupply in NAND, while others may see capacity shortfalls.

The outlook is also not so rosy for fab tool vendors, which counted on a big capital spending cycle for NAND. In fact, NAND suppliers are expected to push out their capital spending plans until June of 2013 and perhaps beyond, said Vijay Rakesh, an analyst with Sterne Agee.

The lack of capital spending is expected to create a shortfall in NAND capacity, creating perhaps a long cycle of acute shortages. Presently, there is a capacity glut for NAND. “Demand should catch up with capacity by mid-2013,” said Jim Handy, an analyst with Objective-Analysis. “Then, there could be NAND shortages from then until the middle of 2015.”

In total, suppliers are expected to ship 28.013 billion gigabits of NAND in 2012, which represents a bit growth of 49% over 2011, according to Stern Agee. The figure is lower than the historical averages in terms of bit growth, which ranges from 65% to 85%, according to the firm. In total, suppliers are expected to ship 43.756 billion gigabits of NAND in 2013, which represents a bit growth of 56%, according to Stern Agee.

Boom to bust
NAND has seen its share of boom and bust cycles. Several years ago, NAND vendors witnessed a meteoric rise amid a boom for cell phones, flash cards, USB drives and other products.

Then, over the last two or so years, Micron, Samsung, SK Hynix and Toshiba began to expand their NAND production at a dramatic pace. The goal was to meet the anticipated demand for the next wave of product drivers, such as smartphones, solid-state drives (SSDs), tablets and ultrabooks.

Seeking to drive down product costs, particularly for SSDs, NAND vendors took the lead in process technology. For example, the Toshiba-SanDisk duo has been ramping up parts based on the world’s most advanced process, a 19nm technology.

The bottom fell out of the NAND market in recent times. NAND vendors built up too much fab capacity. Average selling prices (ASPs) for NAND fell by 46% in the first half of 2012. Demand for NAND in smartphones and tablets remains overwhelming, but SSD and ultrabook shipments have been disappointing thus far.

“The adoption of solid-state drives is not ramping as quickly as forecast, and with only a modest increase in the bits per box for mobile devices, we now see NAND bit growth in the range of 60% to 65%,” said Mike Splinter, chairman and chief executive of Applied Materials, during a recent conference call. As a result, NAND vendors in total plan to cut production by roughly 150,000 wafer starts per month “on top of a reduction in their capital spending,” Splinter said.

Based on recent announcements, Toshiba is cutting 30% of its NAND production, Micron is reducing its output by 15%, and SK Hynix and Samsung are each at 10%, said Hans Mosesmann, an analyst with Raymond James. “Using these percentages, this would equate to a 12% reduction in supply,” he said.

NAND vendors expected bit growth of about 70% in 2012, but they have lowered their forecasts to about 45%, said Robert Witkow, president of Westwood Marketing, a research firm. “All manufacturers are regulating bit growth by slowing the transitions of 2xnm to the 1xnm node,” Witkow said. “All manufacturers are slowing their transitions from 64-Gbit to 128-Gbit devices.”

One OEM, OCZ Technology, lowered its quarterly forecast in September, saying it could not obtain enough NAND parts for its SSDs. “My price survey and other feedback I’ve received confirm some tightness (in NAND supply),” Witkow said. “If we have allocation in NAND, which I think is possible in 2012, it will be short-lived. I think the NAND market will ease at the end of October, as production sold for Christmas winds down.”

The average selling price (ASP) outlook is good for consumers, but horrific for suppliers. In September 2010, NAND crossed the $1.00/GB price point. The price dropped to $0.35/GB in May of 2012, according to Objective-Analysis’ Handy. “It hit $0.31/GB in June, but then it went back up to $0.36/GB in August,” Handy said. “The June pricing was below manufacturing costs, which is unsustainable. It could go as low as $0.31/GB again, but not temporarily as it did before. That would be permanent.”

NAND CapEx slows
On the fab tool side of the equation, Applied Materials and others saw a softening in demand for gear in the summer, due in part to sharp declines in foundry and NAND spending. By late August, tool vendors saw a further deterioration in NAND, causing more tool pushouts, according to Applied’s Splinter.

Capital spending will remain anemic in DRAMs. The foundries expanded their 28nm capacities earlier this year. But more recently, foundries put the brakes on spending to digest their new tool buys, Splinter said. In total, fab tool capital spending is expected to reach $30 billion to $33 billion in 2012, down 10% to 20% from 2011, he said. In its original projection, Applied forecasted a flat year in fab tool spending.

There’s good and bad news for fab tool vendors. For example, Samsung, the world’s largest NAND vendor, is cutting some NAND production. But the company also is converting some of its NAND production to system LSI and foundry services. As it turns out, logic is more profitable than NAND.

Samsung still wants to remain the leader in NAND. Last year, for example, the company began ramping up NAND production in Line 16 in Korea. “Samsung has slowed its expansion of Line 16, but it did not cut wafer starts,” said Westwood Marketing’s Witkow.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, is a foundry plant dedicated for Apple.

The other fab in Austin is currently a NAND facility. Austin represents about 20% of Samsung’s total NAND capacity, according to Barclays Capital. However, Samsung is converting that fab from NAND into a system LSI plant, said Christian Gregor Dieseldorff, an analyst with SEMI. “Ultimately, all of Austin will be converted to system LSI,” Dieseldorff said.

In Korea, Samsung’s main logic/foundry fab is called S1, which is being expanded. Samsung is converting its Line 14 plant in Korea from NAND to 28nm logic capacity. Line 14 is now part of S1, he said.

Meanwhile, Toshiba, the world’s second largest NAND vendor, in June announced plans to cut NAND production by about 30% at its Yokkaichi Operation fab in Mie Prefecture, Japan. At a minimum, this could remove 6% of worldwide NAND supply, according to Barclays Capital.

Micron, the world’s third largest NAND vendor, is re-balancing its capacity. “Micron increased its triple-level-cell (TLC) wafer production slightly, but reduced its multi-level-cell (MLC) slightly in June. My belief is that the move was taken to support the Lexar consumer product builds for Christmas. Micron will likely shift (its production) back to MLC shortly,” said Westwood Marketing’s Witkow.

SK Hynix, the world’s fourth largest NAND vendor, added 10,000 wafer starts at its new M12 fab in Korea. But SK Hynix is also mulling plans to shift its capacity from NAND to DRAM in M12, according to Barclays Capital.

By Mark LaPedus
Ten years ago, Intel Corp. declared that flash memory would stop scaling at 65nm, prompting the need for a new replacement technology.

Thinking the end was near for flash, a number of companies began to develop various next-generation memory types, such as 3D chips, FeRAM, MRAM, phase-change memory (PCM), and ReRAM. Many of these technologies were originally billed as “universal memories.” By definition, a “universal memory” is a single product that could replace all four conventional memory types: DRAM, NAND, NOR and SRAM.

As it turned out, conventional memory has scaled much further than previously thought, pushing out the need for the next-generation technologies. And, in fact, most next-generation memory types are still in R&D. They are expensive to make and difficult to scale.

While there is a frenzy of activity in next-generation memories, the rhetoric surrounding the “universal memory” is fading. Because of the complexity and soaring I/O requirements in today’s systems, there is no single next-generation memory type that has the cost benefits of DRAM, the speed of SRAM, and the non-volatility of flash.

“It is unlikely that we will see a universal memory,” said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “I do not see a new memory type can replace both NAND and DRAM.”

Clearly, after years of hype, the universal memories have come back down to earth. In possibly the best-case scenario, a next-generation technology could become a mere one-to-one replacement for today’s memory types, Lee said. “We might see them in certain applications and segments,” he said.

Universal niches
In the meantime, HP, Intel, IBM, Micron, SK Hynix, Toshiba, Samsung and others are developing various next-generation memory types. Because it remains unclear which technology will replace DRAM and flash, the larger players are developing most next-generation memory types.

There is a sense of urgency to develop these technologies. DRAM could stop scaling somewhere at the 1nm node. “There is not much room for the floating gate to scale in flash. Nobody really believes that planar NAND can go below 10nm,” Lee added.

In one possible scenario in the next five years (or longer), a next-generation MRAM called spin-torque MRAM (STT-RAM) is the candidate to replace DRAM and SRAM. Also in the distant future, 3D NAND and ReRAM may replace NAND flash and the disk drive.

And PCM could not only displace NOR, but it could also emerge as a new class of so-called storage-class memory. MRAM and ReRAM also are being positioned as storage-class memories, which supposedly fit between the main memory and the processor to alleviate the I/O bottleneck in a system.

Alan Niebel, chief executive of Web-Feet Research, has a different viewpoint. The next-generation memory types are classified as storage-class memories, which can be sub-divided into two groups: memory (DRAM-like) and storage (NAND-like), Niebel said. “Possibly by 2020, one technology may be able to bridge the cost, performance, persistence, and power parameters to satisfy both memory and storage needs,” he said. “In the meantime, the leading replacements for NAND in storage are phase-change and ReRAM. STT-RAM could be a DRAM replacement, but it is too costly for storage.”

NAND and DRAM replacements
If or when planar NAND runs out of gas, the prevailing school of thought is that 3D NAND will replace NAND, followed much later by ReRAM. ReRAM is non-volatile and based on the electronic switching of a resistor element material between two stable resistive states. Startup Adesto is sampling one form of ReRAM, dubbed conductive bridging RAM (CBRAM), which is an EEPROM replacement. HP, Micron, Samsung, SK Hynix and others are working on NAND-replacement ReRAMs.

The first ReRAMs are based on a 1T1R (1 transistor and 1 resistor) structure. Next-generation ReRAMs are based on a 1R structure and consist of various architectures, such as 3D and cross-point arrays. These ReRAMs present several challenges, prompting some to believe that these memories won’t appear until 2015 or so. “Each of the metal layers requires advanced lithography, which is very expensive,” said David Eggleston, senior vice president at Rambus. In 2012, Rambus acquired ReRAM developer Unity Semiconductor.

At a recent event, SK Hynix outlined its strategy, which typifies the roadmap of a NAND vendor. First, SK Hynix will continue to extend planar NAND. “I think scaling NAND to 12nm will be very challenging,” said Sung Wook Park, executive vice president and head of the R&D Center at SK Hynix.

SK Hynix is separately developing a 12nm planar NAND part and 3D NAND. 3D NAND is targeted as the successor to planar NAND, Park said. In addition, the company is also working on next-generation STT-RAM with Toshiba. SK Hynix is separately co-developing PCM with IBM.

The industry also is keeping a close eye on SK Hynix and Hewlett-Packard, which have been jointly working on commercializing HP’s memristor by 2015. A form of ReRAM, memristor is a passive two-terminal electronic device. In memristance, if the flow of a charge is stopped by turning off the applied voltage, this component will “remember” its last resistance.

Initially, devices based on the memristor are aimed for storage, said Janice Nickel, research manager at the Cognitive Research Laboratory at HP Labs. “Then, we will look to move up from there.”

SK Hynix has developed an 8-Mbit test chip based on the memristor. HP itself has demonstrated a 54nm cross-bar structure. “The challenge is the integration of new materials,” Nickel said.

Others hope to ship ReRAMs sooner than later. Micron and Sony, for example, have been co-developing so-called Adaptive ReRAM for possible introduction in 2014. Adaptive ReRAMs are expected to have up to 8-Gbit capacities. Initially, Adaptive ReRAM is geared for cache module applications, said Keiichi Tsutsui, senior manager of advanced memory systems at Sony.

Like NAND, the industry is searching for a DRAM successor. When the DRAM runs out of gas, 3D-based Wide I/0 technology is one possible successor. In addition, Micron and Samsung are developing a 3D DRAM technology called the Hybrid Memory Cube (HMC).

There are several challenges to develop 3D DRAM. Longer term, STT-RAM may replace DRAM. Everspin, IBM-TDK, Qualcomm-TSMC, Samsung, Toshiba and others are working on STT-RAM.

STT-RAM makes use of a spin-transfer torque technology. This is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction (MTJ) can be modified using a spin-polarized current. STT-RAMs are fast and non-volatile, but the challenges include scalability and unstable switching currents in the MTJ memory cell.

“It’s really too early for MRAM to replace DRAM,” said Phillip LoPresti, president and chief executive of Everspin Technologies, an MRAM supplier. “MRAM is always going to be behind in cost and density.”

For now, MRAM is geared for the embedded market. Everspin, for example, is shipping first-generation MRAMs based on a toggle-write technology, mainly for the battery-backed SRAM replacement market. In addition, Everspin is also readying the world’s first STT-RAM. In a slide at a recent event, Everspin called it a ST-RAM or ”SpinRAM.”

Using an alternate method for programming an MTJ element, ST-RAM is mainly geared to replace “battery-backed DRAM” or persistent RAM in hard drives and related storage applications, said Steffen Hellmold, vice president of marketing at Everspin. In an invited paper at the upcoming IEDM, Everspin will describe how they built the largest functional ST-MRAM circuit ever built, a 64-Mbit device with good electrical characteristics.

For main-memory in PCs and other systems, DRAM will remain the dominant technology for some time. “MRAM will not replace DRAM for at least the five years,” Hellmold said. “I am willing to place a bet on it.”

New memory phase
Like MRAM and ReRAM, PCM is in its infancy. PCM is difficult to scale and limited by the power required to change from the crystalline to the amorphous state. Researchers are looking at germanium telluride (GeTe) materials to overcome these limitations, said Jean-Luc Delcarri, general manager of Altatech, a subsidiary of Soitec.

Gary Kotzur, a distinguished engineer at PC maker Dell, said PCM has a potential place in online transaction processing (OLTP) systems. For OLTP, PCM needs to have “faster writes,” he said. “The power must be lower.”

Another application is online analytical processing, but for this application, “we need much higher densities,” he added.

By Mark LaPedus
According to a recent study commissioned by Intel, nearly all countries surveyed say that mobile manners have become worse compared to a year ago.

Spot shortages, and possible price increases, for NAND flash have suddenly surfaced in the market amid recent production cuts by major memory suppliers.

SEMI said total fab spending could increase by 16.7% in 2013 and reach a new record high of $42.7 billion.

Intel said that Q3 revenue is expected to be below the company’s previous outlook due to lackluster PC demand. Full-year capital spending is expected to be below the low-end of Intel’s previous outlook of $12.1 billion to $12.9 billion, as the company accelerates the re-use of existing equipment to the 14nm node. “Intel’s guidance cut seems widely expected given many reports about weak consumer PC demand due to macro weakness in China and Europe and with a production/demand air pocket before Win8 launches in late October,” said Craig Berger, an analyst with FBR.

The Semiconductor Industry Association (SIA) said that worldwide sales of semiconductors reached $24.4 billion for the month of July 2012, a slight increase of 0.2% from the previous month. C.J. Muse, an analyst with Barclays Capital, sees a downturn coming based on the SIA figures. “As expected SIA data released saw semi revenues post modest growth and confirms our outlook for semis to track down -2% to -8% year-over-year, depending on demand in the month of September,” he said.

For months, there have been rumors that Fujitsu will sell its chip unit to Renesas. In the meantime, Fujitsu Semiconductor has unloaded and sold its LSI assembly and test facilities to J-Devices.

Integrated Silicon Solution has completed an equity investment in Nanya. ISSI will have access to leading-edge process technologies with certain volume guarantees from Nanya for specialty DRAM production. Taiwan DRAM maker Nanya will also provide foundry support capabilities for the continued development of ISSI’s NOR flash and analog products.

Altera unveiled several key technologies planned for its next-generation of 20nm products, including stacked 3D chips.

Cree rolled out 100mm epitaxial wafers based on silicon carbide (SiC). The wafers enable high-voltage bipolar devices such as IGBTs.

Semiconductor R&D spending is projected to hit a record-high of $53.4 billion in 2012, according to IC Insights.

The Microsoft/Intel cartel, known as Wintel, now finds itself playing catch-up in the new era of smartphones and media tablets, according to IHS iSuppli.

Global smart meter shipments grew 33.6% in Q2 over the previous quarter, and were up nearly 51.3% year over year, according to IDC.

Despite a fuzzy economic outlook and concerns regarding the decline in sales of consumer LCD products, TFT LCD panel suppliers are still expecting 2012 shipments to grow 8% to 757 million and revenue to increase 13% to $85.3 billion, according to NPD DisplaySearch.

By Mark LaPedus
For years, many have predicted the end of flash memory scaling, particularly NAND, but the technology continues to defy the odds as it moves down the process curve.

Still, there are signs that the floating gate structure in today’s flash memory is on its last legs. The floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio. And there is an increase in cell-to-cell interference in the word lines.

“The floating gate has been very successful in scaling down to the current 20nm node or even the 1xnm node,” said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “There is not much room for the floating gate to scale. Nobody really believes that planar NAND can go below 10nm.”

Today, the Toshiba-SanDisk duo is shipping NAND devices based on the world’s most advanced process, a 19nm technology. Going forward in NAND, Lee and others see at least two or more nodes remaining in the 1xnm regime.

The question is what’s after NAND flash? Currently, the industry is pursuing three basic categories in the NAND replacement sweepstakes: scaling existing NAND; 3D NAND; and the next-generation memory types.

There is no clear-cut winner right now. But in some circles, the initial and most promising successor is 3D NAND. “3D NAND is an extension of existing NAND,” Lee said. “Vertical NAND is in the development stage right now. The timeline for mass production is as early as 2013. Some companies have announced 2015.”

Defying the odds
Clearly, flash scaling has defied the odds. Ten years ago, Intel, the first vendor that commercialized NOR flash, predicted that flash would hit the wall at 65nm. Banking on those predictions, a number of firms began to develop various next-generation memory technologies that could replace NAND, NOR or DRAM—or all three. FeRAM, MRAM, phase-change and ReRAM are among those candidates.

The prediction was wrong, however. NAND has scaled down to 19nm, while NOR has migrated to 45nm. Thanks to 193nm immersion lithography and self-aligned double patterning (SADP), flash vendors have been able to scale the floating gate.

The ability to scale NAND and NOR has also pushed out the need for the next-generation memory types. And besides, most of these new memory types are still in R&D. They are expensive to make and difficult to scale.

Scaling today’s NAND down to 10nm is also difficult. NAND vendors may have to use self-aligned quadruple patterning, as extreme ultraviolet (EUV) lithography remains delayed. “NAND is even beyond current EUV resolutions. Even if EUV is available as of today, double patterning has to be used together with EUV,” Lee said.

There is also a remote chance that today’s 2D NAND could scale further using charge trap technology. Charge trap uses a silicon nitride film to store electrons. “I think the generation of charge trap flash as a planar device is limited,” he said.

Initially, if or when today’s NAND runs out of gas, the industry is banking on 3D NAND. “With 3D NAND, scaling is no longer driven by lithography. The gate length is defined by deposition,” Lee said.

3D NAND is also challenging, but the production steps are slightly different than 3D stacked DRAM and logic. The key step to 3D NAND is to build a multitude of oxide/nitride or oxide/doped polysilicon stacked layers. Another key step is to fill the deep memory holes or trench slits. “The top foreseeable challenges are ultra-high-aspect ratio (>40:1) conductor etch and dielectric etch with high etch selectivity to the hard mask,” Lee said in a recent paper.

There’s another challenge as well: Can the 3D NAND developers put their products into production? The main 3D NAND contenders are Toshiba’s BiCS, Samsung’s VG-NAND, Macronix’ BE-SONOS, Hynix’ vertical cylindrical FG, SanDisk’s 3D memory and Intel/Micron’s stackable PCM, according to Forward Insights.

The 3D NAND industry emerged in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. BiCs makes use of a “punch-and plug” structure and charge trap memory films. Toshiba has fabricated a prototype 32-Gbit BiCS flash memory test array with a 16-layer memory cell using 60nm design rules.

In 2009, Samsung described its 3D NAND technology based on a terabit cell array transistor (TCAT). A year later, Macronix talked about a BE-SONOS charge-trapping technology. And Hynix is developing a 3D dual control-gate with a surrounding floating-gate.

One of the newer candidates is the stackable phase-change memory (PCM) device from Intel and Micron. Micron recently announced a 2D PCM device based on a 45nm process. In PCM, it is difficult to scale the cell array. PCM is also limited by the power required to change from the crystalline to an amorphous state.

Researchers are looking at new materials beyond traditional GST-225 schemes to overcome these limitations. Among those materials are binary and ternary alloys like germanium telluride (GeTe). “GeTe is one of the enablers,” said Jean-Luc Delcarri, general manager of Altatech, a CVD and inspection equipment subsidiary of Soitec. Altatech has installed its CVD system at CEA-Leti, which is developing PCM for the sub-20nm node.

It’s unclear which 3D NAND devices will eventually move into production, but there is a huge appetite for NAND in mobile and other applications. “I can’t say which vendor is ahead,” Applied’s Lee said. “I think vertical NAND will likely be adopted in traditional applications. The biggest applications are smartphones, tablets and mobile computing. What is still to come are SSDs.”

3D NAND debate
Analysts have slightly different viewpoints. “The only company that has told me a schedule is Toshiba, who plans to sample 3D NAND in 2013,” said Jim Handy, an analyst with Objective-Analysis, a research firm.

“The thing that is driving (3D NAND) is the use for more bytes in video,” Handy said. “3D NAND is straightforward for a DRAM maker since it has stacked SiO2 and polysilicon layers like a stacked capacitor DRAM and trenches like a trench cell DRAM. I have heard that the aspect ratios for the trenches are somewhat tricky.”

Greg Wong, an analyst with Forward Insights, does not see commercial production for 3D NAND until 2015 or so. “NAND flash manufacturers are pushing planar NAND flash to sub-20nm nodes. As they extend the roadmap for 2D NAND, the introduction of 3D NAND gets pushed out,” Wong said.

“There are technical challenges with etching a high aspect ratio pillar and multiple stacks, but the big challenge is economic. The investment required is significantly more for 3D than 2D NAND,” Wong said. “3D NAND employing charge trapping technology will have some challenges in meeting the performance specifications of 2D NAND. However, by stacking multiple layers, lower cost per bit can be attained.”

Alan Niebel, president of Web-Feet Research, agreed. “3D NAND should enter the market around 2015 (or after). Designing and qualifying 3D NAND will probably be a seven year process, which started in 2007. Concurrently, it takes easily another five years to perfect the manufacturing and especially in manufacturing 3D ICs,” Niebel said.

“3D NAND should have a much higher areal density and lower cost than 2D NAND, since the F2 divides in half with each layer, probably four layers max per chip. Performance in both speeds (read and write) and endurance will deteriorate with 3D NAND compared to 2D,” he added. “The stacked structure will have more bits to address, more interconnects with each layer and longer distance from cell to controller that will add latency to the 3D. Perhaps endurance may not suffer too much if the lithography is the same for 2D and 3D NAND cells, but by stacking them in 3D, these additional steps could possibly fatigue the control gate oxides and further reduce endurance.”

Besides the technology challenges, Applied’s Lee sees another hurdle—cost. “NAND vendors will go into 3D only if they can meet a cost target. We are quite confident the cost structure of 3D NAND will be lower than 2D NAND. The reason is that 3D NAND is less lithographic and double-patterning heavy,” he said.

By Mark LaPedus
Seeking to reduce the cost of solid-state lighting and related applications, LED manufacturers are taking a page from the IC industry: They are looking at larger wafer sizes and new materials in the fab.

Today, the state-of-the-art LED fab is a 150mm (6-inch) facility, but a large percentage of these plants are still using 50mm (2-inch) substrates. The vast majority of LED suppliers use substrates based on sapphire technology. The exception to the rule is Cree, which uses silicon carbide (SiC) substrates.

In what could drive down manufacturing costs, Bridgelux, Lattice Power, Osram, Philips Lumileds, Toshiba and others are exploring or beginning to ramp up LEDs based on a lower cost substrate material: silicon. Toshiba, for one, is ramping up a gallium nitride (GaN) on silicon process using 200mm wafers.

In addition, other vendors are starting to ramp up LEDs based on separate GaN-on-GaN or semi non-polar GaN substrates using 50mm or smaller wafer sizes. GaN promises to generate more lumens per area, but the substrate costs are still expensive.

GaN-on-silicon processes on 200mm substrates has a 1- to 2-cent per square mm die cost advantage over traditional sapphire in LED production, said Jy Bhardwaj, vice president of research and development at Philips Lumileds, one of the world’s largest LED makers. “It isn’t like silicon will take over everything,” Bhardwaj said. “Silicon is indeed under development as a cost play, feasible only when the performance disadvantages have been overcome. Silicon must also enter at 200mm without any increased processing costs.”

Sapphire and SiC, the incumbent technologies, will continue to make advances amid a push towards silicon. “The sapphire industry is not going to stand still. The sapphire world is also investing in 200mm,” he said.

Compared to semiconductor plants, LED fab costs are reasonable. A 50mm (2-inch) LED fab runs from $50 million to $60 million, said Christian Dieseldorff, an analyst with SEMI. In comparison, a big LED fab runs from $120 million to $150 million. “Most LED fabs run a mix of wafer sizes,” Dieseldorff said. “There is not really a pure 6-inch dedicated LED fab out there, because 6-inch sapphire is very expensive.”

It’s unlikely that manufacturers would build a dedicated 200mm LED fab. Today, global LED demand can be entirely met by a single 200mm line with 50,000 wafer starts per month, according to Philips Lumileds. So, don’t expect 300mm LED fabs in the near term.

Sea of change
Still, there is a sea of change taking place in LEDs. After years of sizzling growth, the LED market is currently suffering from a capacity glut and sluggish demand. According to SEMI, total LED fab capital equipment spending is projected to hit $1.917 billion in 2012, down from $2.52 billion in 2011. In 2013, LED fab capital spending is projected to be $1.96 billion.

One of the reasons for the glut is that the Chinese government handed out subsidies of up to 50% to buy the key LED equipment, metal organic chemical vapor deposition (MOCVD) tools, to LED makers in China. China recently ended most of the MOCVD subsidies, but the move caused excess capacity in the worldwide market.

LED demand is also mixed. The LED market is maturing for TVs and mobile products. The next big thing is solid-state lighting, which could save $120 billion in energy costs over the next 20 years, according to the U.S. Department of Energy.

There is still a glaring cost delta between LED lamps and the lowly incandescent light bulb. The cost of a 60-watt LED replacement bulb is roughly $25 to $40, compared to a mere 50 cents for today’s incandescent bulb, said Robert Steele, a consultant for Strategies Unlimited, a research firm. “LEDs are five times more efficient, but the price gap for a LED replacement bulb still remains too high for consumers,” he said.

China makes the cheapest LED bulbs at about $14 to $24 per unit. High-end LED makers are looking to reduce the cost of the package, which in turn could help bring the price of an LED bulb to around $11.06 by 2020, according to Lux Research.

LED suppliers also are focusing on the substrate to reduce costs. In a simple LED manufacturing flow, the substrate goes through an MOCVD or epitaxy process, followed by etch and packaging. The MOCVD tools represent 50% or more of LED fab capital expenditures.

Hydride vapor phase epitaxy (HVPE) is an alternative approach that is said to speed up the flow for thick GaN layers in LEDs. Using HVPE, LED makers can reduce the cost of GaN template wafers, said Chantal Arena, vice president and general manager of Soitec Phoenix Labs, a subsidiary of Soitec. “Our strategy is to use production-proven silicon epitaxy equipment features and add our gallium source and delivery system to create a high productivity HVPE equipment,” Arena said.

New LED substrate materials
At present, there are five main LED substrate types. With its patented SiC substrate technology, Cree announced a 150mm LED fab in 2010. At that time, Philips Lumileds became one of the first sapphire LED vendors to move to 150mm substrates.

Silicon and GaN are the new kids on the block. In June, China’s Lattice Power announced what the company claimed were the world’s first GaN-on-silicon LEDs in production. Lattice Power’s LEDs are made on 50mm wafers.

Then, in July, Toshiba said it will shortly start mass production of white LEDs based on a GaN-on-silicon technology on a 200mm line in Japan. Toshiba and its partner, Bridgelux, have been collaborating on the development of GaN-on-silicon technology.

“The opportunity for silicon is not on 6-inch, because 6-inch costs for sapphire are really coming down. The opportunity for silicon is going to be on 8-inch,” said Philips Lumileds’ Bhardwaj. “But that opportunity is only there for a short period of time, because sapphire will be available on 8-inch and it will come down in cost. So the question is, can silicon deliver in the next one or two years? The performance has to be at parity or very near it. Today, the best case is 5% below the best in class sapphire. The worst case is 10% to 15% below.”

Like sapphire and SiC, GaN-on-silicon suffers from material stress due to a combination of lattice and thermal expansion mismatch. “Therefore, you’ve got to create this interface matching and growth nucleation layers. The greater the mismatch, the higher the number of dislocation defects and it is critical minimize the threading dislocation density (TDD),” he said.

Lattice Power addresses the problem using patterned substrates that isolate the stress caused by cracking. It utilizes an AlGaN/AlGaN multilayer buffer that manages internal strain. With this approach, Lattice Power claims a manufacturing yield of more than 95%.

On the GaN front, startup Soraa is developing LED lamps based on a GaN-on-GaN technology. Unlike sapphire, SiC and silicon, GaN is latticed matched, which lowers the TDD. Others are developing semi non-polar GaN. With this technology, the substrates are free of stacking faults, thereby reducing TDD by 10,000 times, according to Kyma, a supplier of substrate products.

“There is a lot of interest in GaN,” said Strategies Unlimited’s Steele. “You can drive more current through the LED, but it’s very expensive. The challenge is to get substrate costs down.”

There could be room for all substrate technologies, especially in the fledging solid-state lighting market. Lighting only represents 10% to 15% of the overall LED market and there is still room for growth. “LEDs are still rapidly growing in lighting,” Steele said.