By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: What’s the big challenge with 3D stacking from a DFM perspective?
Ramaswami: People want to put a couple of vias in the place of one because they don’t know if the first one is filled or not. What happens is you put a lot of strain on the transistors adjacent to them—5 microns, 10 microns or 15 microns away. In response to that, people want to shrink the via dimensions, but that’s not practical to fill. This is where design, manufacturing and design for manufacturing all come together. Right now the industry has a sweet spot around a 5 to 6 micron CD (critical dimension). Let’s get that working first before we move onto other dimensions.

SMD: How about testing of these stacked die?
Mason: We’re feeding design for manufacturability risk areas into the ATPG (automatic test pattern generation) flow. We’re informed by our analysis of the chip of what likely problem areas might be—stress, TSVs, lithographic hot spots, or strain-induced problems—and we feed those locations into the test pattern flow and they set up test vectors that are diagnostic against those problems. One of the solutions I see is heavier use of ATPG. If you have informed manufacturing people who can anticipate where the problems might be—and I think we can—then you can develop test methodologies targeted for those problems. That’s part of the answer.
Smayling: A big problem for test will be that these 3D chips are different functions. If you’re used to working with logic testers and now you’ve got DRAMs or NAND flash or mixed signal, do you call up three different test guys? It’s going to be a real nightmare to integrate test and to make it cost-effective.
Michaels: I agree that test will be a great challenge. The other fundamental issue is that failures at the stacked die level are extremely expensive. How you minimize failure and catch it upstream through probability of good die, through system disaggregation and choosing the right technology for the right chip will fundamentally have a big impact.

SMD: The cost escalates not just because of the design, but also because of a larger bill of materials, right?
Michaels: Absolutely. You’re throwing out multiple chips and the packaging for something that is likely a single chip or integration failure. You have to catch those early on in the process or it’s going to be extremely uneconomical.

SMD: Will we see more restrictive design rules as we move down Moore’s Law and into 3D?
Capodieci: The complex set of design rules that have been burdening the design manual since 65nm will be radically simplified. That does not mean designs will become simpler, though. They will become more regular. The problem with the complex set of design rules is they need to deal with a very large number of exceptions. When we have extremely regular functions, we’ll also be able to simplify the design rules. There’s been bad synergy between design rules and design when designers became more creative. We are now at a point where everything will become simpler, but new criteria will have to be introduced at the physical design level. What we’re looking at here are special constructs that violate the design rules but which achieve manufacturability.

SMD: But if we put die A on die B, we may be creating a bad die from two known good die, right?
Capodieci: That’s correct. We need to start thinking in 3D. The density is now an issue. What kind of thermal densities will we create? There will be rules for 3D, but they will be subsumed by the fact that we will start thinking about those rules in 2D, as well.
Michaels: Those issues exist today with differences in density. The super-linear growth in design rules was driven in part by trying to define what is not allowed. If you look at any hyperspace of design rules, it’s looking like Swiss cheese. You have to make the transition or flip to defining what is allowed. What patterns are allowed vs. what isn’t allowed? That’s a big change for designers, and it’s a way for foundries to help them make the best choices. At the leading edge you’re starting to see a closer partnership between the fabless companies and the foundries.

SMD: As we look at 3D and advanced 2D, there also is more rationalization to match functionality with what’s needed. Does it make sense to move analog IP to 14nm, for example. How are these changes affecting design?
Mason: If the 20nm node is going to cost you so many dollars per square millimeter of silicon, and 130nm or 180nm analog silicon running on depreciated capital equipment is going to cost you 10% or 1% of that, with proven yield, and you have a cost-effective way to integrate that with a 3D solution, it’s a very simple business problem. That assumes you have a way to do it and your architecture allows you that much decoupling of your analog systems. There are issues there. Sometimes a little bit of analog needs to be proximate to some other circuit. But we will take full advantage of the fact that we have this enormous analog infrastructure and digital infrastructure in the same company.
Ramaswami: Any new application is an opportunity, for sure. Having said that, this is the first time I’ve seen in a long time where a customer’s customer, a customer and Applied are all working together to see what can be done and what should not be done from a technical and a cost point of view.
Smayling: A regular design allows a surprising amount of integration of different functions. The tremendous improvement in variability of critical dimensions is something the analog engineers are interested in getting a piece of. That regularity can extend back to older technology nodes. The whole debate about regular design vs. 3D complex design is driven by people trying to sell supercomputers to do very complex point solutions to increasingly complex problems.
Mason: One of the reasons you do regular designs is you can certify them. They’re known to be good, and you can make aggressive decisions because you know what’s going to happen. But if GlobalFoundries has one set of regular designs, TSMC has another, UMC has another and SMIC has another one, how do you standardize all of this? It’s one thing to talk about regular designs in the IDM space, but when you’re talking about commoditized silicon manufacturing, I’m not sure how to do that.
Capodieci: The overall family of forbidden patterns is more a function of the technology and the technology node. We’re all dealing with the same wavelength and materials. The secret sauce lies not in a special solution. It is reasonable to imagine the patterns will overlap about 95%. The difference will be when we go to the esoteric stuff—more than Moore. That will have radically different shapes and the designs will be radically different. But as long as we keep pushing optical lithography, immersion and on to EUV, we’re going to see the same patterns.
Michaels: At the end of the day there are going to be differences driven by design rule choices, integration choices and material choices. You’re still going to want to maintain your designs at the physical layer. You’ll want to maintain your design requirements—your track height, your pin access, etc.—but fundamentally you’re going to have to do a port anyway. And porting may be easier in a pattern-based world than a design-based world.

SMD: As we push time to market in design, does yield get affected?
Michaels: The challenge of accelerating design is keeping the costs in line. If you look at complex SoCs, the amount of unique IP required on every chip is going up. The desire to re-use hard IP is much greater. The challenge is, what that IP is placed next to can have a strong impact on the parametric or functional unit. How you get to the point where you can re-use IP more effectively comes back to driving from the elimination of the unknown stuff.

SMD: What happens at 450mm? Does yield go up or down?
Michaels: The cost of a good die will go down.
Mason: Yes, and that’s the only thing that matters—cost.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: How good is the information exchange across the supply chain these days?
Capodieci: We need to push a lot of design information onto the manufacturing floor. This is a huge area. The EDA industry really needs to wake up and create a new set of flows. This is one of the most advanced industries in the world. We fabricate sophisticated devices without actually knowing what we’re fabricating. We ask for less-than-optimal information about where the critical issues are. New flows and new interfaces can be added to the manufacturing floor, respecting the IP and the proprietary nature of the design. But the information can be passed on to the manufacturing floor so it can be monitored and acted upon.

SMD: We’re not just creating hardware anymore. How does software affect yield, and is it even considered part of yield?
Michaels: If you look at the fabless sector, they’re hiring multiple software engineers per design engineer. It’s where a great deal of effort is going. But for our purposes, once you get past test and packaging and yield we tend to view it as the fabless problem. It’s not our market.
Mason: At TI we’re investing enormous resources in software and compilers that our customers use. It’s something we have to deliver to the ecosystem to use our products. We’re not using software to fix a yield problem. We’re typically not coupling the software with the fab yield problem right now. It’s more of a design enablement activity.

SMD: Will that change?
Mason: There’s more and more integration across the entire design space, and that includes software. Software is a critical part of what we do on the product side.
Capodieci: In the foundry space, we are still very active in doing esoteric R&D with universities. This is a little futuristic, but we have seen interesting research out of UCSD (University of California San Diego) on dark silicon, which is the silicon that does not get activated. We make it fully functional, but it is hardly used because of power issues. So there are software techniques and architectural techniques that go into making the best use and creating opportunistic cores. This is beyond our traditional field, but in the future we need to keep an eye on how the architectures will evolve with a focus on what needs to yield with a certain variability level and what needs to yield with a different variability level. This is an approach I call managed variability. Not all of the physical components react equally to the process. We need to be able to distribute this, but we need to know which components we’re building. This will be beyond 20nm.
Ramaswami: Most of our investments in software have been in three areas. One, of course, is process design. When you have very deep vias, you have diffusion of materials from the very top to the very bottom. A lot of the modeling has to be done in terms of concentration of gradients as well as mechanical agitation. The second area is around chamber control. When you have a multichip system, how do you measure the parameters? The feedback to the system becomes critical. An example is CMP, where you look to measure in real time the thickness of the materials and you control the polish rate. These get very critical with 10nm or 15nm films at the gate level. The third area is for inspection, where inspection and analysis are becoming a big deal at the wafer and at the mask level.

SMD: What happens with stacking of die and we have to drill holes in the silicon? Where are we now and where will be in a couple years?
Ramaswami: Most of these vias are made in the via-middle process, which is basically a blind via and done right after contact. You have the contact formation to do the blind via, you etch it, line it, and it’s all done. Or you assume it’s done, because you have no way of really knowing. Of course we can do some X-ray analysis at the full wafer level, but we only get ghost images of gray and white. It’s like looking at an ultrasound. You have to be a trained radiologist to figure out what it is. You’re sending the wafer on and putting faith in the rest of the logic line, which may be 10 or 20 layers, each one going through a heat cycle. You’re just hoping the via is in good shape at the very end, and you really don’t know until you do backside testing. In terms of mechanical yield and cross sections, we believe today that filling the via is not an issue as far as structural analysis is concerned. How well it is done electrically, with heat cycles, we just don’t know because data is limited. And often a different side of the fab—the packaging side—finds the data. That feedback loop takes a long time.
Capodieci: In terms of 3D, we’re a little bit behind—particularly with extraction. The problem becomes bigger, of course. But the process side is ahead of the curve. Still, it’s something that needs to be brought to fruition if we are going to bring 3D architectures to market.
Michaels: From the foundry standpoint you can’t completely test at the single-chip or wafer level. That will require the foundries to use more equipment data, more characterization, to find a probability to finding out how close they are to being in the center of the process. You may not be able to test exactly but you can clearly determine when should you scrap, etc. These new techniques of leveraging more data out of the fab than traditional metrology will become more important.
Smayling: In stacking, one of the opportunities for yield improvement stems from the fact that fab inspection traditionally has been on a surface. We’re going to have to think about how to inspect these stacked structures. It’s something we don’t have technology for today, but it’s going to be needed to drive these activities. For EDA, whether they’re stacked or not they’re going to be designed piece by piece. One of the biggest problems for EDA is that each of the pieces is done potentially at a different technology node. Now you’ve got a PDK that works with one version of verification software, a different PDK that works with a different version of verification software. And so when you stack these things together there’s no consistent environment for even doing verification. There is a big opportunity for verification to take on these kinds of issues.
Mason: There are lots of challenges with 3D. TI is right in the middle of those kinds of technologies because that’s the way the industry is heading. One issue that’s important in all of this is DFM. There are all kinds of mechanical stresses in this process, and these mechanical stresses have electrical implications. Where these TSVs are on the wafer relative to transistors and whether those are timing-critical circuits that are impacted by mechanical stresses has to be considered. There is research in this area now. We haven’t worried about these DFM issues in the past, but we will have to.

SMD: What kinds of mechanical stresses?
Mason: Where you physically change the silicon and that has an electrical effect. If you take a chip and macroscopically bend it, that affects the speed of transistors because of the electrical impact of that strain. When you’re doing that locally, you can change the timing of that circuit and break the circuit. That can happen because you’re putting a through-silicon via there that you didn’t simulate.

SMD: Stacking in 2.5D seems much more straightforward compared to full 3D stacking. Which one will come out first and why?
Ramaswami: I think 2.5D is much simpler. But we see the end market today driven by mobile devices, which requires a DRAM stack on top of a logic chip. That clearly does not lend itself to 2.5D or interposer technology. So we need to get that working, no matter what. The questions we’re getting now on 2.5D is how to make the interposer more active rather than just having a piece of silicon with lines through it. Putting more capacitors and inductors on them is an area we’re beginning to pursue with a couple of universities.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss yield issues with Sesh Ramaswami, senior director of strategy at Applied Materials; Luigi Capodieci, R&D fellow at GlobalFoundries; Kimon Michaels, vice president and DFM director at PDF Solutions; Mike Smayling, senior vice president at Tela Innovations; and Mark Mason, director of data integration at Texas Instruments. What follows are excerpts of that conversation.

SMD: As we move down the Moore’s Law curve, how will yield be affected?
Mason: Every time we move down a node we anticipate a certain level of entitlement, both in performance and in terms of cost per function. One of the things that plays into that is yield. It’s our expectation that yield, over time, will go to very high levels. The question is what will be the difficulty in ramping yield to the entitlement yield that you expect. We are dealing with that using design for manufacturability methodologies to ensure that we get to that level.
Smayling: As we move beyond 28nm we will see more factors that have a quantification kind of problem. When we began using thin gate oxides at atomic thicknesses we ran into problems. We ran into random dopant fluctuations because of discrete problems we didn’t expect. We will see those kinds of problems as we continue to shrink geometries.
Michaels: Final entitlement yields in established markets will be just fine. That’s always been the case. In fact, the time it has taken the industry to get to those points has been fairly consistent. But we’re going to see here is more train wrecks early on. Like the transition to copper we have more immature materials, more variation and new failure mechanisms. And we have a lot more parametric failure mechanisms that are going to cause a lot of challenges in distributions of initial yields, both in the fabs and in the foundries.
Capodieci: We’re in violent agreement here. One of the issues is that at 28nm and beyond, the physical design is going to have a very tight coupling with manufacturing. All of the methodologies that we have developed at 90nm, 65nm and 40nm now become essential. The early train wrecks could be avoided, but only through a tight collaboration between the manufacturer, the foundry, the IP providers and the designers, coupled with a methodology for verifying all of this. We’re talking about a DFM ecosystem that needs to play together. But whether this ecosystem is here and pervasive is another matter.
Ramaswami: If I can contain my comments to the through-silicon via and chip stacking, the challenge we see is that while part of the via is done by the foundries or the fabs, how well it’s done is determined by the back-end guys—that might be the foundry or the packaging house. It’s a guess, too. You don’t know how well you’ve done until everything is done. The second part has to do with all the stresses that you’ve built up on thin wafers, which are fully processed. We still don’t know, once the wafers are de-bonded, how they’re going to survive through to packaging.

SMD: How good is yield right now for 28nm?
Michaels: At 28nm there’s a lot of new materials and new integration, which inherently makes yield more challenging. The foundries are working to solve that, but the proof will be in mass production.
Mason: 28nm from a yield ramp at this point does not feel terribly different than the previous nodes I’ve worked on. There are challenges. We have a list. We are working them with our foundry partners. That’s what we do at every node. We expect to deliver entitlement yield ramps on 28nm on time and according to the plans we’ve set.
Capodieci: Yields look good. We’re on target for delivering on time. The key will be whether the physical design will comply with the new methodologies. Yield will be excellent for those designs we have implemented already. With the implementation of certain recommended rules I feel very confident that will work. But if you’re talking about designs that get shrunk from the previous node, those will have some churn. They will need to jump on new CAD methodologies and new verification. The question is whether the design and manufacturing are in sync.

SMD: As we look forward into the next node and into stacking of die, will it be the same yield ramp as for other nodes?
Capodieci: At 20nm, the ramp looks steeper because of the introduction of a possible set of disruptive techniques that right now are still up in the air. We don’t know which one we’re going to bring to high-volume manufacturing. That includes double patterning and a host of different techniques. That will depend on how ready the physical implementation will be. For critical layers, if you cannot decompose them your yield is going to be zero because you cannot tape out with any foundry. We’re already working to make those designs compliant.
Ramaswami: The challenge we see is how to minimize variation, whether it’s chamber-to-chamber or across the wafer. A lot of the work we are doing in process control and components, such as how the valves open and close, is all about chamber matching and wafer matching. A second area is lineage roughness. One or two nanometers can have an impact on performance.
Michaels: Once you look at stacking chips, and you’re only testing 3D chips, it’s very expensive to throw it out. What’s going to be required from the foundry perspective is controlling the variability as well as understanding whether the wafer is within spec. We can’t rely just on wafer probes at the wafer level anymore.
Mason: Yield is something you get when you multiply a lot of numbers less than one together. It’s a function of area. If you have a stacked system, but it has all this area in it, that impacts yield. It also has extra processes in it that impact yield. Nothing yields 100%. So once you multiply all these processes together, then by definition you’re going to have more challenges. We also have to carefully define what we’re talking about. As a customer you’re concerned about the yield package, but as process engineers we’re concerned about the yield of the logic circuits vs. the memory. That’s another layer of complexity.

SMD: We’re used to designing using a linear approach, but complexity will require all of this to be done concurrently between design and manufacturing. Who’s responsible for making sure that happens and will it work?
Smayling: The communication between design and manufacturing has always been a critical part of success. What we’ll need to do more is communicate unambiguously and in a less-burdensome way for both the manufacturing and the design side. There are efforts under way for open DFM and open PDK standards to make this communication more universal and clearer.
Michaels: The physical layer is becoming a place where you potentially differentiate in a negative way by causing problems. That requires tighter interaction between the design and the foundry. But the PDK in a design-rule manual, as a contract between the design team and the foundry, is a fallacy. It’s impossible to guarantee that even with guard-banding. Even if you address every potential corner case, problems exist. We saw that at 40nm. That’s what needs to change.
Capodieci: We have been working on this for many years. We need to enrich the design-rule manual and the PDK with additional constructs. We’re seeing some of those in the IP domain, but we also need constructs from the verification side. Pattern-based verification is working well today. We will see libraries of patterns to transfer information back and forth and share ownership across the physical design and with the foundry.
Ramaswami: Whether it’s lithography, patterning or packaging, we’re trying to figure out what are the design tools that are required. What are the process conditions required, no matter who we work with? In the 3D space we’re working closely with Synopsys with capacitance and stress modeling.
Mason: In TI we have 65 years of semiconductor manufacturing history in-house, but we also use foundries. We understand all about building wafers and we can communicate that to the foundries. But there is a danger in this concept of better communication and having the designers know all about this stuff. The design flow is already pretty busy just getting the design out, so you have to be pretty careful about burdening the design community with design information they’re not quite sure what to do with. You have to build systems that automatically inform the design flow without disrupting the design process. You can’t just push information up the design flow. That’s helpful for conversations but not for design.