Posts Tagged ‘Synopsys’
By Jeff Dorsch, Contributing Editor
The Electronic Design Automation Consortium (EDAC) is no more. The industry organization, founded in 1989, is changing its name to the Electronic System Design Alliance, or ESD Alliance.
The name change is being accompanied by an expansion of the organization’s charter. Having taken on semiconductor intellectual property several years ago, the ESD Alliance will also address advanced packaging and embedded software, according to Robert Smith, who took over last year as executive director of EDAC. The ESD Alliance will also welcome service companies that offer design know-how and resources.
The alliance’s launch was marked by an evening event on Wednesday (March 30) at the SEMI headquarters in San Jose, Calif., where the ESD Alliance has its offices. In attendance at the social gathering were several EDAC directors, including Simon Segars, chief executive officer of ARM Holdings; Wally Rhines, chairman and CEO of Mentor Graphics; Lip-Bu Tan, president and CEO of Cadence Design Systems; and Aart de Geus, chairman and co-CEO of Synopsys.
“We’re part of this large ecosystem,” Bob Smith said Wednesday evening, adding, “Semiconductors – they need design.” He recognized by name many of the people involved in EDAC and now the ESD Alliance.
A slide presentation at the event began with “Kingdom of Rain,” by The The, segueing to “Love Shack” by the B-52’s – two songs dating to 1989, the year EDAC was formed. That also was the year Taylor Swift was born, one slide noted.
In 2016, marked musically by Mark Ronson’s “Uptown Funk” in the slide show, the ESD Alliance is taking the place of the EDA Consortium.
By Jeff Dorsch, Contributing Editor
Custom Compiler is one new tool. It promises to provide what the company calls “visually-assisted automation” in designing custom ICs.
Custom chip designers have asked, ‘Where are the productivity improvements?” for their line of work, de Geus said Wednesday morning (March 30) at the Santa Clara Convention Center.
Designing advanced chips with 3D transistors, FinFETs, adds complexity to the design process, he noted, with “many more rules” and transistors that have “many fins.”
Custom Compiler offers visually-assisted layout with interactive placement and routing, the Synopsys chairman said. The tool’s capabilities “can bring significant productivity,” he added.
To go with Custom Compiler, Synopsys last week introduced the VCS Cheetah simulation tool for system-on-a-chip designs. As part of the VCS verification suite, Cheetah adds the “fastest engines,” unified compile, and unified debug for complex IC designs, de Geus said.
Cheetah employs fine-grained parallelism and advances in CPU/graphics processing unit architectures to speed up simulation for register-transfer level and gate-level designs, according to Synopsys.
De Geus began his keynote saying, “We are going to change the world again.” By “we,” he meant Synopsys, its customers, and its partners in addressing chip design for the Internet of Things, automotive electronics, and other areas.
IoT, he said, can also stand for “immensely optimistic thinking,” to the general amusement of the large audience for the opening keynote. “Deep down, I’m a great optimist,” de Geus added.
Taking “Smart Everything” as his theme, de Geus moved on to the topic of digital intelligence, which is less ambitious than artificial intelligence. “Digital can do things humans cannot,” he said.
While some people will debate whether applications, the computing cloud, the networking edge, or “the fog” is the true center of attention for the IoT, de Geus broke it down to sensors with data storage and some data processing capability, “generating massive amounts of data” – Big Data, as it is commonly known.
Developing the Internet of Things calls for consideration of “technomics,” de Geus said. The impact of IoT technology will be “very long and very broad,” he said.
All of the hardware and software going into the IoT must be secure, according to de Geus, making sure that “the Internet of Threats” doesn’t take over the technology.
Synopsys has made a substantial investment in code security through its acquisition of Coverity and other moves, the Synopsys chairman said. He also addressed automotive-grade intellectual property for chip design and the introduction of data fusion in the IC design process.
“What we need is smart everybody,” de Geus concluded.
SNUG Silicon Valley 2016 continues through Thursday with 10 topic tracks and 52 presentations for Synopsys users. Almost 2,500 users are attending the two-day conference, it was said.
Chenming Hu, a University of California at Berkeley professor, is scheduled to give Thursday’s keynote address on “What Else Besides FinFET?”
By Jeff Dorsch, Contributing Editor
Taiwan Semiconductor Manufacturing Company came to Silicon Valley on Tuesday for a day of presentations on its latest chip technology. The TSMC Technology Symposium for North America drew more than 1,000 attendees at the San Jose Convention Center.
The world’s largest silicon foundry led off the day with a pair of announcements: ARM Holdings and TSMC said they would collaborate on 7-nanometer FinFET process technology for ultra-low-power high-performance computing (HPC) system-on-a-chip devices, building on their previous experience with 16nm and 10nm FinFET process technology, while MediaTek and TSMC extended their partnership to develop Internet of Things and wearable electronics products, using the IC design house’s MT2523 chipset for fitness smartwatches, introduced in January and fabricated with TSMC’s 55nm ULP process.
TSMC’s work with ARM on the 16nm and 10nm nodes employed ARM’s Artisan foundation physical intellectual property, as will their 7nm efforts.
On Tuesday afternoon, the hundreds of attendees heard first from BJ Woo, TSMC’s vice president of business development, on the company’s advanced technology, including its moves toward supporting radio-frequency IC (RFIC) designs for smartphone chips and other areas of wireless communications.
“Cellular RF and WLAN are RF technology drivers,” she said. Looking toward 4G LTE Carrier Aggregation, TSMC began offering its 28HPC RF process to customers in late 2015 and will roll out the 28HPC+ RF process in the second quarter of this year, Woo added.
TSMC has won 75 percent of the business for RFIC applications, she asserted.
The foundry will start making 10nm FinFET chips for flagship smartphones and “phablets” this year, with 7nm FinFET devices for those products in 2017, according to Woo.
The business development executive also touted the company’s “mature 28-nanometer processes,” the 28HPC and 28HPC+, saying they are “rising in both volume and customer tape-outs.”
TSMC has been shipping automotive chips meeting industry standards since 2014, Woo noted, primarily for advanced driver assistance systems (ADAS) and infotainment electronics. The foundry is now working on vehicle control technology, employing microcontrollers.
The company’s 16FF+ process has been used in 50 customer tape-outs, Woo said. “Many have achieved first-silicon success,” she added. TSMC is putting its 16FFC process into volume production during this quarter.
“Automotive will be the [semiconductor] industry focus,” Woo predicted.
She also spoke about the company’s MD2 local interconnect technology, its 1D back-end-of-line process, and its spacer BEOL process.
Regarding 7nm chips, Woo said the company will offer two “tracks” of such chips, for high-performance computing and mobile applications. “Both will be available at the same time,” she said.
Most of the semiconductor production equipment being used for fabrication of 10nm chip will also be used for 7nm manufacturing, according to Woo. Those 7nm chips will be 10 to 15 percent faster than 10nm chips, while reducing power consumption by 35 to 40 percent, she said.
Risk production of 7nm chips will begin one year from now, in March of 2017, she said.
Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, reported on development of electronic design automation (EDA) products for the 16nm node and beyond.
“Low-power solutions are ready,” he said of the foundry’s 16FFC process. IP is available to use with 16FFC for automotive, IoT, HPC, and mobile computing applications, he noted.
Design and manufacturing of 7nm chips will involve cut-metal handling and multiple patterning, according to Lee. “We’ve used this technology on 16 nanometer and previous generations,” he said of cut-metal handling.
TSMC will support multiple SPICE simulators, having developed hybrid-format netlist support, Lee said. Pre-silicon design kits for 7nm chips will be available in the third quarter of 2016, he added.
The TSMC9000 Program for automotive/IoT products will be “up and running” in Q3 of this year, providing “automotive-grade qualification requirements in planning,” he said.
Lee also spoke about the foundry’s offerings in 3D chips, featuring “full integration of packaging and IC design” with TSMC’s InFO technology. The HBM2 CoWoS design kit will be out in the second quarter of 2016, he said. “We’re very excited about that,” Lee added.
George Liu, senior director of TSMC’s Sensor & Display Business Development, said, “The Internet of Things will drive the next semiconductor growth.” When it comes to the IoT and the Internet of Everything, “forecasts are all over the map,” he noted.
Taking diversification as his theme, Liu said TSMC’s specialty technology will help bridge the connection between the natural world and the computing cloud. First there is the “signal chain” of analog chips and sensors, leading to the “data chain” of connectivity, he said.
Liu reviewed a wide variety of relevant technologies, such as CMOS image sensors, microelectromechanical system (MEMS devices, embedded flash memories, biometrics, touch and display technology, and power management ICs.
At the all-day conference, which included an ecosystem exhibition by partner companies, TSMC emphasized its readiness to take on 28nm, 16nm, 10nm, and 7nm chip designs, along with the more mature process technologies. It’s game on for the foundry business.
By Jeff Dorsch, Contributing Editor
The second day of the InvenSense Developers Conference saw presenters get down to cases – use cases for sensors.
There were track sessions devoted to mobile technology and the Internet of Things, with the latter featuring presentations on industrial and automotive applications, smart homes and drones, smartphones and tablet computers, and wearable electronics. InvenSense partner companies had their own track on New Technologies, fitting into the conference’s “Internet of Sensors” theme.
One of the presentations that wrapped up the conference on Wednesday afternoon (November 18) was given by Pim Tuyls, chief executive officer of Intrinsic-ID, the Dutch company that worked with InvenSense to develop the TrustedSensor product, a secure sensor-based authentication system incorporating the FireFly system-on-a-chip device.
TrustedSensor will be shipped to alpha customers in the first quarter of 2016 and will go out to beta customers in the second quarter of next year, according to Tuyls. “This is real,” he said.
The Intrinsic-ID founder briefly reviewed the company’s history, to start. It was spun out of Royal Philips in 2008 and is an independent company with venture-capital funding, Tuyls noted.
Intrinsic-ID was founded to provide “cyber physical security based on physically unclonable function,” or PUF, Tuyls said. “We invented PUF,” he added. “It has been vetted by security labs and government agencies,” among other parties.
Taking “The Trusted Sensor” as his theme, the Intrinsic-ID CEO said, “Sensors are the first line of defense. You want to make sure you can provide a certain level of security.”
It is critical to achieve “the right balance” in designing, fabricating, and installing sensors, with security, flexibility, and low footprint among the key considerations, according to Tuyls.
While whimsically describing PUF as “a magic concept,” Tuyls noted, “Chips are physically unique,” with no two completely alike due to manufacturing processes.
PUF can “extract a crypto key from any device,” he added. “You can authenticate any device.”
Intrinsic-ID has tested the PUF technology with a wide variety of silicon foundries, Tuyls said – namely, Cypress Semiconductor, GlobalFoundries, IBM, Intel, Renesas Electronics, Samsung Electronics, Taiwan Semiconductor Manufacturing, and United Microelectronics. It has been implemented by Altera, Microsemi, NXP Semiconductors, Samsung, and Synopsys, he added, and process nodes ranging from 180 nanometers down to 14nm have been tested.
Tuyls concluded by emphasizing the importance of sensor security for the Internet of Things. “We should not wait; we should not try to save a few cents,” he said. “It is important, but it is hard.”
Earlier in the day, attendees heard from Sam Massih, InvenSense’s director of wearable sensors. “There’s a wearable solution for every part of the body,” he commented.
“Step count isn’t enough,” Massih said. “You need context for data.” He cited the example of a user who goes to the gym three times a week and spends an hour on the elliptical trainer machine for one hour on each visit.
“That’s data that can be monetized,” he said.
InvenSense announced last month that it would enter the market for automotive sensors. Amir Panush, the company’s head of automotive and IoT industrial, said in his presentation, “Sensors need to be smart enough.”
The megatrends in automotive electronics include the use of motion sensors for safety in advanced driver-assistance systems (ADAS), the smart connected car, and tough emission restrictions, according to Panush.
“We have signed a deal with a Tier One partner,” Panush said, meaning a leading automotive manufacturer, without identifying the company. “We are ramping up internal R&D in automotive.” InvenSense is presently opening design centers focusing on the $5 trillion automotive market, he added.
InvenSense was founded in 2003 and went public in 2011. The company posted revenue of $372 million in fiscal 2015 with a net loss of $1.08 million (primarily due to charging $10.55 million in interest expense against net income), after being profitable for the previous four years. InvenSense gets more than three-quarters of its revenue from mobile sensors and has a growing business in IoT sensors.
Customers in Asia accounted for 63 percent of the company’s fiscal 2015 revenue, according to InvenSense’s 10-K annual report. The company spent $90.6 million on research and development, representing about 24 percent of its net revenue.
GlobalFoundries and TSMC make nearly all of InvenSense’s wafers. Assembly packaging of its microelectromechanical system (MEMS) devices and sensors is outsourced to Advanced Semiconductor Engineering, Amkor Technology, Lingsen Precision Industries, and Siliconware Precision Industries.
The company had 644 employees as of March 29, 2015, with nearly half of them involved in R&D.
STMicroelectronics is InvenSense’s primary competitor for consumer motion sensors, the 10-K states, while the company also competes with Analog Devices, Epson Toyocom, Kionix, Knowles, Maxim Integrated Products, MEMSIC, Murata Manufacturing, Panasonic, Robert Bosch, and Sony.
By Jeff Dorsch, Contributing Editor
There was a celebrity roast on 4th Street in San Jose, Calif., on Thursday night.
The occasion was the presentation of the annual Phil Kaufman Award to Wally Rhines, chairman and chief executive officer of Mentor Graphics, for his contributions in the field of electronic design automation. Dr. Rhines has served as Mentor’s CEO since 1993 and as chairman of the EDA software and services company since 2000.
The Phil Kaufman Award is presented by the Electronic Design Automation Consortium (EDAC) and the IEEE Council on Electronic Design Automation (CEDA). It honors the memory of Philip A. Kaufman, the EDA industry pioneer, electronics engineer, and entrepreneur, who died in 1992.
Barrett said of Rhines, who was a top chip executive at Texas Instruments prior to joining Mentor, “We competed for about 20 years, which is probably why he went to Mentor Graphics.”
He added, “His hairline is receding faster than mine.”
The retired Intel executive later said Rhines’ career has been “fantastic,” adding, “He certainly exceeded all our expectations. You done good, man. Keep it up.”
A video shown before the formal presentation offered Barrett and other top executives showering accolades on Rhines, who turned 69 years old on Wednesday, November 11. Among those praising Rhines were Aart de Geus, chairman and co-CEO of Synopsys, and Lip-Bu Tan, president and CEO of Cadence Design Systems – business rivals and friends.
“He’s actually a cool cat,” de Geus said of Rhines in the video.
In his remarks, Rhines returned the favor to those praising him, saying of de Geus and Tan, “We’ve had enjoyable interactions.
“I’m particularly gratified that my professor, Craig Barrett, came here for my roast,” he said. “He willingly paid for the beer at The Oasis in Menlo Park.”
On a more serious note, Rhines said of Barrett, “He was very critical to my success.”
Rhines recalled the days when chip designers used rubylith sheets to lay out integrated circuits. “We evolved an industry,” he commented. While IC design and layout has become highly automated with EDA software, system design in many industries remains in the rubylith era, Rhines said. He called for a movement to “automate system design the way we automated electronic design.”
The evening drew to a close with a spoof video depicting Rhines as not only a visionary leader in EDA, but also as a race-car mechanic, a sushi chef, and a hair stylist. A good time was had by all.
By Jeff Dorsch, Contributing Editor
Aart de Geus is not running for governor of California.
The Synopsys chairman and co-CEO denied that speculation in meeting with journalists Monday morning at the 25th annual Synopsys Users Group Conference in Santa Clara, Calif. In any case, Governor Jerry Brown just began his last four-year term, and there’s not another gubernatorial election in the Golden State until 2018.
“I have a life so interesting,” de Geus said during an hour-long, freewheeling discussion of mostly technical topics. In addition to leading the electronic design automation, intellectual property, and software firm he founded in 1986, which had fiscal 2014 revenue of $2.057 billion, de Geus serves as the guitarist of Legally Blue, a blues band that regularly performs in Silicon Valley.
The political process in Sacramento and Washington, D.C., is plagued by “diffraction,” de Geus observed, leaving little or no public consensus on important issues, such as climate change and water supplies. Synopsys has provided corporate philanthropy for public education in the valley and the Second Harvest Food Bank, among other causes and charities. De Geus said he personally supports the Environmental Defense Fund and Human Rights Watch.
As he noted earlier in the morning during his SNUG keynote address, de Geus spoke about the hardiness of Moore’s Law, which is often proclaimed to be dead.
“For 15 years, analysts have predicted the next chip is impossible,” he said. He recalled that while he was a student 37 years ago, semiconductor experts generally agreed that the industry would never produce chips with dimensions smaller than 1 micron.
“Everything is a constraint problem,” he commented. “It’s always been like that.”
De Geus added, “I have been surprised by how quickly FinFET has caught on.” Later on Monday, Synopsys customers testified about how they have designed chips with FinFETs using Synopsys tools.
Asked about the implementation of fully-depleted silicon-on-insulator technology, de Geus said, “The jury is still out.” He added, “We are seeing design starts.”
The complexity of semiconductor design and manufacturing is increasing, de Geus acknowledged. “Of course it’s getting hard,” he said. The industry will go through the usual period of hand-wringing about technical challenges, according to de Geus. “Then, we nail it!”
By Jeff Dorsch, contributing editor
The world is moving toward “Smart Everything,” according to Aart de Geus, founder, chairman, and co-CEO of Synopsys. “The door will open gradually, and then quickly,” he said in Tuesday’s keynote address at the Design and Verification Conference and Exhibition, or DVCon, in San Jose, Calif.
“The assisted brain is on the way,” de Geus told the standing-room-only audience. “This may be dreaming, but I don’t think so.”
Taking “Smart Design from Silicon to Software” as his official theme, the veteran executive urged attendees to “shift left” – in other words, “squeezing the schedule” to design, verify, debug, and manufacture semiconductors. “Schedules haven’t changed much,” de Geus said. The difference now is that the marketing department has as much influence in planning and scheduling a new product as the engineering department, he noted.
Chip designers also should “shift left” on semiconductor intellectual property, de Geus said. “IP reuse is the biggest change in 15 to 30 years,” he asserted. “Reuse leverages your innovation.”
After plugging the concepts of unified compilation and unified debugging architectures, de Geus touted the use of virtual prototypes in chip design. “Software guys are impatient with you,” he said. Synopsys, he noted, has created 400 million lines of software code.
Turning to the Internet of Things, de Geus said, “There are a lot of opportunities there.” The problem is “these things are full of cracks,” he added. There are significant engineering and security issues that must be addressed in networks of connected devices.
Developing the FinFET “was said to be impossible seven to eight years ago,” de Geus said. Nonetheless, the semiconductor industry was able to realize that advanced technology to move beyond the 28-nanometer process node, he noted. The future is likely to present similar challenges.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.