By Ann Steffora Mutschler
As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable.

But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. You’re on autopilot until you hit a disruption, and 3D represents a disruption.”

Whether it is memory stacked on logic, which is most common today, or stacking multiple logic die on top of each other vertically with through silicon vias (TSVs), both approaches are complicated and require more infrastructure than traditional SoCs.

Yervant Zorian, a Synopsys fellow and chief architect, noted that we have always dealt with multiple chips—but the multiple chips that we dealt with previously were packaged chips. “Having packaged chips on a board allowed us to test the chips fully upon packaging when they are on the wafer. And also, after being packaged to give the full quality chip, proven and warrantied to the board-level team to assemble it on the board. Now that’s all good when a die is packaged—a package protects it from further defectively. However, with 3D stacks or 2.5D interposers or some other advanced packaging technologies we are dealing with there is bare die that is unpackaged so the whole issue starts with that.”

So even though the bare die are fully tested, they are prone to defectively during assembly, mounting, transportation. “Whatever you do between the production of that die up through the time it is assembled with the rest of the dies there is this defectivity magnet situation where certain things happen to it and therefore we need to retest it after it’s been assembled—whether it is two dies, four dies, at every stage you need to test it again to make sure that nothing is damaged,” he added.

Clearly, the test challenges with stacked die include the need to test things at multiple points during fabrication and assembly, Petrakis said. “Then there is a big question about how much testing is required. With test there is cost and what do you forgo and what do you actually test.”

There are two schools of thought here, he noted. One is to use the normal manufacturing test type of approaches such as implanting test circuitry as is normally done and testing each die separately. “You make sure that you apply all the tests and then you know you probably have good die to work with. ‘Probably’ is a good term because you never know.”

Then, if the design will use through-silicon vias, what is the best approach to test and how do you get access to the test interface? “On a normal chip you just go to the pads and you say, ‘These are the test pads,’ and you target those. On a TSV-based design there is a lot of talk about landing probes, but the dimensions are so small that there is fear that they are going to be damaged,” he added.

It’s not all doom and gloom with stacked die, though. “The fun comes in when you start stacking logic die,” asserted Stephen Pateras, product marketing director for Mentor Graphics’ Silicon Test Solutions group. “In the case where you had a single logic die you had full access to it. If there were any test pins and memories that needed to be accessed directly even though they are stacked, you’re going through the BiST, the JEDEC standard interface, so you don’t have to worry about accessing the DRAMs directly. But with stacked logic die, now presumably you want to test pieces of a logic die. You want to test the interconnect between them, so you need access each of those logic die independently somehow. Generally you don’t have access to them, because if they are stacked vertically the idea is that the bottom die will be the one that is connected to the package and the other die are connected to each other. So there may be neighbors top or bottom in that stack. That’s where we need to have a way of going through the stack to get access to those die for test so you need some kind of test access architecture that makes use of the TSVs.”

At the foundation of such a test access architecture is the proposed IEEE P1838 standard, which gives just such access.

Zorian explained that IEEE P1838 complements the work that was done previously with JTAG 1149.1 and IEEE 1500, whereby JTAG was for the chips on the board and 1500 was for the cores in the SoC. “P1838 is for the dies in a 3D structure to talk to those dies. You need an access port and this access port cannot be JTAG. It cannot be 1500, but it can be something between the two and very complementary to those working hand-in-hand coherently with the first two standards to handle the new multi-dies in a package. P1838 will allow us to know exactly what that test bus is. The seven-bit communication bus proposed today will communicate the test related functions between one die to the other, from that die to the next and so on.”

By the time 3-D becomes prominent it is expected that P1838 will be ratified as an IEEE standard.

Further, Cadence’s Petrakis noted that the idea behind p1838 is isolation. “How do we isolate one die from the others such that we can test it internally without disturbing anything else? Then it’s not quite really disturbing it. It’s really a matter of true isolation. You do not want any foreign signals or unknown traditions to affect the testing that you are doing. The isolation is that we put the chip in a mode where it only sees data coming in and out from itself. In other words, the application of test reading the results back is not influenced by anything else.”

The looming cost concern
Amidst the technical challenges of 3D and 2.5D stacked die is the discussion surrounding who will pay for all of this extra testing.

Synopsys’ Zorian said, “The two stops in test that we used to have, which is testing the chip at the wafer level and testing the chip post-package, will still be there. But now we introduce intermediate steps so suddenly we need to do more test in between. When I have two dies together, three dies together—these are the prevalent situations where we need to test them. And there is a cost associated with it because it is after the die has been produced, so you cannot cost-wise expect the die producer that is the chip manufacturer to do that. It is a packaging-oriented cost because it happens later on during the stages of pulling those dies together. It depends who will be doing it and therefore who will pay for it.”

At this point, it seems that the cost will not fall to the die producer, but it depends on how the business model develops—especially because several chip manufacturers and foundries have expressed interest in being part of this ecosystem. “Whether it is TSMC, GlobalFoundries or otherwise, if they are doing it then of course it will be the last stage, because it’s not the wafer manufacturing stage or the wafer testing stage. It is one stage after that.”

However the situation turns out, the rising wave of 3D manufacturing and test is causing ripples throughout the entire ecosystem.

By Ann Steffora Mutschler

With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations.

Certainly, double patterning was the biggest change and the biggest concern on the designer’s minds when they began moving to 20nm, observed David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics. They wanted to know what double patterning was and how to deal with it.

“Also, for the foundries themselves, they wanted to know how were they going to find provide a solution that was viable to the users,” Abercrombie said. “That’s certainly been the bulk of the questions we’ve gotten with the move to 20 nm and below—things related to double patterning, finding and fixing errors, how to deal with parasitic extraction or LVS or whatever, place and route and other things associated with double patterning. It’s certainly a new and different kind of error to deal with.”

The nature of the difference

Most design rule checks typically are associated with either a single polygon or its neighbor. That includes width or spacing or area, which can be complex. For instance, the space is dependent on the width, the run length, etc., but it’s still basically a neighbor-to-neighbor interaction or the layout of the shape itself.

“With odd cycles and anchor path errors, it’s now an issue of the network of interacting shapes—multiple shapes that can be spread over long distances and how they interact with each other in the network of spacings to form this odd cycle or this anchor path,” said Abercrombie. “It’s very different than the traditional rule in that sense. In some ways people have learned to think about it more like an antenna rule that is network-based. It’s not conductivity-based, it’s spacing-based, but it’s about the network of shapes and the spacings.”

This is a whole new level of complexity for designers to deal with. “If you’ve seen 20nm designs from customers, they’re different from 28nm and the reason for that is because of the core fundamental issue in double patterning of conflicts, where one defines a conflict as a native conflict or a loop conflict,” said Manoj Chacko, product marketing director at Cadence noted. “A native conflict is something that you can detect but cannot fix without a design change. That means the designer has to make a design change.”

Consider a loop conflict, for example. If you have four polygons, for example, and two masks for double patterning at 20nm, then each polygon is split into two masks and four polygons is split into eight. That works fine in a very regular layout, but not all layouts are so regular.

“This seems kind of reasonable given that you can assign four polygons eight colors, but in reality it’s a little different because it depends on the proximity of the polygons to the others and so on,” Chacko said. “If you had nine polygons because of an L joint, for example, even if you have to split four into eight but the eighth polygon is not straight, it’s an L—now the L basically may become two colors again, making nine. This is called a loop problem, where you have the eighth polygon that is split into 2 colors. This is the problem that designers see. It doesn’t require systematic changes but it does require identification of the loop, and then there are methods to fix it.”

One other problem is when you think of that last ninth polygon as an L, where at the corner of the L where the two lines join. That could make a split. The foundries decide on the split based on their process. They may not do a split at a joint. They may do it on a straighter edge. But when they make the joint, there is an overlay of these two masks. If you think of that ninth polygon – that eighth polygon that got split into two pieces—they will expose first one joint, then etch it, then expose the remaining portion of that L, then etch it. Now you have to make sure these two exposures make that one L that the customer wants. The idea is that the overlay is a problem. In manufacturing, it’s called overlay. In design, it’s called stitching—meaning they have to make sure there’s enough overlap at the split/splice location. So that is another issue that design tools have to give good feedback about.

These coloring issues are exactly why Mentor Graphics looks at this differently, Abercrombie said. “Displaying the error as a ring is so much more productive than showing the colors because this was the initial mental struggle [with double patterning,] and the request that came up most was, ‘I want to see the colors.’ That was the first thing designers said—only the colors. And I said, ‘Why do you want to see the colors?’ ‘So I know what to fix.’ Seeing the colors is actually a misleading thing. If you imagine an odd cycle there is no legal way to color it. That’s the problem. That’s why it’s an error. There is an odd number of things interacting, and you have two colors and you can’t divide and odd number by an even number or you get a remainder. So you can’t color them alternating colors in an odd cycle, because somewhere in that cycle you’re going to end up with the same two colors next to each other. When you ask the tool to show you colors, inherently the tool can only show you the wrong colors because in that configuration there are no legal colors.”

A second problem is that there are many, many different wrong colorings that could be shown because there is no right one, so the selection of which one to show is completely arbitrary.

This is why Mentor approaches this type of error with a ring scenario. “By showing colors, there could be a random chance that I showed you that one error that may be the hardest one to fix and hence I’ve pushed you down a path of most work,” Abercrombie said. “By ignoring the colors—not showing the colors, if at all possible because it’s just going to mentally push you in a direction—look at the ring and look at the options that it is showing you as a benefit. Now you have multiple choices and you can do what is best for you.”

Not so scary

Mentor’s Abercrombie asserted that as scary as it is for designers to learn something new, “like anything else once they start dealing with it they learned pretty quick and they found it’s not those it’s not as overwhelming as they thought.”

And there are even some nice things about double patterning errors, he said, in that although the error can seem large and involve a lot of shapes with a lot of spaces around things, the advantage of it is that you have multiple options for fixing it. In a given odd cycle, for example, you only have to break one separation within the network of polygons that are interacting and it is clean. You don’t have to fix them all. You only have to fix one of them.

“In that way a single error has many ways to fix it and that’s better than a lot of other DRC rules,” he said. “When the check is like ‘me and my neighbor’ and how far away we are—when you only have one option you’ve got to fix that space and that may be difficult because of the ramifications of trying to fix it. When you try to move those edges, or you might have to move vias and other shapes, that could be a very complicated location to fix. But with a DP error, the fact that it’s got multiple options gives some freedom to say, ‘Here’s an odd cycle with five different spaces and there are actually five choices that I can make.’ I can look at which one is easiest for me.”

Saleem Haider, senior director of marketing for physical design and DFM at Synopsys, agreed. “[DP errors], at the highest level, look pretty much the same as a general design rule error. Even without double patterning at 28nm we have a fairly complex set of design rules that the foundries gives us and design implementation has to adhere to those. Ten years ago, pretty much all design rules were somewhat width- and spacing-oriented. Now the rules are very, very complex. Some of them are based on the size of the object itself, and there are spacings from corners and edges and sides, etc., so it’s a fairly complex set of rules.”

Double patterning becomes a part of that, so at the end of the day, a DP violation or a DP error is going to, generically speaking, look just like a design rule error, he said. Just as if there was a design rule error in the design, the foundry would not accept that design because when the design comes into the foundry, one of the first things they do is run design rule checking on it to see if it meets the checking criteria that they specified. If the design doesn’t meet it, they will send that design back to the design team. It’s part of the incoming process. It’s the same for DP.

Like many new technologies, understanding double-patterning errors is just a learning process, Mentor’s Abercrombie concluded. “The foundries first had to figure out what it is they want to provide and support and work with us to make the tool capabilities to do that. Now that they’ve rolled out the decks to the customers it’s been more about educating the customer to overcome that initial shock of something new and get them educated. As soon as they play with it for a little while, it comes pretty fast. They’re smart. For the ones that have already made that move, they are settling in pretty quickly.”

Additional resources:

http://www.mentor.com/solutions/foundry

http://semimd.com/mentor/

http://www.synopsys.com/Tools/Implementation/CapsuleModule/ic_validator_wp.pdf

http://www.synopsys.com/Solutions/EndSolutions/20nmdesign/Documents/20nm-and-beyond-white-paper.pdf

By Mark LaPedus
In New York, Saratoga County is booming. Saratoga counts on several growth engines, including semiconductors. In the county, GlobalFoundries is ramping up a new fab and recently announced an R&D center. In addition, there is a new push to build casinos in the county to further boost the local economy. But the local mayor is apparently against the idea, according to reports.

Samsung overtook Apple as the top worldwide semiconductor buyer in 2012, according to Gartner.

In 2012, Samsung almost doubled its foundry sales and surpassed UMC to become the third-largest IC foundry in the world, according to IC Insights. IC Insights believes that Samsung will challenge GlobalFoundries for the No. 2 spot in the rankings in 2013.

Synopsys announced immediate availability of its EDA solutions for finFET-based semiconductor designs. GlobalFoundries and Samsung are collaborating with Synopsys in the arena.

Soitec announced its results for the third quarter. The mobility-driven markets continue to offset PC segment weakness.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.92 in December, up from 0.79 in November, according to SEMI. “Both bookings and billings increased in December, but remain below figures reported one year ago,” said Denny McGuirk, president and CEO of SEMI. “While uncertainty remains regarding the 2013 equipment outlook, the foundry and advanced packaging segments are the key investment drivers at the beginning of the year.”

SEMI announced that Rudy Kellner, vice president of the Industry Group at FEI, has joined the SEMI North American Advisory Board (NAAB).

The new edition of the International Technology Roadmap for PV (ITRPV) will be presented and published at the upcoming PV Fab Managers Forum, according to SEMI.

The Chinese end market dominated shipments of solar photovoltaic (PV) panels during the final quarter of 2012 with 33% of global end-market demand, according to NPD Solarbuzz.

Solar PV equipment spending was $3.6 billion for 2012, a 72% decline from the peak of $12.9 billion in 2011, according to NPD Solarbuzz. Finlay Colville, vice president at NPD Solarbuzz, said: “Spending for 2013 is forecast to decline even further to $2.2 billion, levels not seen in the industry since 2006.”

Mentor Graphics announced a hardware emulation solution for ARM Cortex-A9 MPCore processor-based system-on-chip (SoC) designs.

After two straight years of contraction, the global DRAM market has the opportunity to rebound to double-digit growth in 2013, according to IHS iSuppli.

A new generation of lower-cost and more appealing ultrabooks is expected to help cause global shipments of solid-state drives (SSDs) to more than double in 2013, according to IHS iSuppi.

With emerging economies such as China and India slowing down, the Southeast Asian nations are emerging as key destinations for multinational companies, both as markets for their products as well as a source for new technologies, according to Lux Research.

By Ann Steffora Mutschler

For reducing cycle time of DFM checks prior to manufacturing, pattern matching is a topic of great excitement as of the past few manufacturing nodes.

The idea behind the technology is that there are certain patterns in the physical layout of the chip, which unless they are addressed, won’t come out right. That’s what causes the drama, observed Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. “The way we used to do things is not going to work anymore.”

It’s common knowledge that getting a good yield at advanced nodes is getting tougher. “It’s a big challenge for foundries because the lithography equipment is still the same and they are pushing the technology nodes,” said Manoj Chacko, product marketing director at Cadence. “At 28nm they are using the 193nm immersion stepper or scanner. At 20nm it is the same equipment; at 16nm it’s probably going to be the same machine and most likely for 10nm it is likely to be the same machine unless EUV kicks off. What’s happening here happening here is that the wavelength is 193nm, immersion has to improve the K-1 factor, but the foundries are pushing feature sizes more than 10 times smaller. So the lithography issue is a big problem.”

Finding lithography issues in a design is based on computational lithography, which is an extremely compute-intensive process. “Compute-intensive processes are good in manufacturing and were okay at 40nm, but as we go down to 28nm and 20nm the computing power needed is not like just 1X or 2X. It’s almost like 5X or 10X more, so the number of CPUs needed to do a job is higher,” Chacko pointed out.

While a fab or foundry may be outfitted with the CPU power to handle these processes, the design team is not. This is where is where pattern analysis comes in. “Just like the same thing we are hearing in the Web space— they call it big data—there is a similar analogy here. How do you process large amounts of data in an intelligent way? That is the whole crux of this thing.”

Cadence, Mentor Graphics and Synopsys all have worked with the foundries on essential pattern matching meant to evolve DFM signoff with minimal impact to the design community. Each has its own approach, but they all meet the requirement of the foundry for signoff.

In the case of Cadence, following the acquisition of CommandCAD in 2007, the company includes pattern classification as the core essence of its approach in order to reduce the sheer number of patterns from the foundry, which could number in the hundreds of thousands depending on the process.

“What we do for foundries with this technology for pattern classification is to try and reduce hundreds of thousands of patterns into pattern families. If we can reduce say 100,000 patterns into 100 patterns, this becomes an economical and deployable capability for the design community. We are able to reduce and classify hundreds of thousands of patterns into pattern families. So what pattern matching tools do is they have the tech file, which is a library of about patterns from the foundry, and after they’ve done routing they do a pattern certain match. Whatever that patterns are found that information is fed back to the router to avoid those patterns,” Chacko said.

In the case of lithography hotspot checking, which also falls into the pattern-matching genre, it turns out that there are certain specific patterns and combinations of physical shape. When one shape of a certain type is next to another shape of this type and it is exposed to lithography, it will not come out right. There may be some pinching or shorts– and those patterns need to be fixed, Haider explained.

“The set of patterns that are bad—the violating patterns—for a given node is not necessarily a static set. So we start with a large number of potential violators. As the process matures the people in the factory fine-tune the processes and the patterns are not violators anymore, so slowly the need for very strict checking gets mitigated. This is what we saw at 45nm. We are seeing a bit of it at 28nm as well, and at 20nm it remains to be seen,” he continued.

Identifying and preventing problems
At Synopsys, Haider noted that the company has been working on hotspot checking technology for a long time and has invested in internal development. The company comes at the problem from two trajectories.

First is the ability to perform a detailed lithography simulation on the entire design whereby it is very exact but admittedly heavy. There is also a pattern matching technology where instead of simulating the entire process Synopsys works with the
foundry to obtain a library of potentially offending patterns, searches the design for those, and that is 1,000 times faster than the first approach.

Technically, explained Stelios Diamantidis, product marketing manager at Synopsys, “with pattern matching technology what we’re doing is taking a problem that is very mathematical on the foundry side—it is very much related to optics and simulation and applies a lot of high complexity convolution to design shapes—and we are turning it into a much more manageable physical design and verification problem that is closer to a traditional design rule check or a search-and-repair type application. That’s really the special sauce in the pattern matching technology—how to transition from a foundry-side manufacturing application into something that can be much more designer friendly and also much more intuitive and usable. The technology itself really works with managing geometries. It leverages our hierarchical design analysis validator, which we use for design rule checks, but then translates this or augments it into a two-dimensional space, multi-shape search capability.”

Michael White, director of product marketing for Calibre physical verification at Mentor Graphics, agreed that the challenge that engineers have seen is that doing simulation over the entire design is very computationally expensive and the run times for doing lithography at the full chip level are prohibitively long. “Lots of folks were doing full litho on their IP. They were doing full litho on their IP blocks as they were building up their design. But when they were getting to the full chip level the pain level was pretty high. That is still true today where folks are doing full LFD simulation at the cell or block level as they are building up their design. But again, you need to come up with a different strategy at the full-chip level.”

That is why pattern matching has become so interesting at 28nm as the way to make it practical to do full-chip lithography simulation. Using the equation-based DRC technology, he noted that when a match is found, the designer can get a hint on how to fix the problem within the flow.

Interestingly, White has observed more rapid adoption by fabless companies because while producing a new chip, “they get back that their yields aren’t quite what they want. Their failure analysis teams working at the last chip [tell them], ‘We had a failure here, we had a failure there.’ The failure analysis team typically are former foundry or fab folks, so they are used to looking at a CD SEM and looking a series of shapes. The traditional communication methodology was for them to draw on a piece of paper and say, ‘I saw this set of shapes.’ Somebody then tries to use a text-based syntax to describe that, and then they go off and do checks to find out if there are other designs in process within the company, and whether this pattern is present anywhere else. That whole flow takes weeks, and you are going from a CD SEM image, to something on paper, to a text-based syntax. You are transforming how you are communicating what the problem is through multiple different mediums. It’s not very effective.”

Pattern matching allows the DFM engineers to clip out patterns from the GDS and use that to populate a library of weak and detractor patterns, which significantly speeds up the feedback loop from what they were finding in failure analysis and test back up to the design teams. That allows the teams to start fixing yield detractor patterns and stop using the patterns that cause problems, he said.

By Mark LaPedus
Lux Research has released its top 10 emerging companies in 2012. It features leaders in bio-based materials, 3D-printing, photovoltaics, drug delivery, energy efficiency and a fabless chip maker.

Soitec announced the grand opening of its North American solar manufacturing facility in San Diego. The concentrator photovoltaic (CPV) modules produced in San Diego will support hundreds of MWp of contracts for utility-scale projects in California.

IHS has released its top 10 predictions for the solar industry in 2013. Here’s one prediction: Many integrated players, particularly those based in China, will fold up shop in 2013.

Ericsson will take a non-cash charge related to its 50% stake in ST-Ericsson. Ericsson continues to believe that the modem technology has a strategic value for the wireless industry. ST-Ericsson is working on a technology based on SOI. Ericsson will continue to explore various strategic options for the future of ST-Ericsson assets. To acquire the full majority of ST-Ericsson is, however, not an option.

In a blog, Gold Standard Simulations has offered some advice to the SOI community: Metal-gate-first FD-SOI is good but gate-last could be spectacular.

Strain technology has been a key enabler for improving transistor performance. But there is a question whether stressors will maintain their effectiveness in IC scaling. Also which stressors will be most effective as the industry moves from planar to finFETs? According to a paper from Applied Materials and Synopsys at IEDM, the answer is clear: “S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled finFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in finFET devices for the 22nm node and remain effective with conservative scaling of contact/gate CD only.”

Worldwide wafer fab equipment (WFE) spending is forecast to total $27 billion in 2013, a 9.7% decline from 2012, according to Gartner. In 2012, WFE spending is on pace to reach $29.9 billion, a decrease of 17.4% from 2011 spending. The market is projected to return to growth in 2014.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.79 in November, according to SEMI. This compares to a ratio of 0.75 in October.

Hewlett-Packard’s Inkjet and Printing Solutions division has reaffirmed its use of Mentor Graphics’ Pyxis Custom IC Design Platform as HP’s standard solution for custom IC design and verification. In addition, HP has selected Mentor’s Questa CDC as its standard solution for clock-domain crossing (CDC) verification.

Mentor announced comprehensive design, manufacturing, and post tapeout enabling support for Samsung’s 14nm IC manufacturing processes. In addition, Mentor announced advances in its T3Ster+TeraLED measurement and characterization hardware.

Ultratech has acquired the assets of Cambridge Nanotech. Based in Cambridge, Mass., Cambridge is a supplier of atomic layer deposition (ALD) systems.

ASML Holding and Cymer provided a status update regarding ASML’s previously announced pending acquisition of all of the outstanding shares of Cymer. ASML is responding to a request for additional information from the Antitrust Division of the U.S. Department of Justice regarding the transaction. This second request is part of the regulatory review process under the Hart-Scott-Rodino Antitrust Improvements Act of 1976. ASML and Cymer continue to anticipate completion of the transaction in the first half of 2013.

In a rare move, the Federal Trade Commission (FTC) is blocking a semiconductor acquisition. The FTC issued an administrative complaint seeking to stop Integrated Device Technology’s proposed $330 million acquisition of PLX Technology. The deal allegedly would give the combined firm a near-monopoly in the market for a type of integrated computer circuits called PCIe switches. In response, IDT and PLX have mutually agreed to terminate their merger agreement.

Micron posted a loss. “Unit shipments in both segments were impacted by unspecified manufacturing issues, although we do not believe these related to yields and more about execution on the back-end. Without these issues, we believe Micro would have beat consensus forecasts,” said Hans Mosesmann, an analyst with Raymond James. “Management provided a brief update on the Elpida acquisition, reiterating its expectation for the close sometime in 1H 2013. We also see positive strategic merits from the deal, including a significant addition to the company’s mobile DRAM portfolio (mobile DRAM share goes from ~4% to ~21%), with Elpida having a supply agreement with Apple.”

For the first time in 14 years, Nokia will not sit atop the global cellphone business on an annual basis at the end of 2012. Samsung is set to seize the mobile handset market’s top rank, according to IHS iSuppli.

Driven by continued demand for smartphones, tablet PCs, and other personal media devices, the total flash memory market (NAND and NOR) is forecast to grow 2% to $30.4 billion in 2012, surpassing the $28.0 billion DRAM market in sales for the first time, according to IC Insights.

IMS Research recently released its fourth annual video surveillance trends for the year ahead. Here’s one trend: The increased popularity of HD and megapixel resolution security cameras has been a hot topic in the video surveillance industry.

VLSI Research is raising its 2013 IC forecast to a +10% jump. “We are much more bullish and expect this to be an ASP-driven upturn due to the constraints in the capacity that the industry will face next year, especially in the memory market. As a result, we project IC units to increase 7% and ASPs to rise 3%. We’re seeing plenty of positive ‘Christmas black-hole’ indicators that the first half will be much hotter than thought before Thanksgiving.”

The semi equipment market has been downgraded to -16% in 4Q ’12, according to VLSI. The fab tool market in 2012 is expected to be minus 12.5%. 2013 is unchanged at -5.3%.

By Ed Sperling
The number of restrictive design rules that have to be dealt with by routers at 28nm and beyond has increased by several orders of magnitude compared with several generations ago, creating havoc in the automated tools world and slowing down the entire design process.

At a time when market windows are shrinking, complexity is making it harder to meet even the old schedules. That has prompted everything from new design strategies that incorporate more third-party IP and full subsystems to changes in how long companies stay at one process node and whether they skip nodes. In some cases, it also has led to shrinking the verification schedules, which raise questions about just how bug-free chips will be in the future, and how much can be accomplished once chips hit the market through software updates.

Particularly hard hit are the routers. Routers are a key part of any design. Place and route has automated much of this complex but highly redundant task for decades, only to be pushed back into redressing the issue at each successive node. Something has changed over the past couple nodes, though. There is more to consider, and routers are paying the price. Because wires don’t scale as well as transistors, the resistance causes heat and noise that can interrupt signals. That has to be taken into account by the router.

Add to that more metal layers, more and increasingly complex interconnects, and more congestion around memories that are scattered throughout SoCs and the problem of routing becomes even tougher. There has been much work done to solve this problem, one node at a time. But EDA vendors say there is much more to be done at each new node, making the problem worse.

“Yesterday’s routers were overworked, too,” said Aart de Geus, chairman and co-CEO of Synopsys. “But the advances being made are remarkable.”

Whether those advances are sufficient, though, is a matter of debate, particularly at 28nm and beyond. Throw in double patterning at 20nm, and finFETs at 14nm, and it’s enough to create panic in some circles.

“With double patterning and triple patterning, all the EDA guys say everything is ready—and it’s true that most of the pieces are ready—but not everything can be combined,” said Jean-Marie Brunet, product marketing director for litho-friendly design and DFM at Mentor Graphics. “You need to change how you deal with place and route in double patterning. It impacts the router, the placer, how you create router fill and pin access.”

Brunet said there are now about 2,000 to 2,500 rules for the router to deal with. And he said almost every major EDA player’s router does basically the same thing, so if one vendor is wrestling with the problem then so is everyone else.

“It’s no longer just layout that is very complicated. The problem is that the router has to understand the rules and still do all the things that it has been doing. The complexity of vias is unbelievable. At 14nm we’re seeing double vias everywhere, while at 28nm we did not have double vias. And how do you explain to a router that a via is rectangular?”

Rectangular vias were introduced by the major foundries at 28nm. It is uncertain at this point whether they will be replaced by cylindrical vias in the future, but it’s clear this has made routing more difficult. More complexity equals more design rules.

“We used to have 10 pages of design rules 20 years ago,” said Mark Bohr, senior fellow of the technology and manufacturing group at Intel. “It’s now more than 100 pages, and that puts a huge burden on automated layout and routing. You need to work on the tools a couple years in advance.”

From a design standpoint, each new node requires more restrictive design rules just to make sure that chips are functional and that yield is sufficient. But adding 3D transistors and double patterning require another big jump in the number of design rules. Bohr, who is working on the 10nm node, said Intel is now in the early development phase of defining design rules for that node.

“This is the price we pay to expand 193nm immersion lithography,” he said. “The good news is that we can re-use some of the tools. The bad news is that it requires a lot more rules.”

GlobalFoundries is working on 10nm place and route tools, as well, according to CTO Gregg Bartlett. “This requires a lot of collaboration across the ecosystem,” he said. “We’re in early discussions on this.”

Going up
One of the ways that chipmakers have dealt with this kind of complexity has been to add more metal layers. This is a sort of crude stacked die approach, rather than one using through-silicon vias and separate die or subsystems, but it brings its own unique brand of problems from a design standpoint.

“There are two challenges as far as the router goes,” said Rob Aitken, an ARM fellow. “The first involves metal layer one rules, which need to have bi-directionality—vertical and horizontal. Then there is everything else. But a huge amount of the complexity in the rules is the interaction of the vertical and the horizontal. That can bring it to its knees.”

And increasingly it has. The amount of time spent on the routing side of the design is increasing, which is part of the reason there has been such slow movement to the next process node. It’s also one of the reasons there has been such an explosion recently in the design for manufacturing software market, which serves as yet another checkpoint for rules violations.

FinFETs will add yet another volume of design rules, which is one of the reasons that fully depleted silicon on insulator (FD-SOI) has gained more attention lately. The rules are basically the same, making it an attractive alternative all the way down to 14nm. After that, it is likely that both finFETs and FD-SOI will be required.

“The big question is what is the turnaround of the routing capability,” said Mentor’s Brunet. “One way you get around that is to turn off all the features when you test it, so it looks good when you bring a product to market. But that doesn’t work for long. And improving layout at the end of the design cycle is difficult.”

By Mark LaPedus
The auction of ProMOS‘ 300mm fab ended in failure this week. There were no bidders for the Taiwan DRAM fab, as the price was considered too steep, according to reports. The bidding for the fab will re-open next month. At one time, GlobalFoundries, TSMC and UMC were interested in the fabrication facility. Now, Taiwan foundry vendor Vanguard is the leading contender for the facility.

GlobalFoundries is embarking on a long-term strategic initiative, called “Vision 2015,”which will include the expansion of its Singapore-based 300mm fab for advanced mixed-signal processes. However, the company reduced the site workforce by approximately 300 employees, or about 4% percent of its Singapore employee base, due to the softening of the current macro-economic environment.

The Semiconductor Industry Association (SIA) has elected GlobalFoundries CEO Ajit Manocha as its 2013 chairman and John Kelly III, IBM senior vice president and director of IBM Research, as its 2013 vice chairman.

Applied Materials plans to combine two business units, Energy and Environmental Solutions (EES) and Display, under one leader. Ali Salehpour, a former senior vice president at KLA-Tencor, will join Applied as group vice president and general manager of the EES and Display groups. As part of the changes, Mark Pinto, executive vice president and general manager of EES, and Tom Edman, group vice president and general manager of Display, announced their intention to leave Applied.

For the quarter, Mentor Graphics reported revenue of $268.8 million, non-GAAP earnings per share of $0.32, and GAAP earnings per share of $0.27. “Revenue and earnings were records for Q3. Mentor and the electronic design automation industry continue to benefit from the semiconductor industry’s transition to the next generations of technology,” said Walden Rhines, chairman and CEO of Mentor Graphics.

The Collaborative Alliance for Semiconductor Test (CAST), a SEMI special interest group, has elected new leadership. Elected by CAST was Chris Portelli Hale, manufacturing test director at STMicroelectronics, as CAST chair, and Octavio Martínez, senior director of engineering at Qualcomm, as vice chair.

Tokyo Electron Limited (TEL) has cancelled its joint solar venture contract with Sharp and dissolved the joint venture Tokyo Electron PV Ltd. set up by both companies. In February 2008, TEL and Sharp embarked on the development of plasma CVD systems for use in thin-film silicon solar photovoltaic cells. At present, Sharp appears to be in financial trouble. Meanwhile, TEL has also been on an acquisition spree. In March, TEL announced the acquisition of Oerlikon Solar. In May, TEL reached a definitive agreement to acquire NEXX Systems.  In October, TEL acquired FSI International. In November, TEL reached a definitive agreement to acquire Magnetic Solutions Ltd. MSL is engaged in the development, manufacture, and sale of magnetic annealing systems.

David Lam, founder of Lam Research in 1980, and currently chairman of both Multibeam and the David Lam Group, has been selected for induction into the distinguished Silicon Valley Engineering Hall of Fame. Other eminent technologists selected for induction include: Aart de Geus, chairman and co-CEO of Synopsys; Martin Hellman, professor emeritus of electrical engineering at Stanford University; and David Hodges, professor emeritus of the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley.

Here’s the current climate for VLSI Research’s so-called “Weather Report,” which gives a pulse on the IC industry: “The clouds are clearing, revealing a tall mountain to climb. Order activity jumped higher for the first time in nearly six months, led by foundries and logic IDMs. The uptick is seasonal and it’s coming off very low levels as chipmakers remain very cautious about prospects in 2013 due to macro and fiscal uncertainties. Moreover, order activity is down nearly 9 points from last year’s levels, which suggests that the seasonal increase in Q1 will be more subdued from last year. We expect Q1 sales to increase 10% sequentially.”

Despite soft macroeconomic conditions, the market for mobile communications equipment will grow by a robust 13 percent this year, propelled by climbing shipments of mobile handsets and tablets, according to iSuppli.

Samsung and Apple are forecast to dominate the smartphone market this year. In total, these two companies are expected to ship an estimated 353 million smartphones and hold a combined 47% share of the total smartphone market in 2012, according to IC Insights. Smartphone suppliers under pressure include Nokia, RIM, and HTC, each of which is expected to register steep double-digit year-over-year declines in smartphone unit sales this year.

Who’s winning the tablet wars? The answer: Apple, Amazon and Google. The loser? Microsoft. Apple is expected to ship 67.7 million iPads in 2012 and 83.5 million in 2013, according to FBR. The iPad mini is off to a slow start. And Samsung is trailing the pack with the Galaxy Tab. Samsung will ship 6 million Tabs in 2012 and 7.4 million in 2013, according to FBR. Craig Berger, an analyst with FBR, said: “We think Apple will manufacture at least 7.5 million iPad minis in 2012, and 18.5 million units in 2013. We now believe Amazon will manufacture about 10 million units (of the Kindle Fire HD) in 2012 and 15 million in 2013. We think the Google Nexus could move more than 6 million units in 2012 and about 10 million units in 2013. Contrary to what we see for the Kindle Fire and Google Nexus, we believe the first month’s sales of the MS Surface RT tablet have underwhelmed expectations. We estimate production of all Surface tablets, including the x86 models available in 1Q ’13, to be about 3 million units in 4Q ’12, with sales perhaps trending around 3-5 million units in all of 2013.”

By Ann Steffora Mutschler
Semiconductor Manufacturing and Design sat down recently to discuss how the industry is making 3D ICs a reality today with Sylvan Kaiser, chief technology officer at Docea Power; Steve Smith, senior director for 3D-IC strategy at Synopsys; and Ahmed Jerraya, director of strategic design programs at CEA-LETI.

SMD: How far are we from having the models we need to enable 3D ICs? Are we going to get them from the foundries?
Smith: You do inevitably have to get basic models from the manufacturer or whoever is supplying the source of the materials even. We’ve talked about models of manufacturing materials—chemicals even. There are models for everything. But certainly the consumer that we’re talking about in this room is a semiconductor design engineer or a packaging engineer so they’re going to need to know what rules they need to follow to get their device manufactured within enough reliability, performance, longevity and cost in order that I’m going to be able to take responsibility on behalf of my company or my employer. It goes back to the first question of who is responsible. It’s the guy who is writing a check, but there’s trust. And that trust is done through a formal contract, a set of models. The models come from the engineering work that the supplier has done and the work that they do is often done based on work that their equipment manufacturers did alongside research organizations and universities around the world.
Jerraya: In fact what you have today you have many of the pieces. The work today is to put these pieces together and make it simpler, more automated. Process related modeling is almost there. We know all of these have been done for some cases, for some technologies; now the point is how to make this all automated and inserted in the tools, all the backend tools, all the modeling simulation, all the physical simulation, the power, thermal, mechanical simulation—all those things we need. The pieces are there.
Smith: We were talking about collaboration earlier. I see a lot more now even within our customer base that the semiconductor design companies historically have had separate departments responsible for each of these pieces: a packaging department, an IC department, a CAD or EDA department, IP modeling department, and more. For the first time I’m starting to see them have meetings with their vendors together, which hasn’t happened in my experience. I’ve been in EDA for over 30 years and I haven’t seen that before so I think they’re forced to talk more closely to one another inside the organization because the challenges are coming from the combination of the package, the interaction with the ICs, the stacking, the foundries and the vendors. It’s happening naturally.
Kaiser: Something also that is encouraging from my viewpoint is that the possible targeted systems with 3D have been clarified, and that’s very encouraging. Now we can clearly see different products that can be targeted with 3D and that’s very encouraging because it gives the objectives to reach. And as an EDA provider this really gives the direction to follow. Now with 3D we can really see that some products, maybe memory cubes, there are the interposers, there are the memories on digital logic—these are very clear targets. This really gives the path towards the tools development and collaboration.

SMD: What is the biggest weakness other than the integration piece that we talked about?
Smith: It’s not any weakness. I think it’s more just balancing in the force of business. It only becomes unbalanced if technology is no longer able to deliver reliably the next generation. Everybody’s been predicting Moore’s Law is going to die. Well, it’s still going on, and we’re talking about 14nm. With packaging, they’ve been talking about wire bonding eventually giving out or memory design. We’re still dealing with DDR and low-power DDR, DDR2 and DDR3. Each one of those extends the lifecycle of a certain technology so the question is, at what point does it become imbalanced for a particular company who has a need to fill? When that happens they have to fill the void with the next jump, and in this case it will be 3D or 2.5D. It’s always the same question. It’s not a matter of if, but when. The technology is there. I think we are starting to see signs now of life with a certain set of classes of application. We’ve already seen memory design done in stacks so we know that that can be done. We have also seen 2.5 D being done with a number of companies like Altera, Xilinx, TSMC, and the next one seems to be showing signs of life right now so if we are lucky we might see next year at DAC an actual physical example. I know we’ve said that for many years, but it actually as long as the imbalance stays there it’s going to get filled with a real device very soon I think.
Jerraya: 3D has been around for long time, and there has been a lot of hype around it. Today we see the light in the tunnel. Coming back to the question of the strength and the weakness, it relies on the business part because there are two kinds of forces. Some people are willing to control this 3D and take the benefits, and some people are scared of it because it’s going to change business. In fact, what we are near to making, which is 2.5D, will create a change in the PCB business in system integration. It changes in terms of the packaging part but also the procurement of chips, because we are going to buy chips at advanced nodes provided by some design houses or whatever they are, and we will then package them into a system. This is new, and it is a step further in integration.
Smith: Even though we’ve been doing this for years we could be completely thrown off by some random element. We will look at our other favorite topic: smart phones. Who would have thought five or six years ago the phone companies could have a game changer? It wasn’t even new. It was existing technology. But somebody with the right idea and the integration skills that made it happen. The same will be true here.

Part one of this series can be viewed here. Part two is here.

By Ann Steffora Mutschler
SemiMD sat down recently to discuss how the industry is making 3D ICs a reality today with Sylvan Kaiser, chief technology officer at Docea Power; Steve Smith, senior director for 3D-IC strategy at Synopsys; and Dr. Ahmed Jerraya, director of strategic design programs at CEA-LETI. For part one of this series, click here.

SemiMD: Because CEA-LETI has direct experience with this, what was the biggest challenge to creating the 3D design prototype?
Jerraya: Here we will talk about the design side—putting things together—because on the technology side you have some challenges. In putting things together the key problem was the estimation of what we will have inside on the physical side like the thermal aspects, for example. Here in many aspects we were progressing in a blind way, we didn’t know what will come out even if we made some simulation but still in fact the tools are in early phases of doing this. Also, testing was a little bit of a challenge.

SemiMD: What aspect of the testing was the biggest challenge?
Jerraya: Everything had to be invented because you need to imagine a new process for testing. There is lots of theory about it the last two or three years. Lots of people are talking about good theories that were helpful for what we did. But the problem is you need to make choices. It’s like if you are setting standards or something like that. It’s not very simple. You need to make decisions.
Smith: [What CEA-LETI did] is an example of what a semiconductor company is going to have to deal with when doing this for real. I don’t mean they didn’t do it for real—they did—but not in a volume-production, commercial environment. It’s obviously at a different scale when you are doing it in volume and you need to test to a high degree at least those components or parts that are most likely to fail in the system. There are question marks now as far as what are the elements of the 3D stack that are required to be tested because they are out of their failure mechanisms. Is it the TSVs, the microbumps and so on? One of the challenges that we’re also hearing is the mechanical aspects of testing the die, either on the wafer or after being microbumped. Are we going to have probe pads or probe pins small enough to be able to do that? Do we need to create new test access methods? There’s a lot of theory around that, but again, we still haven’t seen any real commercial products in the marketplace and so, while it might seem like a good idea to say, ‘EDA needs to do better,’ we always come after the commercialization of technologies. That’s always been the case and we’re not going to be first this time…I don’t think there’s anything unusual about that. I think the brave, maybe the foolhardy, go ahead regardless and they figure it out and eventually they make things work. There are a lot of smart people in the industry. In my opinion, if I was to answer the question…the biggest impediment is not a technical one, it’s again more of a business one. When does the economics make sense for a particular product? Or it may be a risk reduction. Who is going to take the first stab of putting a project on the table – putting up that challenge of flying to the moon with 3D IC?

SemiMD: On the thermal side of things, what technically has to be done right now to get people ready for 3D?
Kaiser: The thermal issues even for 2D or 2.5D are increasing because of shrinking geometries, so that is just a logical progression of the technology. People are more and more aware of these thermal issues even for 2D, but with 3D it’s certainly exploding. That’s interesting and everybody is worrying about that. I think one of the first missions I would say is to explain that there are actually several issues already linked to temperature. Thermal is not only one thing. You can talk about very localized thermal issues relative to mechanics in 3D relative to TSVs. You can talk about thermal gradient over the whole chip that will cause timing issues between the IPs communicating and you already can talk about thermal budget globally on the system. This budget may be imposed by the system manufacturer or the equipment manufacturer because you cannot have a handheld device at 100 degrees Celsius. So in terms of temperature and thermal issues, there are several aspects relative to thermal issues.
Smith: Certainly the phases are awareness and education because you don’t want to be surprised; and then comes modeling and analysis and having that available so that smart engineers can use techniques to redesign or circumnavigate the issues. The last phase is the automation. You can only automate something when you know what steps are the best. With 3D IC what we’ve got today is a basic toolkit that you can actually use today’s commercial IC design tools to add TSVs and routing, and things like that. But you still have to have the smarts of the system engineer to package it around it. That hasn’t changed and that’s not automated in any tool today. All you can do is analyze and verify. There’s no automation.
Kaiser: Yes, it’s like a pyramid: You have to have the models and to really understand which issue you would like to tackle and the appropriate model for that. Below you have the tool, and on the base you have the methodology, which provides the automation. And this pyramid has to be constructed for temperature analysis.

SemiMD: We need to do a lot of modeling. We need to model the TSVs, the package, what else do we need to model and how are we going to do it? What is the best way to approach this?
Jerraya: There are two dimensions you need to think about. First, it’s all different physics you are going to model. And second, you need to model these at different levels. Today, for PCBs, we have lots of tools working on the physical level for PCB, but for this kind of integration…the iteration is so long and so expensive that you need to make sure that what you are doing is right. This is why you need to analyze all the different physics—mechanical, electrical, thermal—and you need to do them at the higher level before you design the different chips that you are going to integrate together. And then, of course, you need to model at the physical level what we are doing in the PCB. The most important thing is modeling at the higher level before your final implementation.
Smith: As you’re going to decompose the system into multiple chips or components or even in a single IC, you’re going to need a budget across the entire chip. It’s typical in a complex design today or a system that you may have tens or hundreds of design engineers, each with his own budget or block of chips to deal with. Ultimately you can be more accurate in smaller parts of the design, which maybe is necessary to make sure you achieve the budget. Nobody wants to be the one that goes over and then has to steal from another neighbor. That’s a methodology that’s been evolving for decades and I think it’s another dimension that you have to take into account, but it’s still driven by the overall system architecture or the environment into which this 3D IC package is going.

SemiMD: When we talk about modeling at different levels, is this a single model or that we can pull different characteristics out of? How will that look technically?
Kaiser:  For thermal simulation, one of the new issues with 3D is that TSVs might have a big impact at the same time. They are very small devices and today it’s not really established when and with which format will be provided to the designers. That’s something that must be solved and tackled today. The best way to deal with that is to discuss it with the foundries with the companies enabling the technology to understand what will be in the flow, what they will be capable of providing and at which stage in the flow.
Jerraya: It’s like we are adding new devices in the design. For a design kit you will need to have the corresponding p-cells, the corresponding rules for constructing functional devices, and all of these need to be inserted in that design kit.
Smith: There are different models for different aspects and it’s truly fundamental, and maybe this is where EDA or at least the tools come into play. There are certain basic tools that can be used to do early analysis of new devices. For example, in the area of through-silicon vias, the TSVs have been well known for decades but never really embedded within a silicon process in real life. A lot of the early research was done with finite element analysis type of tools to model a single TSV and its surrounding silicon area. That’s one model, and it’s done to provide the building blocks in which to create a higher-level model in terms of electrical characteristics, thermal characteristics and so on, that can be put into a PDK or a design kit along with a set of design rules. But there’s not going to be one model that rules all. There is nothing unique about this other than the fact that it’s relatively new, but we are getting to the point where the real stuff is coming very soon.

By Mark LaPedus

IC makers have been looking at the electric vehicle industry for growth. So whatever happened to the electric car? Toyota has scaled back the sales targets for its electric car. According to Lux Research, the head of Toyota’s vehicle development gave a vote of no confidence for the technology, by saying the “capabilities of electric vehicles do not meet society’s needs.” Meanwhile, Tesla Motors recently lowered its sales targets. Another car maker, Nissan, is offering big discounts on the Leaf because of slow sales. GM’s Chevy Volt has struggled to win customers, even though it’s not purely electric. And Fisker Automotive, which uses the same approach as Chevy, has experienced an assortment of problems.

At the 2012 IEEE International Electron Devices Meeting (IEDM), slated for Dec. 10-12 in San Francisco, Applied Materials and Synopsys are expected to submit a paper entitled, “Is strain engineering scalable in FinFET era? Teaching the old dog some new tricks.” “Strain technology has been a key enabler for improving transistor performance in the past decade. With the industry moving toward a 3-D FinFET structure from a planar MOSFET, the corresponding implications on stressor design needs to be analyzed afresh due to strong orientation dependence of stress enhancements,” according to the IEDM abstract from the companies. “In this work we have tried to address both issues; stressor design for FinFETs and scalability of corresponding stress enhancements. We found that the S/D epi remains an effective and scalable source of strain engineering for FinFETs. Contact and gate metals provide new knobs for engineering strain in FinFETs and remain effective with conservative scaling of contact/gate CD.”

Altatech, a subsidiary of Soitec, has introduced a multi-chamber chemical vapor deposition (CVD) system that enables photovoltaic (PV) cell manufacturers to develop and optimize their solar cell designs using advanced thin-film deposition of amorphous silicon and other materials. By performing all deposition processes within a single system, the new AltaCVD Solarlab tool reduces cycle times and materials consumption in fabricating advanced single-junction, tandem-junction and triple-junction PV cells.

GlobalFoundries is preparing to build a three-story, 565,000-square-foot manufacturing research center, according to a report.

While over-capacity continues to plague the global solar industry, the Taiwan PV industry is operating at high-capacity, according to SEMI.

SVTC Technologies is struggling and has apparently cut workers, according to reports, which added that the R&D foundry is mulling plans to close its sites in Austin, Texas and San Jose.  Multiple sources say SVTC may completely shut down. In an e-mail, SVTC declined to comment on the reports. A spokesman for Oak Hill Capital declined to comment. Oak Hill is an investor in SVTC. In 2007, Cypress sold its R&D fab unit to Oak Hill and Tallwood Venture for approximately $53 million. SVTC became a “lab-to-fab” facility aimed at third-party engineering groups.

As it turns out, Tezzaron Semiconductor has signed a contract to purchase the assets of a semiconductor technology development and wafer fabrication facility in Austin, Texas, previously run by SVTC. Tezzaron will continue the operations of this facility while adding capabilities to assemble its own 3D devices.

Struggling Renesas has obtained a $6 billion bailout from various banks. The chipmaker announced the execution of an agreement of a syndicate loan, with Mizuho, The Bank of Tokyo-Mitsubishi UFJ, Sumitomo Mitsui Trust Bank and Mitsubishi UFJ Trust and Banking Corporation.

Sharp has obtained a syndicated loan as it struggles to find investors.

For its 2012 fiscal year, Micron reported a net loss of $1.03 billion. C.J. Muse, an analyst with Barclays, said: “While Micron was hesitant to provide any speculative commentary around the potential Elpida acquisition, management did note that the deal is expected to close in [the first half of calendar year 2013].”

The JEDEC Solid State Technology Association has announced the initial publication of its Synchronous DDR4 standard.

Intel and its OEM partners unveiled the first wave of new tablets and tablet convertible designs based on Intel processors, including the new Atom Z2760, formerly codenamed “Clover Trail.”

Samsung’s foundry business has been selected by STMicroelectronics to provide it with products at the 32/28nm process node.

X-Fab plans to invest more than $50 million in its MEMS operations over the next three years.

Diodes plans to acquire Power Analog Microelectronics.

Gartner says Windows 8 is a big gamble Microsoft must make to stay relevant.

IC Insights believes that the more profitable foundries will be those that keep at the leading-edge of the process technology roadmap.

The average amount of DRAM in each smartphone shipped worldwide is expected to surge by nearly 50 percent this year, according to iSuppli.