By Mark LaPedus
Smartphones and tablets are migrating towards new and faster application processors, basebands, graphics chips and memories.

In the cell-phone chipset area alone, there are a multitude of options and design considerations. Some devices combine the application processor and modem on the same chip. Some are separate devices. In addition, the architectures range from single- to eight-core devices.

On top of that, devices eventually will migrate from planar to finFET transistors. And not to be outdone, there are a couple of major technology platforms to choose from: bulk CMOS and fully-depleted silicon-on-insulator (FD-SOI). Startup SuVolta also has garnered some attention with its dual-gate 2D transistor, but so far it remains an underdog in a highly competitive market.

Needless to say, OEMs face some tough choices and challenges. The prevailing wisdom is that next-generation smartphones and tablets will require more cores and new transistor architectures. After all, consumers want more performance, bandwidth and battery life.

In reality, however, there is no one-size-fits-all technology. As the market continues to splinter into various sub-segments, such as entry-level phones, smartphones, superphones and tablets, there is room for several different architectures and technologies.

Still, OEMs must rethink their design and product choices before jumping on a device with the most cores and the usual processes. In fact, there is a common and oversimplified message that more processor cores translate into a better performance in mobile systems, said Marco Cornero, a fellow and head of advanced computing at ST-Ericsson, a cell-phone chipmaker.

The reality is that mobile designs are much more complex. There are several factors at play in determining the efficiency of multicore systems, such as software, chip frequency, area and power, Cornero said. And generally, quad-core and beyond may be overkill for today’s systems, thereby creating unnecessary costs for OEMs and consumers. “It makes sense to add more cores if the software can utilize them,” he said. “The problem is the software can’t utilize them.”

Going against the grain, he contends that the optimum solution for mobile platforms involves two main technologies: dual-core and FD-SOI. Dual-core architectures provide enough horsepower, and are more efficient, than today’s slower quad-core devices for mobiles. And bulk CMOS is rapidly running out of gas, propelling the need for a new technology like FD-SOI, he added.

Still, there are various tradeoffs between bulk and SOI, not to mention the implications in moving from planar devices to finFETs. “FinFETs move the line quite nicely in terms of power efficiency,” said John Goodacre, director of program management within ARM’s CPU group. “With finFETs, unfortunately, we lose the dynamic range.”

Multicore: Fact vs. fiction
In any case, there are some parallels between the development of processors for PCs and mobile systems. The prevailing wisdom changed almost overnight in 2001, when Pat Gelsinger, then Intel’s chief technology officer, proclaimed that if chip scaling continued on its current pace, then processors could reach the power density of the sun’s surface by 2015.

At the time, IBM, Intel, AMD and others were racing each other to develop faster microprocessors by boosting the clock frequencies. In those days, Intel claimed that its Pentium 4 processor would scale up to 10 GHz, but in reality, heat dissipation issues limited the clock speeds to only 3.8 GHz.

Then, a decade or so ago, Intel and others moved away from the “megahertz race,” focusing instead on multicore designs. That put far greater emphasis on core efficiency and power consumption, but multicore also caused a fundamental disruption in software on the PC. Applications had to be written in a concurrent and parallelized fashion to map the programs efficiently on multiple processors. Even today, parallelism remains a challenge in system environments.

To some degree, history is repeating itself on the mobile processor front, at least according to ST-Ericsson. To prove its case, the cell-phone chipmaker examined the performance of Apple’s iPhone 4S and 5. The 4S is based on Apple’s A5 application processor, which includes dual-core, 800-MHz Cortex A9 chips from ARM. The iPhone 5 is based on Apple’s A6, which has two custom 1.3-GHz cores based on ARM’s technology.

The software performance of the iPhone 4S and 5 were benchmarked using Browsermark, Geekbench and Sunspider. The benchmarks were conducted by AnandTech, a hardware review Web site.

Deriving the data from AnandTech’s benchmarks, ST-Ericsson drew two conclusions. First, the dual-core processors in the iPhones ran below their theoretical peak performances. Not one of the processors in the iPhone showed signs of being “saturated” in terms of CPU efficiency and frequency, according to ST-Ericsson.

Second, the iPhone 5 ran faster than the 4S. This has little to do with dual-core chips, but rather the faster speeds are attributed to “other hardware optimizations, such as an improved memory sub-system,” according to ST-Ericsson.

Like the PC, the problem is that software scales less proportionally in multicore mobile designs, according to the firm. The dual-core design in the iPhone also impacts clock frequency, due to conflicts on the shared resources in the system.

Now, the market is turning up the volume about quad-core. “There has been a lot of marketing about quad-core,” said ST-Ericsson’s Cornero, “but quad-core doesn’t bring a lot of benefits.”

In Web browsing, for example, a system can run 30% faster when moving from single- to dual-processor designs. But a system only shows a 0 to 11% improvement when moving from the dual- to quad-processor designs, according to the company.

Second opinion
Regarding the multicore debate, ARM has a different viewpoint. “With multicore, I spread the work over two cores,” ARM’s Goodacre said. “In aggregate, the number of instructions are about the same or potentially even less. Then, I can start playing a power game with the voltage. You can lower the frequency with the associated cores for that given workload.”

The real question is whether the software can take advantage of multicore devices execute in parallel. “We’ve got applications that are single-threaded. They run perfectly well on a single thread,” he said. “The question is why do I need multiple cores if the existing workloads can work on one? What we’re really seeing today is a lot of individual sub-systems. This is where we can leverage dual- and quad-core. What that means is that everything runs faster and smoother.”

ARM refers to this as explicit concurrency. Multicore designs are likely required in two booming segments—gaming and social media. “In the user interface, scrolling up and down on Facebook can resource four CPUs flat out. Going back and forth on applications in Android is another one,” he said. “When we look at LTE bandwidths, those management threads are fairly significant in terms of IP traffic. So, you might have three dominant threads, plus management. So, four for the design phase is reasonable. One keeps the management in place. Another puts the network tasks in place. The user interface and the applications each require one.”

There are also tradeoffs on the process and transistor fronts. “Bulk, through voltage and frequency scaling, can get your power/performance ratio down plus or minus 50%,” Goodacre said. “FD-SOI has a specific body-bias technique, which allows it to stretch the voltage down even further while still delivering performance.”

When asked about the shift towards finFETs, he said: “The interesting thing with finFETs is that the steepness of the curve is greatly reduced. It’s much flatter. I don’t have much dynamic range in terms of power efficiency,” he said.

In response to the dynamic range issues, ARM proposes the move towards its heterogeneous architecture, dubbed big.LITTLE. In January, Samsung rolled out an eight-core application processor based on the big.LITTLE architecture. The Exynos 5 Octa from Samsung consists of four Cortex-A15s to handle processing-intense tasks, while four Cortex-A7s are used for lighter workloads.

“Why would I go to eight cores? Some threads would be much better off using a smaller processor. That would represent our ‘LITTLE’ core. In effect, we have about four to six times power efficiency difference between our ‘big’ and ‘LITTLE’ cores,” Goodacre said.

The question is whether big.LITTLE is best served by bulk or FD-SOI? “Does FD-SOI stretch the voltage further with big.LITTLE? This is yet to be confirmed until we measure it,” he said.

In any case, today’s dual-core architectures, combined with FD-SOI, are potentially a powerful combination. ST-Ericsson itself has rolled out an integrated, dual-core cell-phone chipset based on 28nm FD-SOI. The FD-SOI part is 30% faster than bulk devices, said Joel Hartmann, executive vice president of front-end manufacturing and process R&D at STMicroelectronics. “We have demonstrated a 50% power reduction,” he said.

One company has put a new twist in the FD-SOI debate. “FD-SOI is a simpler technology,” said Asen Asenov, chief executive of Gold Standard Simulations, a provider of simulation services. “There are fewer process steps than bulk.”

At 32nm/28nm, the statistical variability introduced by the random discrete dopants in FD-SOI is lower than bulk, Asenov said. With FD-SOI, the threshold voltage variation is reduced more than six times and the leakage is reduced five times for almost equivalent drive current, he said.

STMicroelectronics’ FD-SOI technology is based on a gate-first technology. With gate-first FD-SOI, chipmakers could reduce the voltage to below 0.7V. However, Gold Standard’s simulations revealed that gate-last FD-SOI at 28nm would enable a supply voltage below 0.5V.

“If you take metal-gate-first FD-SOI, and compare with 28nm bulk, FD-SOI will still have a lower variability. If you develop metal-gate-last, this will bring additional benefits,” Asenov said. “FD-SOI in general has a very good chance to deliver a low-power extension for 28nm. A lot of the infrastructure has been put in place. There is enough evidence to make the big fabless companies think very seriously about moving to FD-SOI.”

By Mark LaPedus

Raising the ante in the foundry business, GlobalFoundries has added a 10nm finFET process to its roadmap and expanded its technology platform offerings.

The foundry vendor plans to move into production with its 10nm finFET process in 2015, a year after its recently introduced 14nm finFET technology. In addition, the foundry vendor has also expanded its technology platform offerings to five, including bulk planar, super-steep retrograde well (SSRW), fully depleted silicon-on-insulator (minimum), fully depleted silicon-on-insulator (maximum) and finFET.

Perhaps the biggest surprise on the roadmap is SSRW, a technology that controls short-channel effects using a doping technique. For SSRW, GlobalFoundries has been talking to SuVolta about the technology, according to multiple sources, but it’s unclear if the companies  have reached a deal.

Ajit Manocha, chief executive of GlobalFoundries, disclosed the company’s new roadmap during a keynote presentation at the 2012 IEEE International Electron Devices Meeting (IEDM) in San Francisco on Tuesday. During the keynote, Manocha also addressed GlobalFoundries’ capacity plans, 450mm fabs and EUV.  In fact, GlobalFoundries is not counting on EUV for the 10nm node.

His keynote was entitled, “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!” During the keynote, Manocha said the fabless/foundry model is alive and well in spite of recent comments from an undisclosed party.  “Somebody said the foundry business is dead,” he said. “The same company wants to get into the foundry business. Something doesn’t add up.”

The comments may have been directed towards Intel. In a recent interview with SemiMD, Mark Bohr, senior fellow at Intel, said: “The traditional foundry model is running into problems. In order to survive, the foundries will have to become more like an integrated device manufacturer. Being an IDM, we have design and process development under one roof. That’s really a significant advantage.”

At IEDM, Manocha agreed the foundries must act more like IDMs or virtual IDMs, saying the old model simply doesn’t work. “The traditional foundry model is that you work in isolation,” he said. “It doesn’t work.”

In the new model, dubbed Foundry 2.0, there is a deeper and earlier collaboration between foundries and their customers, he said. GlobalFoundries refers to its strategy as a “collaborative device manufacturer.”

New Technologies

As part of its strategy, GlobalFoundries continues to expand and accelerate its foundry offerings.  Within its new 300mm fab in New York, the company has begun ramping the plant for 28nm and 20nm technology. In 2013, the New York fab will be capable of running 30,000 wafers a month. At some point, the fab will capable of running 50,000 wafers a month.

Meanwhile, in September, GlobalFoundries rolled out its finFET technology for the 14nm node. GlobalFoundries is taking a “modular fin” approach with its bulk finFET offering, dubbed 14nm-XM. The 14nm-XM combines a 14nm-class fin with its 20nm back-end-of-line (BEOL) interconnect flow.

By taking the modular approach, the company has accelerated its process roadmap by a year. Early process design kits (PDKs) are available, with customer product tape-outs expected in 2013. Production, which is slated for 2014, will take place within GlobalFoundries’ new 300mm fab in New York.

Then, in October, rival Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) updated and accelerated its process roadmap. The world’s largest silicon foundry has accelerated its 16nm finFET efforts by one quarter and added a 10nm finFET technology to the roadmap. TSMC’s 10nm finFET process, dubbed CLN10FF, is expected to move into risk production close to the end of 2015.

GlobalFoundries moved to keep pace with TSMC. At IEDM, GlobalFoundries disclosed a 10nm finFET process, which is due out in 2015, or a year after 14nm finFET.  “We have accelerated (the 10nm finFET process),” Manocha said after his keynote at IEDM.

At 10nm, GlobalFoundries and others may be forced to extend 193nm immersion, while also going with a multiple patterning scheme. EUV is late to the party and may miss the 10nm node. “10nm will be optical,” he said. “We have evidence that we can do 7nm with immersion.”

GlobalFoundries did not describe the details of its 10nm process. The foundry vendor did disclose it would offer several new technology platforms. Besides planar bulk and finFETs, the company is moving to offer FD-SOI.  In July, GlobalFoundries agreed to manufacture STMicroelectronics’ FD-SOI technology in both the 28nm and 20nm nodes. The SOI substrates are supplied by Soitec.

As part of its technology offerings, GlobalFoundries plans to offer two versions of FD-SOI: minimum and maximum. The maximum version is a technology tuned for a specific application. IBM and STMicroelectronics are examples of companies that would utilize maximum versions of FD-SOI. Meanwhile, the minimum version is a simple and an “out of the box” FD-SOI technology, said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries.

In addition, GlobalFoundries also plans to offer SSWR, a doping technology. “You add a ground plane below the channel,”  Kengeri said. The technology is a 20nm planar process at 28nm costs. For years, several companies have been working on the technology to solve a major issue. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node.

To solve RDF and other problems, one company, SuVolta, recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.

In the distant future, GlobalFoundries is also looking at 450mm. It is part of the recently-announced Global 450 Consortium. The G450C group includes five IC manufacturers, with IBM and GlobalFoundries joining the original “International Sematech” members, Intel, Samsung, and TSMC. Those companies, along with Sematech and the SUNY-Albany College of Nanoscale Science and Engineering (CNSE), will sit on the board of directors that will govern the consortium.

The G450C demonstration line in Albany is targeted for 14nm design rules in early 2013. “Do I want to be the first one (on 450mm)? No. Do I want to be the last? No. I would like to be behind the first,” Manocha added.

By Mark LaPedus
The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond.

Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography.

The sea of change likely will add to the burden on the foundries, which are already under stress as they continue to do more of the R&D and heavy lifting for their customers. At present there is debate about what changes will be needed for this extra load, as well as the looming inflection points on the process and transistor fronts. But the future seems clear in one respect—some changes will be needed.

Intel has taken a big lead in the process race and the foundries are struggling to keep up. In addition, the cost-per-transistor curve has been falling at about 29% per node to enable cheaper systems. At 28nm and 20nm, however, the curve is leveling off at the foundries.

“The fabless companies at the leading-edge, such as Nvidia and Qualcomm, are visibly concerned about their foundries’ ability to keep up with Moore’s Law,” said G. Dan Hutcheson, president of VLSI Research. “To stay in the game, they need a steady decline in cost-per-transistor. If (the curve levels off), this certainly puts into question the common wisdom that the fabless-foundry model is impenetrable.”

The pressure resides squarely on the leading-edge foundries, GlobalFoundries, Samsung, TSMC and UMC, to keep up and deliver. Outside of Intel, vendors face a challenging transition from today’s planar technology at 20nm to finFETs and other architectures at 14nm and beyond.

They also must select between various CMOS technologies to enable scaling. Foundries are leaning towards bulk technology for planar at 20nm and finFETs at 14nm. A rival camp has made a case for silicon-on-insulator (SOI) technology. On the transistor front, there is talk about a hybrid finFET/planar approach. SuVolta has a new planar transistor option. And 3D stacked devices provide yet another avenue.

It’s unclear which technologies will emerge as the winners or losers. What is clear is that only companies with deep pockets can afford to participate. At 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million, according to GlobalFoundries. And it will cost a staggering $32 billion in total process and tool R&D alone to develop 450mm fabs, according to VLSI Research.

Nonetheless, the fabless-foundry model appears to be far from broken, and predictions about the death of foundries seems greatly exaggerated. The pure-play foundry market is projected to reach $29.6 billion in 2012, up 12% from 2011, according to IHS. This business will grow by 14% in 2013, with double-digit growth continuing in 2014 and 2015, they said.

20nm challenges
Still, the 20nm node represents a pivotal juncture. Intel has made the shift from conventional planar transistors at 32nm to 3D finFETs at 22nm. For foundries, 20nm represents the last node in the planar era, because planar is beginning to suffer from undesirable short-channel effects.

And previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process. “As we move to 20nm, the fundamental differentiation between high-performance and low-power processes is going away,” explained Mojy Chian, senior vice president of design enablement at GlobalFoundries.

This move, coupled by delays in past nodes, prompted some industry pundits to imply that the fabless-foundry model is somehow broken. Chian dismissed the notion, saying the “fabless-foundry business is thriving.”

So what will keep the fabless-foundry model viable? There must be more collaboration and a new mindset, in which the foundries must change from being mere manufacturing partners into virtual IDMs, Chian said. “New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market,” he said.

Vendors must also make some tough choices. On the CMOS front, for example, the foundries will generally move to conventional bulk silicon at 20nm, due to cost. GlobalFoundries is in the bulk camp, but it will also make select chips for IBM and STMicroelectronics using fully depleted SOI (FD-SOI) at 28nm and 20nm.

Regarding SOI, Soitec is offering another CMOS technology option. It provides SOI for planar (FD-2D) and finFET (FD-3D) devices. FD-2D has 241 process steps, compared to 328 for bulk, according to Soitec. SOI wafers are more expensive, but IC makers can offset the costs with fewer process steps, more performance and less power, said Steve Longoria, senior vice president of strategic business development at Soitec.

Jeff Lewis, senior vice president of marketing and business development at SuVolta, said the industry needs a new solution besides bulk and SOI at 20nm. “The cost-per-transistor is higher at 28nm than 40nm/45nm,” Lewis said. “The problems get worse for the 20nm node due to double patterning.”

Another problem is transistor threshold voltage variation, which is caused by systematic and random variations, he said. A phenomenon called random dopant fluctuation (RDF) causes more than 70% of all random variations at 65nm and the problems are getting worse at each node. “In scaling, you start to get mismatches from one transistor to another,” Lewis said. “So the threshold voltages start to vary.”

To solve RDF and other problems, SuVolta recently rolled out a new transistor option that extends conventional bulk CMOS technology. SuVolta’s Deeply Depleted Channel (DDC) technology works by forming a deeply depleted channel when a voltage is applied to the gate.

Beyond 20nm
The problems continue to mount beyond 20nm. It’s unclear if EUV will be ready for the 14nm node. So, IC makers must contend with costly multi-pattering schemes. On the transistor front, Intel has made the migration to finFETs, but its technology has been a hot topic of discussion. Some “have painted Intel as being in trouble with tri-gate because images from a tear-down showed the fin was not squared off, but more shaped like a half-oval,” VLSI’s Hutcheson said.

Others have shown more vertical fins. “It’s very doubtful that Intel is in trouble,” Hutcheson said. “To get a squared off shape would be easy, but it adds steps, hurts yields, and dramatically increases cost.”

Intel may have made some tradeoffs to solve one bulk finFET challenge: height variation. In finFET production, there is an etch step, followed by a back-fill oxide process, and then an implant for junction isolation. The hard part is to make fins with consistent heights during the etch process.

Because of height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. In response, one foundry claims to have overcome some of these obstacles. According to a paper at the recent IEDM, GlobalFoundries implemented a dual shallow trench isolation (STI) process to ensure fin height control. Its high-k/metal-gate scheme also helped construct “tall/narrow” fins with less doping for better RDF, according to the paper.

FinFETs provide a 40% improvement in power reduction, but the technology still doesn’t put the cost-per-transistor back on the 29% reduction curve. “You are getting a significant power advantage,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “It’s still a challenge to translate that to a die cost reduction.”

All told, the industry should take a harder look at SOI, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. “FD-SOI is a fairly simple process, but there is a cost penalty,” Patton said. “When you get to finFETs, it’s a different story. The cost issue becomes neutral between bulk and SOI. Variability is also an advantage for SOI for finFETs.”

In the SOI model, “you place your order to the substrate supplier,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that promotes SOI. “The height of the fin is pre-determined. It’s pre-made for you.”

Fin variability in bulk finFETs is about 140% to 170% higher, versus SOI finFETs, according to the SOI Consortium. In the front-end-of-the-line (FEOL) process alone, SOI finFETs have 56 process steps, compared to 91 for bulk finFETs, the group said. In total, the FEOL cost for SOI finFETs is $561, compared to $805 for bulk, they said.

Still, GlobalFoundries, TSMC and Samsung are banking on bulk finFETs at 14nm for two reasons. First, it’s unclear if the SOI wafer suppliers can meet demand during crunch times, said GlobalFoundries’ Kengeri. “Historically, customers are not used to designing in SOI. They are comfortable designing with bulk,” he said.

What’s next?
Beside traditional finFETs, there is also talk about a hybrid approach. In this concept, chip makers would combine finFETs and planar devices on the same chip. The planar devices could include analog IP. “This is not easy to do,” Kengeri said. “It’s a complicated process.”

A more likely scenario is that current finFET technology would be scaled at least two generations to 10nm, he said. Then, at 7nm or before, the industry is looking at various next-generation finFETs to solve the mobility problems. The candidates include quantum well finFETs, PMOS germanium finFETs, and SOI. “From a research point of view, we’re looking at everything, but nothing is settled,” Kengeri said.

By Mark LaPedus

The technology roadmap for semiconductors remains in flux, as there are more signs that the foundries may accelerate the insertion point for finFET transistors amid next-generation lithography delays.

Even before finFETs, there are also questions about the 20nm node at the foundries. And at a recent event, various factions debated over which technology will enable future designs. In general, the two main technology candidates are based on bulk CMOS and silicon-on-insulator (SOI). Startup SuVolta Inc. has developed another option. And 2.5D/3D stacked technology provides yet another scaling path.

Causing part of the confusion in the semiconductor roadmap is the exact timing for the insertion point of extreme ultraviolet (EUV) lithography. Right now, the foundries plan to use 193nm immersion lithography and double-patterning to enable planar devices at 20nm.

If EUV is ready, the foundries hope to move into finFET production at 14nm. But if EUV is late at 14nm, the foundries will use triple-patterning at that node, said Shang-yi Chiang, executive vice president and co-chief operating officer at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), at the company’s recent technology symposium.

Another option is to accelerate the insertion point for finFETs, which could be introduced at a new half-node — perhaps 18nm or 16nm, he said. This would be done with 193nm immersion and perhaps double-patterning. Asked if TSMC has changed its current finFET roadmap for the 14nm node, Chaing told SemiMD: “Not at this moment.”

At a separate event, Joël Hartmann, corporate vice president of front-end manufacturing and process R&D at STMicroelectronics Inc., put it more bluntly. “At 14nm, we want EUV,” Hartmann said during a presentation at last week’s GSA Silicon Summit in Mountain View, Calif. “The industry absolutely needs EUV. The problem is that EUV is late.”

If EUV remains late at 14nm, Hartmann also proposed the idea of pulling in the roadmap and rolling out finFETs at the 16nm half-node. Nvidia, Qualcomm and others are also nudging their foundry partners to accelerate their respective finFET production schedules.

Much of this largely depends upon ASML Holding NV’s ability to ship EUV. Last week, ASML disclosed its initial production EUV tool – the NXE:3300B – will ship by year’s end, as promised. The main problem still centers around the EUV light source. The main source vendor, Cymer Inc., claims to have demonstrated 30 Watts of power at a high duty cycle. Cymer also demonstrated 50 Watts of raw power, applying pre-pulse technology. But to achieve acceptable throughputs of 60 and 125 wafers an hour, the power source must hit 100 Watts and 250 Watts, respectively.

20nm questions

While EUV remains a question mark, there is also some debate regarding the technology roadmap for semiconductors. First, there are some major questions surrounding the 20nm node in general. As reported, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) recently said it plans to combine technologies and offer one process at the 20nm node.

“The argument is that the R&D requirements to do (multiple process) variants is just too great to pull off for 20nm,” said G. Dan Hutcheson, president of VLSI Research Inc. “Another argument is that variability is so high that it swamps the electrical distinctions between” the various variants.

”Given (the advent of) multi-core architecture, it makes sense that designers would want to use both high-performance and low-power processes with different transistors for different cores on the same chip,” Hutcheson said. “There have always been different transistors on the same chip anyway, just not on this scale. Hence, there would only be a need for a single process, but with multiple modules to address (various process) needs.”

He added: ”You still have the same variability problem, but having a version makes it easier to manage on the fab line as well as in the end market. Designers would love this and designers always get what they want. Thus, I would argue that a single process strategy at 20nm is not only a trend, but the new normal.”

On the transistor front, meanwhile, Intel Corp. has moved into production with bulk-based finFETs at 22nm, with plans to extend that technology down to future nodes. Outside of Intel, the two options for the 28nm and 20nm nodes include bulk planar transistors and fully-depleted silicon-on-insulator (FD-SOI). At 14nm, planar transistors are expected to run out of steam, requiring either bulk finFETs or SOI-based finFETs. SuVolta has proposed another technology.

Bulk vs. SOI vs. SuVolta

The three basic camps — bulk, SOI and SuVolta — each claim they have a superior solution. But all camps agree on one premise. “Clearly, the end-user doesn’t want” less performance, said Paul Boudre, chief operating officer at SOI wafer specialist Soitec, during a panel discussion at the GSA event. “The end-user wants more.”

Regarding the direction of transistor technology, Boudre said: “Bulk is running out of gas at 20nm.” For decades, CMOS circuitry has been implemented on standard bulk silicon wafers. The advantage of bulk CMOS is cost, flexibility and scalability, but the SOI camp has a different viewpoint.

At the GSA panel, Matt Crowley, vice president of hardware at FPGA startup Tabula Inc., represented the bulk camp. Recently, Tabula made headlines, when the startup struck a foundry alliance with Intel. Intel will make Tabula’s FPGAs based on its 22nm tri-gate and bulk process.

In Intel’s tri-gate structure, the traditional “flat” two-dimensional planar gate is replaced with a thin 3D silicon fin that rises up vertically from the silicon substrate. Intel claims that its tri-gate transistor provide up to 37 percent performance increase at low voltage versus Intel’s 32nm planar transistors.

Crowley said Tabula is bullish about Intel’s tri-gate technology, because it provides lower power for FGPAs. “The finFET enables traditional scaling,” he told SemiMD. “The finFET is compatible with our CAD infrastructure.”

The rival SOI camp both agreed and disagreed. The SOI camp agreed that the world is moving towards fully-depleted finFETs, but disagreed that bulk is the way to go. “SOI is vastly superior” over bulk for finFETs, said Subramanian Iyer, IBM Fellow and chief technologist at IBM Corp.’s Microelectronics Division, during a presentation at the GSA event.

Iyer said bulk-based finFETs are susceptible to junction leakage and “fin height variability.” For finFETs in general, there is a perception that it is difficult to control the widths and heights of the fins in the manufacturing process.

IBM, one of the champions for SOI in the market, will move to finFETs on SOI wafers at the 14nm node. However, the Fishkill Alliance of companies, including Samsung, GlobalFoundries, Toshiba, and others, will pursue bulk finFETs at the 14nm node.

For years, AMD, IBM, and Freescale have been among the largest-volume users of SOI wafers. SOI wafers command a price premium over bulk, but Soitec has argued that by using the buried oxide layer, the number of process steps can be sharply reduced, with about 90 fewer total steps. Shallow trench isolation steps can be largely eliminated, for example.

Propelling the technology for future designs, Soitec recently said it is ready to provide SOI wafers to both planar (FD-2D) and finFET (FD-3D) customers. STMicroelectronics recently announced they will pursue fully-depleted SOI (FD-SOI) for 28nm application processors.

Planar FD-SOI technology relies on an ultra-thin layer of silicon over a buried oxide. Compared to bulk, FD-SOI has 10 percent fewer process steps and the wafer costs are roughly equal, ST’s Hartmann insisted. STMicroelectronics also plans to use FD-SOI at the 20nm node, he said.

Meanwhile, SuVolta presents another option. SuVolta’s so-called Deeply Depleted Channel (DDC) transistor technology is said to leverage existing CMOS design rules and process flows, and can be manufactured in existing fabs because it does not require new equipment or new materials.

During the GSA panel, Pushkar Ranade, senior director of process integration at SuVolta, also floated an idea that emerges from time to time: Let’s slow down the two-year process technology cycle in order to get a return-on-investment. “Is a two-year cadence the right cadence? Maybe a four-year — or five-year — cadence makes sense,” he said. “The industry could have a longer cadence, but improve the feature” sets of each technology node.

For example, the current versions of Apple Inc.’s successful iPad are based on a 45nm application processor – at a time when the industry is hyping 14nm, he added.

At one time, venture capital money was plentiful in the semiconductor industry, thereby fueling a wave of new and innovative startups.

But more recently, venture capital has dried up in the semiconductor arena. Venture capitalists have shifted their focus away from semiconductors and moved towards industries with less risk and potentially enormous returns. Green technology and social media come to mind.

The risks are too high to fund many chip startups today. IC design costs are soaring out of control and it’s sometimes difficult to find new markets.

The data is gloomy. The Global Semiconductor Alliance (GSA) shows VC funding for the industry-such as IP, EDA/design, foundry, test and packaging-at $717.5 million in 2007 compared to $272.2 million in 2010, with 2011 tracking at roughly half the rate of last year.

Still, there is room for some new and innovative startups. SuVolta Inc., a developer of low-power IC technology that cuts chip power consumption by 50 to 90 percent, has secured $17.6 million in venture funding.

The company will use the funding to continue to develop its low-power silicon technologies. New investor Bright Capital participated in the round, joining all existing SuVolta investors including Kleiner Perkins Caufield & Byers (KPCB), August Capital, New Enterprise Associates (NEA), Northgate Capital, DAG Ventures and others.

“While the past five years have produced impressive innovations with the web and mobile devices, it’s just as important that we continue advancing the underlying technologies that make these innovations possible,” said Forest Baskett, general partner at NEA.

“Unfortunately, the funding for core semiconductor technology has significantly declined over the same period. Funding a venture like SuVolta is important because we need companies striving to truly disrupt the status quo in the semiconductor industry,” he said.

“Power is now the biggest design constraint for electronic products,” said Bruce McWilliams, president and CEO of SuVolta. “Lowering power consumption has far reaching benefits for a range of applications and products including mobile devices. SuVolta is pleased to be advancing the possibilities from continued scaling of planar, bulk CMOS technology.”

At the International Electron Devices Meeting (IEDM) last month in Washington D.C., SuVolta along with its development partner and licensee, Fujitsu, demonstrated power consumption reduction with the ultra-low-voltage operation of SRAM (static random access memory) blocks down to 0.425V.

By David Lammers

SuVolta Inc. (Los Gatos, Calif.) and Fujitsu’s semiconductor operation presented a joint paper at IEDM 2011 in Washington, D.C. Wednesday (Dec. 7) showing good SRAM performance below 0.5V Vdd, which they said validates SuVolta’s claims of low-power operation in a bulk silicon, planar CMOS technology.

Fujitsu, which took an early license to SuVolta’s Deeply Depleted Channel (DDC) transistor technology, plans to introduce products next year which enhance ICs made on trailing-edge design rules with the SuVolta approach. At IEDM, Fujitsu presented reliability data for a 576-Kb SRAM which operates at 0.425V, with half the expected variation in the threshold voltage (Vt).

SuVolta now has about 50 employees, with a core group of executives from Intel, AMD, and others. ARM and Broadcom are among the fabless companies which have expressed interest in the technology. The initial licensee, Fujitsu, is providing Spice models to its foundry customers, and is working on second-generation products which use revised IP that takes advantage of the DDC technology.

Two large foundries are evaluating the SuVolta technology with silicon wafer shuttles, and a third is in discussions now, said Jeff Lewis, director of business development. “Some customers are evaluating, and some are beyond that. There is huge inertia in this industry, and the foundries want to run a bunch of wafers to make sure the technology works, before they commit. We believe our technology is solid and that it is going to win in the marketplace,” Lewis added.

“We are more engaged with the foundries since last April, when we announced our licensing partnership with Fujitsu. We are working with multiple places on 28nm technology,” Lewis said.

SuVolta positions itself as a low-power, low-cost way to achieve performance improvements, avoiding the manufacturing complexity of finFETs while staying on the lower-cost bulk silicon wafers. Design porting can be minimal as well.

Scott Thompson, the former 90nm program manager at Intel, is a co-founder and CTO. He said the industry will see a pushback next year on finFETs, as it becomes clear that the vertical transistors are difficult to manufacture for SoCs. Intel senior fellow Mark Bohr, in an IEDM keynote address on Monday, said that Intel will begin shipping Ivy Bridge-architecture MPUs to customers “in the first half of next year” and is early production now with its tri-gate transistor. That places Intel about 5-6 months behind its normal two-year cycle, said participants at IEDM, who speculated Intel is working out production challenges.

Low power operation and costs have become more important that sheer performance in the mobile systems, the SuVolta executives said, noting that Amazon’s Kindle Fire has an applications processor priced at just $7 and the Apple iPhone SoC is in the $20 range. While the Intel processors have a power budget in the 50-70W range, mobile processors must draw about 1W, over a wide range of voltages.

“We only modify about 5 percent of the CMOS flow, require no new tools, and yet our Vt control matching with a relatively simple change of recipe is what sets us apart,” Thompson said.  That control supports better binning, he added, allowing customers to make more money from a higher percentage of good-performing SoCs. “Applications that nominally run at 0.7 or 0.8V can be dynamically scaled back to 0.6V when power savings can be had, and then return to running at 0.7 or 0.8V when a heavier work load is presented,” he said.

The DDC channel has several regions – an undoped or very lightly doped region, a Vt setting offset region, and a screening region. The undoped or very lightly doped region removes dopants from the channel which allows for a deeply depleted channel. This reduces random dopant fluctuation (RDF), enables Vdd scaling and improves mobility, boosting the effective drive current.

The Vt setting offset region sets the transistor threshold voltage levels, without degrading channel mobility. This region also improves sigma Vt over conventional transistors, the company said. The screening region screens the charge, sets the depletion layer depth, and serves as a body for dynamic Vt adjustment through optional biasing techniques. The increased body coefficient supports improved Vt control.

The DDC transistor controls Vt variation, which supports a 30 percent lower operating voltage, lower leakage, and less design guard banding. The DDC transistor supports multiple VTs, vital for today’s low-power products, the company said.

A video describing the SuVolta technology can be seen here.

By David Lammers

Throwing in its hat as a third path to scaling alongside finFETs and fully depleted SOI, SuVolta Inc. claims it has developed transistor processing techniques which support significant improvements in both active and leakage power, and on a planar bulk CMOS platform.

Scott Thompson

The startup has attracted a team of highly regarded former Intel and AMD technologists, including chief technology officer Scott Thompson, who spent a dozen years at Intel. Several well-known venture capitalists, notably Forrest Baskett, Bill Joy, and Andy Rappaport, are among the financial backers.

Fujitsu Semiconductor is an initial licensee, with early plans to quickly improve the power consumption of several 65nm designs by applying the SuVolta technology.

SuVolta rolled out its technology Monday (June 6) with supportive comments from several companies, including ARM, Broadcom, and Cypress Semiconductor. Several technology analysts said they are taking seriously SuVolta’s claim that it offers an alternative to finFETs and fully depleted SOI, the two presumed successors to partially depleted planar bulk CMOS technology at advanced technology nodes.

Thompson said SuVolta’s “PowerShrink” platform involves carefully controlling the dopants in the areas just below the inversion region to create what SuVolta is calling a “Deeply Depleted Channel” or DDC. He said the largely undoped channel allows the inversion charge to move from source to drain without scattering from dopant atoms, which kill mobility, particularly at reduced Vdd’s.

SuVolta claims better control of threshold voltage variation.

The company claims its approach also allows for extremely tight control of the threshold voltage. For high performance SoCs, tight threshold voltage is required to avoid variation in the gate overdrive, which leads to performance variation, he said.

The Deeply Depleted Channel transistor is manufactured with “near atomic layer dopant control, without the need for an ALD tool,” Thompson said.  The near atomic layer dopant control allows the depletion layer to be controlled far more precisely than in a conventional MOSFET, or in a spacer-defined or lithography defined finFET.  “A well-controlled depletion layer width allows for the nominal depletion depth to be deeper than in a conventional MOSFET which in turn allows simultaneously for an undoped channel layer and improved threshold voltage setting,  both of which are key for low-power operation,” Thompson said.

Asked if thinness of the channel was key to the SuVolta approach, Thompson said with the deeply depleted technology “there is much less variation in the depletion layer compared with a conventional device. They key part of this is controlling the depth of the depletion layer. That is what gives us the good sigma Vt (variability) that we see with the 65nm devices today.”

SuVolta is aiming at what is now the dominant growth engine for the semiconductor industry: low-voltage SoCs for mobile devices, said Bruce McWilliams, SuVolta’s CEO, who earlier worked for Tessera Inc., another company which relies on a licensing model for its revenues.

McWilliams said SuVolta’s initial mobile SoC customers can achieve half the power at the same performance, with no changes to the mask set, no new tooling, and no change in their IP cores.

The company also has an engineering team in place which is developing the basic libraries and core IP that will deliver additional power savings for companies using the SuVolta technology from scratch. The engineering team has taped out test circuits and is running foundry shuttles now, sharing the results with potential customers.

“We have 28nm I_on/I_off data.  It matches our expectations for higher mobility from the undoped DDC channel. And the mobility advantage increases at the lower power supply voltages,” Thompson said in an e-mail exchange.

For higher-performance SoCs which need low-power operation, SuVolta’s technology will take advantage of the body coefficient, which supports a fourth terminal in planar CMOS. Planar bulk CMOS platforms, Thompson said, “allow more flexibility in designs by enabling power modes to leverage a wide range of threshold voltages and dynamic  threshold voltages, using body bias techniques which are used now for SOCs in general. These techniques are especially important for high-performance SOC operation with low-power supply voltage modes of ~ 0.5 to 0.7V, resulting in active power modes in the ~ 100 mW range.”

McWilliams said Transmeta used a similar technique to lower the power consumption of its x86 core, while the StrongARM processor also employed the body coefficient to raise or lower the voltage. “It is an old technique, but we came up with a structure to greatly boost that, to dramatically cut leakage or boost performance,” McWilliams said, adding that the biasing approach will become critical at 0.5V operation.

Thompson said the first products employing the SuVolta technology will not use biasing. As companies move to more aggressive low-power modes they will adopt reverse biasing to gain “another factor of ten reduction in leakage.”

SRAM at 0.42V

SuVolta presented some data on a test SRAM, manufactured by Fujitsu, showing the minimum (0.42V) operating voltage, leakage, and local threshold voltage matching (AVT/sigma VT).

SuVolta claims a potential 300 mV reduction in SRAM Vdd.

The SRAM supports read/write operation down to 0.42V, without circuit, layout, or mask changes, Thompson said. Normal operation would be at 0.7-0.8V, which compares with about 1V-1.1V for most 65nm technologies.“This represents a greater than 300mV improvement in supply voltage scaling compared to a typical foundry technology.  The tight threshold voltage control leads to five times lower leakage power,” Thompson said.

“With our 65nm device targets, we show a 2X improvement in Vt variability, both globally and locally. We believe we can do even better at future nodes. The improvement gets larger at lower voltages, which is helpful for SRAM cell stability,” Thompson said. SuVolta has device data down to the 25nm range. Modeling, Thompson said, “gives us confidence that we can take this approach all the way down to 14nm with good mobility, leakage, and threshold matching.”

The SuVolta CTO said the most difficult-to-control source of threshold voltage variation is local mismatch, which is driven by random dopant fluctuations. Since traditional fabrication techniques do not control the location and number of dopants at the atomic level, Thompson said the number and position of the dopants vary device-to-device. SuVolta is claiming that local threshold voltage control is “as good as the best FD-SOI research devices,” he said.

SuVolta’s claims might engender acute skepticism were it not for the pedigree of the team. McWilliams said he and Thompson came to the startup two years ago, and Thompson came up with a completely different approach to achieving the low-power goals using planar CMOS. After leaving Intel, Thompson worked as a professor at the University of Florida, but is now on leave from the university and is spending all of his time at SuVolta.

Two other top engineers from Intel have joined SuVolta. Lucian Shifren, director of device and modeling, was a lead device engineer at Intel for many years, doing much of the TCAD modeling for Intel’s FinFET technology. Pushkar Ranade, director of process integration, was a lead integrator of Intel’s 45nm and 22 nm technologies, taking those technologies from early pathfinding and development to high-volume manufacturing.

Nick Kepler, who earlier held senior technology management positions at AMD, left GlobalFoundries to manage SuVolta’s product development team. Thomas Hoffman, another well-connected ex-Intel technologist who spent several years as a director at Imec, also recently joined SuVolta.

McWilliams said the chip industry will stick with planar CMOS as long as possible. “We can reuse the existing IP, which we think is key to adoption. People don’t want to go back and redo their libraries.”

Jeff Lewis, senior vice president of business development, said SuVolta is in discussions with foundries. Besides the announced relationship with Fujitsu, Lewis said “we are working with quite a few companies, at both advanced and older nodes. 65 nanometers is a perfect place for us to start, especially for companies looking for a mid-life kicker where they immediately have high volumes. But certainly we are working with the major companies at 28 and 40 nanometers.”

McWilliams added that he believes Fujitsu, which also serves as a foundry, will have a SuVolta-enhanced product “on the market in the next year, along with their customers.”

SuVolta had an unusual rollout for a startup, including supporting statements from companies which normally hold their cards relatively close to their vests.

For example, Pieter Vorenkamp, Broadcom’s senior vice president of engineering and operations, went on the record as saying that “SuVolta’s low-power platform could have a dramatic impact on the industry. The substantial device matching improvement of core and IO devices, enhanced body effect and perceived ‘simple’ integration with a digital CMOS manufacturing could have a dramatic impact on reducing power and cost of highly-integrated SoCs.”

Krisztian Flautner, the vice president research & development at ARM, said, “ARM continues to monitor new technologies that may yield significant power or cost reduction in advanced SoC designs. The aim is to avoid excessive upgrade costs in new fabrication facilities or circuit design. SuVolta’s platform offers a promising approach to extending the scaling of CMOS transistor technology.”

T.J. Rodgers, the founder of Cypress Semiconductor, also issued a statement in support of SuVolta.

SuVolta will compete with finFETs and FD-SOI technologies.