Posts Tagged ‘STMicroelectronics’
Peregrine Semiconductor Corp. and GLOBALFOUNDRIES are sampling the first RF Switches built on Peregrine’s new UltraCMOS 10 RF SOI technologies. This partnership unites Peregrine’s 25 years of RF SOI experience with a tier-one foundry. In a joint development effort, GLOBALFOUNDRIES and Peregrine created a unique fabrication flow for the versatile, new, 130 nm UltraCMOS 10 technology platform. This new technology delivers a more than 50-percent performance improvement over comparable solutions. UltraCMOS 10 technology gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.
Peregrine Semiconductor this week celebrated two significant milestones – its 25th anniversary of pioneering RF SOI solutions and the shipment of the two-billionth chip. Peregrine reaches the two-billionth-chip milestone in an order to Murata Manufacturing Company, the supplier of RF front-end modules for the global mobile wireless marketplace.
Rubicon Technology announced the launch of the first commercial line of large diameter patterned sapphire substrates (PSS) in four-inch through eight-inch diameters. This new product line provides LED chip manufacturers with a ready-made source of large diameter PSS to serve the needs of the rapidly growing LED general lighting industry.
Semiconductor Research Corporation and Northeastern University researchers announced advancements in radio-frequency (RF) circuit technology that promise to improve and widen the applications of mobile devices.
Imec announced that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon.
STMicroelectronics announced this week its close collaboration with Memoir Systems has made the revolutionary Algorithmic Memory Technology available for embedded memories in application-specific integrated circuits (ASICs) and Systems on Chips (SoCs) manufactured in ST’s fully-depleted silicon-on-insulator (FD-SOI) process technology.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.