By Mark LaPedus
Apple apparently is switching foundry vendors from Samsung to TSMC. Still, Samsung is moving forward with its U.S. fab plans. The company announced that a $4 billion fab investment at its Austin, Texas, site is on schedule for production of mobile application processors within the second half of 2013. The remodeled fab line will produce mobile application processors on 300mm wafers at the 28nm node. C.J. Muse, an analyst with Barclays, said Samsung will cut its capex by 50% in 2012 over 2011. “The actual range is likely to be down 30%-50% year-over-year, with a bigger cut on the logic side (due to the likely loss of the Apple business) and a more muted cut on the memory side.”

In a decision that will support nearly 10,000 high-tech jobs, the Export-Import Bank of the United States (Ex-Im Bank) has approved a $1.03 billion loan to GlobalFoundries to finance the export of American-made semiconductor manufacturing equipment to Germany. Applied Materials is one of the exporters involved in the transaction. “The ability of our customer GlobalFoundries to access this financing benefits Applied Materials’ manufacturing and R&D in the United States, as well as our supply chain, at a time of tremendous global competition for high-tech jobs,” said Mike Splinter, chairman and CEO of Applied, in a statement.

GlobalFoundries has added a 10nm finFET process to its roadmap and expanded its technology platform offerings. The foundry vendor plans to go from 20nm planar in 2013, to 14nm finFET in 2014, to 10nm finFET in 2015, and 7nm finFET in 2017.

At the SOI Consortium’s event at IEDM, Jeff Watt, a fellow at Altera, presented an evaluation and benchmark of planar fully depleted SOI technology. A simulation showed that 20nm FD-SOI provided a 5X reduction in power over 28nm bulk, Watt said. However, Altera has not made a commitment to SOI for FPGAs and is currently evaluating the technology, he said. “We are looking at all options,” he said. For 20nm, Altera plans to use a bulk technology at TSMC. At 14nm, the FPGA house will likely go with bulk finFETs at TSMC. However, Altera is also exploring SOI.

STMicroelectronics unveiled the results of its 28nm production silicon chips using FD-SOI technology, which it claims offers a 30% improvement in speed over bulk CMOS while using less power.

STMicroelectronics took another step towards the availability of its 28nm FD-SOI technology platform. The technology is now open for pre-production from its Crolles 300mm manufacturing facility.

SEMI praised Congressional leadership as the U.S. Senate passed legislation (92-4 vote) to normalize trade relations with Russia. This allows American companies to receive the full benefits of Russia’s recent accession to the World Trade Organization (WTO) by wavering an outdated, Cold War-era amendment that restricted trade.

SEMI reported that worldwide semiconductor manufacturing equipment billings reached $9.06 billion in the third quarter of 2012. The billings figure is 12% lower than the second quarter of 2012 and 15% lower than the same quarter a year ago.

Mentor Graphics announced the new T3Ster DynTIM tester, a method of measuring thermal characteristics of thermal interface materials.

MIPS determined that a new proposal from CEVA to acquire the company constitutes a “superior proposal” to the merger agreement with Imagination Technologies. MIPS is prepared to continue negotiations with Imagination if it adjusts the terms of the merger agreement.

Rudolph Technologies has acquired Azores. The move will enable Rudolph to enter the back-end advanced packaging lithography market.

Test handler specialist Cohu has agreed to acquire Ismeca Semiconductor from Schweiter Technologies for $54.5 million, plus acquired cash, to be funded out of Cohu’s existing cash reserves.

Worldwide semiconductor revenue is projected to total $311 billion in 2013, a 4.5 percent increase from 2012 revenue, according to Gartner.

The solar industry is reeling from overcapacity and supply outstrips demand by two to one. It needs to drive costs lower in order to overcome diminished subsidies and regain profitability, according to Lux Research. Module prices have fallen precipitously over the past four years to a low of $0.70/W but the cost of goods sold (COGS) for modules has not reached this level, resulting in massive losses for most module manufacturers. Solar modules production costs could fall as low as $0.48/W in 2017, according to the firm.

By Ed Sperling
STMicroelectronics yesterday unveiled the results of its 28nm production silicon chips using fully depleted silicon on insulator technology, which it claims offers a 30% improvement in speed over bulk CMOS while using less power.

The debate over FD-SOI and FinFETs has been notching up over the past few months. While FinFETs and FD-SOI both promise improvements in controlling leakage current, the FinFETs are more difficult to design. FD-SOI uses the same design flow, although it does use a different SPICE model with better characteristics than the one used for bulk CMOS.

ST also used an ultra thin body and box (UTBB) and body biasing to boost performance, according to Joel Hartmann, the company’s executive vice president of front-end manufacturing and process R&D. Hartmann presented his results at an SOI Consortium-sponsored event at the IEDM show last night.

“We are using body bias to boost performance,” Hartmann said. “You can do that with FD-SOI. We also decreased the Vdd of the device by applying body biasing.”

What’s particularly attractive about FD-SOI is that is can be implemented at the 28nm node for a boost in performance and a reduction in power. The mainstream process node right now is 40nm. And while Intel introduced its version of a finFET transistor called Tri-Gate at 22nm, TSMC and GlobalFoundries plan to introduce it at the next node—whether that’s 16nm or 14nm. That leaves companies facing a big decision about whether to move all the way to 16/14nm to reap the lower leakage of finFETs, whether to move to 20nm on bulk, or whether to stay longer at 28nm with FD-SOI.

Hartmann said ST has seen improvements in analog running on FD-SOI, and for memory where the minimum voltage required is lower. He said ST’s road map calls for FD-SOI all the way down to 10nm, with voltages dropping from 0.9v at 28nm to 0.8v at 14nm and 0.7v at 10nm.

One of the sticking points in adopting FD-SOI has been market acceptance. Despite the promise of improved performance and/or lower power, bulk CMOS has been extended using a variety of techniques such as strain engineering and FD-SOI is considered more expensive. At 28nm and beyond, however, bulk has run out of steam, which is why Intel has opted for finFETs.

Still, FinFETs are more difficult to design and manufacture, and they potentially can add significantly to the cost of an SoC. FD-SOI, in contrast, uses the same design tools and reduces the number of masks and metal layers. ST is the first large fab-lite company to adopt FD-SOI and to move beyond just test chips. It remains to be seen which path the rest of the industry takes—and how quickly.

By Mark LaPedus
Get ready for the 2012 IEEE International Electron Devices Meeting (IEDM) in San Francisco. At the event, slated for today through Wednesday, GlobalFoundries CEO Ajit Manocha will give a keynote, entitled: “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!”

Here are some of the papers and events at the IEDM event:

*A team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device. Researchers have integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm.

*IBM will describe a fully-integrated SOI SRAM at 22nm.

*In a separate paper, CEA-LETI, STMicroelectronics, IBM, GlobalFoundries and Renesas will discuss FD-SOI for the 20nm node and beyond.

*STMicroelectronics will describe the performance of ultra-thin box and body technology. The SOI technology will provide a total power reduction of 30% to 40% at identical speed with respect to bulk thanks to back side gate biasing efficiency.

*National Chiao Tung University will discuss a high-performance Ge CMOS finFETs on a thin SOI wafer.

*Imec, GlobalFoundries and Samsung will talk about stress enhanced mobility for n- and p-FinFETs with both Si and Ge channels for the 14nm node and beyond.

*Applied Materials and Synopsys will present a paper entitled, “Is strain engineering scalable in FinFET era?”

*SuVolta, a developer of low-power CMOS technologies, announced the results that demonstrate the performance and power advantages of its Deeply Depleted Channel (DDC) technology.

*The SOI Industry Consortium has organized a symposium that will address the world of fully depleted SOI. The symposium will be held at the San Francisco Hilton Hotel today, concurrent with the IEDM 2012 Conference.

*The 14nm node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. Tomorrow, Applied Materials will host a forum in San Francisco to explore the subject.

Intel’s push in the foundry business has the industry talking. Can the chip giant give the traditional foundries a run for their money? Some say no. In a report, Hans Mosesmann, an analyst with Raymond James, said: “The chatter that Intel should become a foundry for Apple/Qualcomm as a positive for the company is amusing to us given that foundries are the low-end of the semiconductor manufacturing totem-pole. Does it make sense for Intel to build $10 billion shiny new fabs for foundry work? We think not for 45-50% gross margins, and ask IBM how the foundry investment turned out. Intel’s fabs are not meant for the fragmented nature of foundries and truth be known, Intel is a laggard in SoC manufacturing anyway (at least today). Regardless, a formalized foundry strategy would be an acknowledgment by Intel that its model isn’t working and a negative for gross margins.”

Thanks to investments from Intel, Samsung and TSMC, ASML is developing a 450mm EUV scanner. But EUV remains delayed. So the industry is hedging its bets. In an announcement at Semicon Japan, Kazuo Ushida, president of Nikon, said that the company plans to ship 450mm, 193nm lithography tools in 2017 through a joint development effort with Intel. Nikon plans to have 450mm-enabled ArF immersion prototype tools in 2015-16.

In a video on SEMI’s site, Paul Farrar, general manager of the Global 450mm Consortium (G450C), discussed the progress and impact of the G450C.

AMD has amended its wafer supply agreement with GlobalFoundries. As part of the plan, AMD will reduce its procurement of wafers from GlobalFoundries.

International Rectifier introduced a series of high-current, ultra-low dropout hybrid linear voltage regulators based on SOI.

A team of ST and CEA-LETI received the 2012 Général Ferrié Award. They were honored for their work on FD-SOI technology.

ST has taken the decision to exit ST-Ericsson after a transition period and is currently in negotiations on exit options. This disengagement process has started, with the transition expected to end during the third quarter of 2013.  ST will continue to support ST-Ericsson as its supply-chain partner, advanced process-technology partner (FD-SOI) and application-processor IP provider.

Soitec will hold a grand opening celebration of its North American solar headquarters and manufacturing facility in San Diego on Dec. 19.

The Center for Science Teaching and Learning (CSTL) and Applied Materials announced a new clean tech competition challenge that addresses the global problem of access to clean water. The program, which now includes students from Singapore, as well as Xi’an, China, and California’s San Francisco Bay Area, was created last year to inspire the next generation of leaders and innovators in clean technology.

As a result of an equity investment, Qualcomm will become a minority shareholder in Sharp.

Axcelis will exit the dry-strip business to focus on the ion implanter market. Axcelis will sell its dry-strip business to Lam Research.

CyberOptics announced the completion of a restructuring and staff reduction totaling approximately 10% of its global workforce.

Signetics will double its capacity for flip chip package assembly within its factory in Paju, South Korea.

For most of the last two decades personal computers have accounted for a third or more of annual IC sales, but standard PCs are now on the brink of being replaced as the largest end-use product category for integrated circuits, according to IC Insights.

Amid weak economic conditions, IHS is downgrading its forecast for the global semiconductor market in 2012, with revenue now expected to decline by 2.3% for the year.

Sony next year is expected to purchase $8.4 billion worth of semiconductors, up nearly 5% from $8.0 billion in 2012, according to HIS. Meanwhile, Toshiba’s spending will increase 2.0% to $6.1 billion in 2013, up from $6.0 billion in 2012. In contrast, spending at the other major Japanese consumer electronics OEMs, Panasonic and Sharp, will decline in 2013 and 2014.

By Mark LaPedus
In October, Draper Laboratory and the University of South Florida (USF) disclosed an ambitious plan to develop a brain-on-a-chip.

The idea is to devise a “micro-environment’’ that mimics the human brain. Researchers hope to study neurodegenerative conditions such as Alzheimer’s disease, strokes and concussions. The eventual goal is to study the effects of drugs and vaccines on the brain.

Draper, a spinoff from the Massachusetts Institute of Technology (MIT), and USF are using embryonic cells from rats, but researchers plan to use human cells in the future. The brain-on-a-chip combines several technologies, including an emerging field called microfluidics.

Microfluidics deals with the control of fluids in devices. Tiny chip-like devices using microfluidics are used in many applications, such as cell sorting and detection, gene analysis, inkjet print heads, lab-on-a-chip units and point-of-care diagnostic tools. Meanwhile, lab-on-a-chip, and a related field, organ-on-a-chip (i.e. brain-on-a-chip), are systems that integrate various functions in a chip-like format. Some, but not all, lab-on-a-chip systems use microfluidics.

In these areas, OEMs and researchers use many of the same tools and processes borrowed from the semiconductor and MEMS industries. “The tools that are used to manufacture semiconductor devices can also be applied to make an organ-on-a-chip,” said Jeffrey Borenstein, distinguished member of the technical staff at Draper Labs. “The reason for that is you may need a lot of precision to structure these materials. The common tools are photolithography, etching, and other familiar processes in the semiconductor industry.”

Draper is not using leading-edge process technology, but it still faces some major challenges. “There is a need in the microfluidics field for process technologies that will enable things to be made at a higher volume and a lower cost,” said Borenstein, who is also the technical director for a separate project that is developing a human-on-a-chip. “There are some broader research goals in terms of understanding how organs work and understanding disease processes.”

Microfluidics emerges
Driven by the progress in the identification of genes and proteins, sales of microfluidic devices reached $1.3 billion in 2011, up 19% from 2010, according to Yole Développement. Yole also predicts that sales of fab-level microfluidics devices will average 23% annual growth through 2016, pushing the sector to almost $4 billion.

Microfluidics first emerged in the 1980s, but it has only recently begun to ramp up. The technology is being pursued by a plethora of device makers, OEMs and research entities. Affymetrix, Fluidigm, HP, IBM, Philips, Roche, Samsung, Siemens, Sony, STMicroelectronics are just a few of the names in the field.

In microfluidics, the products tend to be customized and the development cycles are long, but manufacturing costs are not an overriding issue. “A lot of people have set up fabrication capabilities for microfluidics that are relatively inexpensive,” said Draper’s Borenstein.

The tiny microfluidic devices themselves are generally comprised of complex pumps and external plumbing to transport a given fluid. The ability to pump the fluids at the micro-scale level is just one of the challenges. This has fueled the need for a new class of micro-pumps based on active and passive schemes.

“Microfluidics still suffers from the lack of a small, cheap and easy to integrate micro-pump,” said Alexander Govyadinov, an R&D engineer at Hewlett-Packard. “Generally, for a breakthrough to occur in microfluidic system development, essential microfluidic elements, pumps, valves, mixers and sensors, need to be integrated via low-cost fabrication technologies. There is also a lack of a killer application. A lot of progress happened, but even more development is required.”

There are other manufacturing challenges as well. “Most structures are 25 or 50 microns,” said Donald Johnson, chief executive of DJ DevCorp, a supplier of specialty dry film resist materials. “Now, there is a drive to get smaller dimensions. If you are looking at the channels, you want to get them down to a few microns. If you look at surface structures, you may be putting nano-structures on the surface.”

The initial, and many of the current, microfluidic devices are composed of silicon or glass and are made using etch and other processes taken from the semiconductor industry. “In many cases, the devices were manufactured using a single material, such as a microfluidic channel etched into a glass plate and sealed with a glass plate, yielding a monolithic microfluidic glass chip,” Johnson said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

The high cost involved in processing glass and silicon has prompted many vendors and research labs to use cheaper and transparent polymer materials like polydimethylsiloxane (PDMS). The polymer does not self-assemble, but rather the material is used to create the patterns or channels in a microfluidic device.

There are several ways to make a microfluidic device. In one common method, a vendor first makes a “master pattern” or “mold” of a microfluidic device. To make a mold, a resist, photomask and an absorber pattern are first applied on a substrate. Then, the “master mold” is patterned using laser ablation, micromilling or lithography.

Once the “master pattern” is created, the device is then replicated. There are several methods to replicate a device, such as casting, injection molding, thermoforming and hot embossing. A more advanced hot embossing technique is called nanoimprint lithography, which could shrink the channels down to the nano-scale. “You will probably see more embossing than imprint today,” Johnson said. “Nanoimprint is mainly in R&D at this point.”

Some are also using a technology called multi-layer soft lithography. In this process, a liquid polymer is poured over the mold. After a curing process, the polymer is peeled off the mold, leaving an imprint of the topography. Several layers of elastomer, which have different patterns, can be stacked and bonded. A microfluidic device usually has two elastomer layers for the flow and control functions.

New and emerging apps
The manufacturing processes and material choices depend on the application. For example, U.S.-based Micronics, which was recently acquired by Sony, last month launched a single-use, disposable card system that makes it possible to quickly determine a blood type.

Developed in part under funding from the U.S. Army, the company’s so-called ABORhCard is designed for a field-deployable test of potential blood donors in austere settings. “We were the first microfluidics company to move away from PDMS and glass to laminates. Final products are hybrid structures-laminates and injection mold,” said Karen Hedine, president of Micronics.

Another application is for a cell detection and sorting system. Cell sorting separates cells according to their properties. The microfluidics device in such a system can be done using micro-contact printing. “A well-known technique is done by contact printing, which can generate monolayers on the surface,” said Tohid Fatanat Didar, a visiting scholar within the Wyss Institute for Biologically Inspired Engineering at Harvard Medical School.

Microfluidics also plays a role in the emerging organ-on-a-chip field. Last year, the National Institutes of Health (NIH), the Defense Advanced Research Projects Agency (DARPA), and the U.S. Food and Drug Administration (FDA) announced plans to develop a chip technology that could screen drugs and vaccines more rapidly and efficiently than current methods. The chip is based on specific cell types that reflect human biology. NIH will commit up to $70 million and DARPA will commit a comparable amount.

DARPA recently awarded a contract to Draper through MIT. Draper is working on various projects such as a human-on-a-chip, brain-on-a-chip, liver-on-a-chip, and a kidney-on-a-chip.

The brain-on-a-chip project itself combines cellular neuroscience, tissue engineering and microfluidics. The chip aggregates cultured neurons, astrocytes, microglia and brain endothelial cells from rats on two micro-fabricated layers. A microfluidic pump was used to circulate nutrients or therapeutics across the vascular channels simulating blood flow. “What we’re trying to do is take the most important features of an organ and scale them down to the micro-scale. Then, you put them on some kind of a platform, where you can evaluate them,” said Draper’s Borenstein.

The fabrication process is straightforward. “You start with a silicon wafer process. And then you transfer that into a polymer using some kind of a molding or embossing technique,” he said. “The bigger challenge is to transition this from a silicon to a non-silicon base. We do not use the latest and greatest photolithography. In fact, most of the photolithographic work that’s done in our lab is done with structures that may have a minimum dimension of 10 microns.”

Still, Draper and other entities will need new manufacturing breakthroughs. “Hot embossing is a good example. Hot embossing is a great process, but it’s a little bit slow,” he said. “The material that has carried the microfluidic field for many years is called PDMS. It’s very inexpensive and easy to process, but it’s not particularly stable chemically.”

Researchers are looking at new and advanced bio-degradable materials for future work. And, of course, the field of organ-on-a-chip technology is still in its infancy. “It’s still in the very early stages,” said Anil Achyuta, principal investigator for the brain-on-a-chip project at Draper. “We have the potential to revolutionize how scientists study the effects of drugs, vaccines, and specialized therapies like stem cells on the brain.”

By Mark LaPedus
Gartner has revealed its top predictions for IT and strategic technology. Among them: By 2014, three of the top five mobile handset vendors will be Chinese; by 2015, big data demand will reach 4.4 million jobs globally, but only one-third of those jobs will be filled; and by 2016, wearable smart electronics in shoes, tattoos and accessories will emerge as a $10 billion industry.

With about 21 months remaining until publicly traded U.S. component manufacturers must disclose their usage of conflict minerals to the government, the electronics industry appears to be unprepared, according to iSuppli. Conflict minerals are defined as those mined in locales of armed conflict and human rights abuses. These minerals, such as tin, tantalum, tungsten and gold, are used in a wide range of components across the electronics supply chain.

According to IDC, end users’ concerns over foreign governments’ access to cloud data, particularly data stored in the U.S., are misplaced. “Scare stories over the Patriot Act abound, but they are fallacious,” said David Bradshaw, IDC research manager for European public cloud services, on IDC’s site. “The Patriot Act is nothing special, indeed data stored in the U.S. is generally better protected than in most European countries, in particular the U.K.”

Hans Mosesmann, an analyst with Raymond James, said: ”While the Street seems to view AMD as imminently going out-of-business we would caution investors otherwise. AMD’s strategy announcement next week (October 29th) will likely be the unveiling of an ARM 64-bit strategic collaboration. With SeaMicro’s world-class fabric, AMD’s strategic positioning becomes quite powerful. We also remind investors that AMD knows the server market quite well, it has an x86 license and it just hired Apple’s processor architect.”

STMicroelectronics reported its third quarter results. The company also cut jobs and reduced its capital expenditures to about $500 million this year. During the quarter, ST-Ericsson’s NovaThor L8540 LTE ModAp platform and the FD-SOI variant of this application processor product were taped out and sample wafer fabrication started. Samples of both products are expected to be available during Q4. STMicroelectronics will fab the chips. ST-Ericsson is a 50-50 joint venture between Ericsson and STMicroelectronics.

During a conference call to discuss its results, executives from STMicroelectronics remained bullish about its efforts with FD-SOI.

TSMC reported mixed results in the quarter. http://www.tsmc.com/english/default.htm “TSMC reported 3Q results and guided 2013 CapEx to $8.0 billion to $8.5 billion, versus $8 billion in 2012, below our estimate of $9 billion. We believe this is consistent with a weakening macro backdrop, coupled with expectation for Apple business to truly ramp in 2014, as opposed to 2013,” said C.J. Muse, an analyst with Barclays Capital. TSMC is expected to make applications processors at the 20nm node on a foundry basis for Apple.

TSMC has purchased 14 hectares of land near Hsinchu, Taiwan. TSMC plans to build an R&D facility for 450mm wafers, as well as 7nm process development, according to TSMC Chairman Morris Chang on Seeking Alpha. Chang also discussed TSMC’s outlook, CapEx, and other topics.

In partnership with the Semiconductor Research Corp. (SRC), ATIC will support 14 research initiatives over the coming year spanning Khalifa University, UAE University, American University of Sharjah, Masdar Institute and New York University Abu Dhabi. ATIC owns a majority stake in GlobalFoundries.

Mentor Graphics has released a new product in the HyperLy-nx suite. h In addition, Kalray has completed its new 160 million gate, 3 billion transistor multi-purpose processor array IC using a Mentor’s functional verification, physical design and verification, and design-for-test flow.

AMD announced its collaboration with Microsoft for more than 125 Windows 8-based PC designs from OEMs, including ASUS, Dell, Fujitsu, HP, Lenovo, Samsung, Sony, Toshiba and more.

During a recent press event at the company’s new headquarters in San Jose, Calif., Maxim discussed integration and other trends in analog. The company also revealed a 90nm process technology and discussed a new class of power system-on-a-chip (SOC) products. And the company revealed its directions, including a strong push in the mobility segment.

Most mobile SoC GPUs were shipped by Qualcomm in the first half, according to Jon Peddie Research.

Texas Instruments announced third-quarter revenue of $3.39 billion and net income of $784 million. “For 4Q ‘12, TI guided revenues to fall 6% to 13%. Annual Capex guidance was cut by $200 million to $500 million, as TI dials back additional capital spending, commensurate with the environment,” said Craig Berger, an analyst with FBR.

Broadcom said revenue for the third quarter of 2012 was $2.13 billion. This represents an increase of 8.0% compared with the $1.97 billion reported for the second quarter of 2012 and an increase of 8.7% compared with the $1.96 billion reported for the third quarter of 2011. “Broadcom reported robust 3Q ‘12 results and gave 4Q ‘12 guidance near Street estimates, better than most peers,” Berger said.

KLA-Tencor reported mixed results. “KLA-Tencor’s results for the first quarter of fiscal year 2013 reflect today’s challenging demand environment for the wafer fab equipment industry,” said Rick Wallace, president and CEO.

It was a tough quarter for ATE giant Teradyne. The company reported Q3 revenues of $463 million, up 35% from the same period in 2011. But Q4 orders are down 61% from this quarter  quarter and Q4 revenue is forecast at between $235 million and $260 million.

By Mark LaPedus
Intel reported quarterly revenue of $13.5 billion and net income of $3.0 billion. http://finance.yahoo.com/news/intel-reports-third-quarter-revenue-200100019.html C.J. Muse, an analyst with Barclays Capital, said: “Intel lowered its capex guidance to $11.3 billion for 2012 vs. our estimate of $11.8 billion. While we believe Intel will remain vigilant in the ramp of 14nm, as Intel looks to aggressively redirect space and equipment to 14nm (80-90% of equipment bought at 22nm is reusable at 14nm node), we see capex of ~$9 billion +/- $1 billion in 2013.”

Is AMD on the ropes again? AMD will cut its workforce by approximately 15%. It also announced revenue for the third quarter of 2012 of $1.27 billion and a loss of $157 million. “Management’s ongoing mis-execution in our opinion seems to be contributing to building too much inventory, firing top operational managers, channel misalignment (and) withdrawing from broad swaths of the market,” said Craig Berger, an analyst with FBR. Meanwhile, analyst, Hans Mosesmann of Raymond James, said: “The worrisome but not too surprising commentary by AMD management was that the PC market will take several quarters to recover. AMD now considers 85% of its current business ‘legacy’ PC, with the planned restructuring focused on attacking various adjacent high-volume markets.”

Seeking to accelerate the development of EUV lithography, ASML has entered into a definitive agreement to acquire Cymer for $2.6 billion. “Cymer’s light source is critical to EUV success and given recent slippage of key metrics, we think it makes sense for the technology to move in-house at ASML,” Muse said.

In response to its foundry rivals, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has updated and accelerated its finFET roadmap.

GlobalFoundries could employ as many as 3,000 workers at its Malta plant, according to reports.

STMicroelectronics’ 28nm Fully Depleted Silicon-On-Insulator (FDSOI) process, which uses substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP.

Soitec announced total consolidated sales of 130.2 million euros for the first half, down by 19.9% on a yearly basis.

European government representatives, consortia and suppliers discussed 450mm fabs at Semicon Europa in Dresden.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.81 in September, compared to 0.84 in August, according to SEMI.

Mentor Graphics has rolled out a formal-based technology in the Questa Verification Platform.  In addition, Mentor announced new capabilities to complement TSMC’s 20nm manufacturing processes.  Meanwhile, SpringSoft and Mentor announced that the Laker-Calibre RealTime custom layout flow has been selected for the TSMC Custom Design Reference Flow. In a related announcement, TSMC has presented Mentor with two “Partner of the Year 2012” awards in various categories. And, Mentor announced the winners of its 24th annual PCB Technology Leadership Awards.

At the Storage Networking World (SNW) conference, there was no shortage of SSD presentations. But none of the keynoters who shared their data center experiences had deployed any SSDs in their systems. This seemed particularly odd to The SSD Guy.

Amazon is in talks to buy the mobile chip business of Texas Instruments. TI’s chips are used in Amazon’s Kindle Fire tablet.

FormFactor completed its acquisition of Astria Semiconductor Holdings and its subsidiary MicroProbe.

Lam Research achieved revenue of $906.9 million, up 22.3% from prior quarter, in first full quarter of consolidated results with Novellus.  “Based on continued push-outs of NAND spending, Lam guided to December quarter revenues of $820-880 million, well below consensus of $927 million,” said Barclay’s Muse. “While management had previously suggested that 2012 WFE was tracking to the low end of the $29-30 billion outlook, management took the opportunity to lower their 2012 WFE outlook to about $28-29 billion.”

Xilinx announced fiscal Q2 2013 sales of $543.9 million, down 7% sequentially and down 2% from the second quarter of the prior fiscal year.  Barclay’s Muse said: “Xilinx reported mixed September quarter results and then guided to worse December quarter, highlighting continued macro pressure for semis.”

Microchip Technology has lowered its forecast. “Our lower than anticipated net sales activity in the September quarter was driven primarily by macroeconomic and industry conditions,” said Steve Sanghi, Microchip’s president and CEO. “The overall global economic outlook continues to be poor and is adversely impacting our business as well as the rest of the semiconductor industry.”

Marvell expects net revenue for the third quarter of fiscal 2013 will be in the range of $765 million to $785 million, compared with prior outlook of between $800 million to $850 million. “The continued slowdown in the global economy during the third quarter is resulting in a weaker PC market than previously anticipated and thus lower demand from our storage HDD customers,” said Sehat Sutardja, Marvell’s chairman and CEO. FBR’s Berger said: “We think Marvell has a structural management problem that inhibits the firm from realizing real change, may discourage the development of formalized engineering processes, and keeps the firm on what seems to be a self-destructive path of no growth and limited traction in cellular. With the board unwilling to make real changes, business at Marvell could migrate from bad to worse over time.”

The NAND and NOR flash memory market landscape is shifting rapidly, with increasingly sophisticated mobile handsets playing a leading role in driving industry trends and determining which suppliers will be successful, according to IHS iSuppli.

By Mark LaPedus
In total, silicon foundry capital spending is expected to reach about $21 billion in 2012, flat from 2011, according to Barclays Capital. In 2013, foundry CapEx is expected to fall 1% to 20.9 billion, according to the firm. TSMC will see its CapEx jump from $8 billion in 2012 to $9 billion in 2013, but Samsung LSI’s CapEx will fall from 8 trillion won in 2012 to 6 trillion won in 2013, according to the firm. “We model GlobalFoundries CapEx inching up slightly to $3.7 billion in 2013 from $3.4 billion in 2012, and UMC CapEx moving slightly higher to $2 billion in 2013 from $1.8 billion in 2012,” said C.J. Muse, an analyst with Barclays. Muse also predicts total CapEx will fall about 5% in 2012, compared to flat in the previous forecast. He lowered his overall CapEx outlook for 2013 to minus 10%, compared to flat to minus 5% in the previous forecast.

TSMC has taped out the foundry segment’s first 3D chip test vehicle using JEDEC’s Wide I/O mobile DRAM interface. TSMC’s partners in the effort include Wide I/O DRAM from SK Hynix, DRAM IP from Cadence, and EDA tools from Cadence and Mentor Graphics.

GlobalFoundries announced a partnership with Masdar Institute to help spur the continued development of Abu Dhabi as a center for semiconductor R&D and manufacturing.

Soitec and Shin-Etsu Handotai have agreed on an SOI licensing extension.

Chinese SOI supplier Shenyang Silicon Technology (SST) has emerged. SST has installed EV Group’s 300-mm, low-temperature automated production bonding system for SOI materials. The China-U.S. joint-venture SOI wafer provider has selected the 300mm bonder as a follow-on to its prior purchase of a 200mm tool from EV Group. The system already has shipped to SST’s facility, marking the first installation in China of a 300mm SOI wafer production tool.

Ericsson and STMicroelectronics currently are working with an external adviser to ensure the best possible future for ST-Ericsson. ST-Ericsson, a 50-50 joint venture between Ericsson and STMicroelectronics, is developing cell-phone chips based on SOI.

According to Strategy Analytics, Qualcomm led the smartphone applications processor market in the first half of 2012. Samsung, MediaTek, Broadcom and TI took the rest of the top-five spots. ST-Ericsson continued its recovery and showed 28% sequential growth in Q2.

SEMI released its annual silicon shipment forecast for the semiconductor industry

The LED industry has added roughly 100 new fabs in the last five years, for a total of 169 fabs worldwide, according to SEMI.

China will spend 250 billion yuan, or about $40 billion, and expects a half million people will be employed in the solar industry by 2015. Additionally, the plan sets a target of 50GW installed capacity by 2020, according to SEMI.

Soitec has completed delivery on a total of 5 megawatts (MW) of its concentrating photovoltaic (CPV) systems to seven solar power plants throughout Italy.

NPD Solarbuzz forecasts that polysilicon production will be greater than solar industry requires in 2012.

ARM has tipped its strategy to crack the server market.

Calxeda, which is developing ARM-based chips for servers, announced $55 million in additional funding.

Following the adoption of a new networking standard, suppliers of embedded computer systems based on AdvancedTCA technology are looking to expand their efforts into new and traditional markets.

Here’s the latest from the Cowan LRA Model: “According to the WSTS’ August actual global semi sales of $23.013 billion, the updated monthly forecast expectation for full year 2012’s total global semi sales is expected to be $294.6 billion. This latest update to the 2012 sales forecast estimate corresponds to a year-over-year sales growth expectation of minus 1.7%, which dropped from the previous month’s year-over-year sales growth forecast estimate of minus 0.5%. 2013′s full year forecasted sales growth expectations is (plus) 7.4%.”

By Mark LaPedus

IC makers have been looking at the electric vehicle industry for growth. So whatever happened to the electric car? Toyota has scaled back the sales targets for its electric car. According to Lux Research, the head of Toyota’s vehicle development gave a vote of no confidence for the technology, by saying the “capabilities of electric vehicles do not meet society’s needs.” Meanwhile, Tesla Motors recently lowered its sales targets. Another car maker, Nissan, is offering big discounts on the Leaf because of slow sales. GM’s Chevy Volt has struggled to win customers, even though it’s not purely electric. And Fisker Automotive, which uses the same approach as Chevy, has experienced an assortment of problems.

At the 2012 IEEE International Electron Devices Meeting (IEDM), slated for Dec. 10-12 in San Francisco, Applied Materials and Synopsys are expected to submit a paper entitled, “Is strain engineering scalable in FinFET era? Teaching the old dog some new tricks.” “Strain technology has been a key enabler for improving transistor performance in the past decade. With the industry moving toward a 3-D FinFET structure from a planar MOSFET, the corresponding implications on stressor design needs to be analyzed afresh due to strong orientation dependence of stress enhancements,” according to the IEDM abstract from the companies. “In this work we have tried to address both issues; stressor design for FinFETs and scalability of corresponding stress enhancements. We found that the S/D epi remains an effective and scalable source of strain engineering for FinFETs. Contact and gate metals provide new knobs for engineering strain in FinFETs and remain effective with conservative scaling of contact/gate CD.”

Altatech, a subsidiary of Soitec, has introduced a multi-chamber chemical vapor deposition (CVD) system that enables photovoltaic (PV) cell manufacturers to develop and optimize their solar cell designs using advanced thin-film deposition of amorphous silicon and other materials. By performing all deposition processes within a single system, the new AltaCVD Solarlab tool reduces cycle times and materials consumption in fabricating advanced single-junction, tandem-junction and triple-junction PV cells.

GlobalFoundries is preparing to build a three-story, 565,000-square-foot manufacturing research center, according to a report.

While over-capacity continues to plague the global solar industry, the Taiwan PV industry is operating at high-capacity, according to SEMI.

SVTC Technologies is struggling and has apparently cut workers, according to reports, which added that the R&D foundry is mulling plans to close its sites in Austin, Texas and San Jose.  Multiple sources say SVTC may completely shut down. In an e-mail, SVTC declined to comment on the reports. A spokesman for Oak Hill Capital declined to comment. Oak Hill is an investor in SVTC. In 2007, Cypress sold its R&D fab unit to Oak Hill and Tallwood Venture for approximately $53 million. SVTC became a “lab-to-fab” facility aimed at third-party engineering groups.

As it turns out, Tezzaron Semiconductor has signed a contract to purchase the assets of a semiconductor technology development and wafer fabrication facility in Austin, Texas, previously run by SVTC. Tezzaron will continue the operations of this facility while adding capabilities to assemble its own 3D devices.

Struggling Renesas has obtained a $6 billion bailout from various banks. The chipmaker announced the execution of an agreement of a syndicate loan, with Mizuho, The Bank of Tokyo-Mitsubishi UFJ, Sumitomo Mitsui Trust Bank and Mitsubishi UFJ Trust and Banking Corporation.

Sharp has obtained a syndicated loan as it struggles to find investors.

For its 2012 fiscal year, Micron reported a net loss of $1.03 billion. C.J. Muse, an analyst with Barclays, said: “While Micron was hesitant to provide any speculative commentary around the potential Elpida acquisition, management did note that the deal is expected to close in [the first half of calendar year 2013].”

The JEDEC Solid State Technology Association has announced the initial publication of its Synchronous DDR4 standard.

Intel and its OEM partners unveiled the first wave of new tablets and tablet convertible designs based on Intel processors, including the new Atom Z2760, formerly codenamed “Clover Trail.”

Samsung’s foundry business has been selected by STMicroelectronics to provide it with products at the 32/28nm process node.

X-Fab plans to invest more than $50 million in its MEMS operations over the next three years.

Diodes plans to acquire Power Analog Microelectronics.

Gartner says Windows 8 is a big gamble Microsoft must make to stay relevant.

IC Insights believes that the more profitable foundries will be those that keep at the leading-edge of the process technology roadmap.

The average amount of DRAM in each smartphone shipped worldwide is expected to surge by nearly 50 percent this year, according to iSuppli.

By Ed Sperling
After years of talking about equivalent pricing, technical advantages and consistent processes, silicon on insulator finally appears to be making significant inroads—but not necessarily in ways, places, or even at process nodes where it initially was predicted to gain ground.

What’s driving at least some of this change is the semiconductor industry’s progression toward stacked die, where commercially available die will be produced in whatever process and on whatever substrate makes the most sense for the manufacturer. What wins the socket—or at least the layer or space in the package—will be price, energy efficiency and performance, although not necessarily in that order. In most cases, however, that means new materials rather than bulk CMOS.

Consider the Hybrid Memory Cube, for example. While the majority of attention being paid to the 3D memory architecture is at the DRAM level, the logic base layer—in this case made by IBM—uses an SOI substrate. And while the initial application is for enterprise applications, where high performance and low power are critical and pricing is less of an issue, there already are discussions underway between Micron and a number of other vendors beyond just the data center.

Scott Graham, general manager of hybrid memory at Micron, said the next generation of the HMC will be in production by the end of next year, with volume applications using 3D-ICs with TSVs in 2015 or 2016. But he said the existing HMC architecture also can be attached to FPGAs, either in a vertical stack or in a 2.5D configuration. The result is that SOI becomes an integral part of 2.5D and 3D stacks, even if some of the other pieces use different materials.

“You can attach the cubes to each other or to FPGAs,” said Graham. “We’re looking at a variety of flexible architectures and protocols.”

Having an additional layer of insulation is a bonus in that architectural arrangement, as well, to buffer against a variety of physical effects ranging from noise to heat—as long as the heat doesn’t get trapped inside a device. So far, the existing architectures allow for heat to escape through exposed sides of the device. In stacked die, getting the heat out requires a variety of architectural approaches ranging from using TSVs as chimneys to using more exotic and expensive approaches such as liquid cooling within a die with microfluidics.

From planar to stacked die
SOI—as well as other substrate materials—are showing up in planar devices, as well. Companies wrestling with a compendium of physical effects at the leading edge of Moore’s Law say that for most applications new materials will be necessary going forward.

Intel remains the poster child of bulk CMOS. It steadfastly has resisted changing from bulk CMOS. But Intel’s architecture also is much more regular and redundant than most others being developed in the IC world. Systems on chip have many more irregular subsystems, which may or may not be on at any given time, and which frequently generate heat, electromagnetic interference and noise in an inconsistent manner that in some cases is determined by user preferences. That causes some parts of the chip to heat up while others remain cool, and with gate oxides now measured in Angstroms additional insulation is considered a very good thing.

Solving all of those problems with guardbanding, the necessary architectural changes, and being able to obtain sufficient yield are difficult, time-consuming and expensive.

“The cost issue is a tough one to deal with from a technology point of view,” said Chenming Hu, professor at UC Berkeley who is considered the father of the finFET. “I believe the world be willing to pay more if none of the semiconductor companies can continue to slash prices. And from a performance/power consumption perspective, I feel quite confident this industry will continue to grow. In the immediate future, finFETS and UTB/ET/FD-SOI are very exciting technologies.”

STMicroelectronics already has begun productizing FD-SOI at 28nm. “We are in the low-power SoC space, and particularly with our subsidiary ST-Ericsson in the mobile computing space, we were looking for a solution that could provide differentiation in terms of efficiency,” said Philippe Magarshack, ST’s corporate vice president of design enablement and services. “We identified planar SOI as the next step going forward. We also identified with our customers what would be the sweet spot for our customers. We had working test chips earlier this year that confirmed our decision to move forward. Our decision was to put a product on the market as soon as possible for the next-generation applications processor.”

He said that one significant advantage of using SOI is the ability to polarize the back edge. “There is more design involved, but we get a 20% boost in efficiency right off the bat. With back-gate biasing you get 30% to 35% boost at high Vdd, and 80% boost at low Vdd. We have use cases in cell phones where the battery life is extended by 30% to 40%. This is a significant benefit.”

IBM holds a similar view, particularly at 20nm.

“We see this really addressing two areas in the SoC space,” said Gary Patton, vice president of IBM’s Semiconductor Research and Development Center “One is that the cost of migrating designs into the next technology node is becoming extremely expensive. The ability to take 28nm technology and do a fairly straightforward migration to FD-SOI and get an immediate performance boost is extremely attractive. But the value proposition of 20nm planar technology has been disappointing for many customers both in terms of cost, because of double patterning, as well performance. Being able to apply FD-SOI to 20nm significantly enhances that value proposition.”

The future
The combination of finFETS plus different substrates provides a couple knobs to turn to reduce leakage and minimize heat. Add that to stacked die, where bigger pipes require less power to drive signals over shorter distances, and the picture becomes even more appealing.

As Micron’s Graham noted, SOI is just a first step in what will likely be a much more rational use of materials to solve very specific problems in stacked die. SOI is an important material, but it is just one of many now under consideration. Nevertheless, it does solve problems for at least a couple more process nodes and in stacked configurations, and at this point most leading edge companies say it is the least-expensive proven solution.

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics. What follows are excerpts of that conversation.

SMD: Are the tools that are available today sufficient to deal with the challenges at hand in terms of manufacturing and packaging?
Geronimi: It’s time to move from a custom solution to an engineered solution.
Aitken: If you look at double patterning, there’s a routing challenge, especially on metal-one. You go through so much effort on standard cell design and you design something that’s decomposable using the various coloring rules that there’s no way you’re going to let the router touch it. Routers don’t understand enough about design rules to be allowed anywhere near it. That is an inherent inefficiency. You lose a fair amount of density by not letting routers onto metal-one. There are similar tool gaps for what metal corners look like. There’s another one in terms of electromigration and IR drop. There are a lot of tool gaps and designers are working around them, but the inefficiencies are there. Better tools could help eliminate some of those inefficiencies.
Capodieci: With respect to multiple levels of patterning, although we’re doing a lot of joint work there I haven’t seen a robust solution being deployed. We need to attack the problem of multi-patterning to realize that problem will be solved by solving another problem—from decomposing things into manufacturable blocks. For directed self assembly or direct-write, some other form of non-patterning approach will be used. Multiple patterning is a useful exercise. I don’t think it’s going to lead us toward an industrial solution because triple and quadruple exposures and all the processes associated with that have technical and financial problems.

SMD: The design industry looks at what can be created, while the manufacturing side looks at it from the standpoint of whether it can be produced with reasonable yield. As business considerations begin creeping into both sides, how does that affect this relationship and the decisions being made?
Liebmann: There’s an increasing reluctance, at least from the tooling side, to bite off more than is digestible. We’ve talked about construct-based design. That extends into construct-based routing. I haven’t found any takers for a router that can deal with 100 legal configurations and nothing else. That’s a very long and expensive development project that the EDA industry won’t take. So we’ve had good luck making improvements to the existing design base. But to really make revolutionary changes on the design side is just as hard as making evolutionary changes on the manufacturing side.
Geronimi: There are things we need to consider now. If we don’t get the tools to work we will have much more difficulty later on.
Liebmann: A lot of this comes back to the lack of a clear roadmap. The ITRS roadmap has become something of a useless document at this point because it extrapolates to zero without taking into account these very disruptive things that are happening, such as double patterning, maybe the switch to EUV, and the introduction of self-assembly. Without a clear road map it’s difficult to ask the EDA industry to invest in a six-year project to develop a new routing technology.
White: It is challenging, with finite resources, to invest a huge chunk in a product development team that can go off and do something that will take multiple years to create a solution. What you find within the industry is that it’s easier or more straightforward to improve on the infrastructure that we know and extend it. That’s the general strategy you’ve seen from all of us.
Lin: Right now most of the burden of double patterning is on the foundry and EDA. I would like to encourage the fabless design houses to look at the different options, not just to rely on EDA and the foundries.
Aitken: What we found with double patterning is that there are two kinds of foundries in the world. There are those that want to see colors and separation in the layout and those that do not. We find it’s actually harder to do the ones that don’t separate because what we do is add the colors, to prove that it can be separated, and then we erase the colors and hope they can find the same decomposition that we did. I’m not convinced that’s the optimal way to do something. Decomposition is a major challenge. Double patterning is at least solvable in normal terms. Triple patterning will require heuristics.
Liebmann: Sometimes marketing gets in the way. There is a fear of inconveniencing the customer, which in this case is the fabless design house. There is no way around it. If you do double patterning, the designers have to get engaged and understand the fundamental problem. This whole idea of coloring is just one way where you need to convince the customer there is a problem, but once they understand that I think it’s a very solvable problem.
White: As we work with customers doing these kinds of designs we are seeing a convergence. Industry-wide, there’s a growing tolerance of coloring. In many instances it’s important information that otherwise is being lost.
Capodieci: We cannot be color-blind. We must see in color.

SMD: Who’s responsible as things go wrong with a more complicated design?
Capodieci: The collaborative model that many of us have been putting in place even at 28nm, where there is very limited usage of double patterning, will be the only way forward. Part of the color awareness is that. It’s not just exchanging operational information about the coloring. It’s also understanding what the corner cases are with the IP and with the routing. Rather than taking the responsibility for blame, we all have a shared responsibility for success. That also means we have a shared responsibility for failure.
Lin: It helps that we have more pieces internally and are working with our external customers. Our early learnings will help us to work with customers earlier.
Capodieci: The golden rule is, ‘When in doubt, blame the vendor.’ If you are an IDM, you blame whoever is external. If you are in a more complex ecosystem, whoever is holding the vendor badge that day gets the blame. Triple patterning brings to the surface a very complex interaction. There are EDA, the foundry, the design customers, and a very stratified group of IP vendors. So maybe there is not a single solution.
Aitken: It’s a very important question. When you look at it historically, we’ve evolved a number of different handoff points. The DRC deck is a classic one. It’s either legal or it’s not. If it fails and it was legal, it’s the foundry’s problem. If it fails and it was illegal, it’s your problem as a layout person. There’s growing recognition that’s not adequate. We want it to be DRC-legal, but we also want sufficient yields, so we check and make sure the things we think are DRC-legal will yield even if the DRC says they will. That level of collaboration will be necessary going forward. The business arrangements haven’t quite figured out how to track it yet, but they’re going to have to. The ‘blame the vendor’ approach is one way to do it, but if it’s your part that isn’t shipping then you’re the one getting fired and that doesn’t matter. So it’s everyone’s responsibility.
Capodieci: That’s exactly right, and that’s why we need to talk about shared responsibility. Regarding the example about DRC and additional yield assurances, many problems today make DFM verification decks mandatory. You must achieve a certain score. There is an open pass/fail, based on the fact that you’d like to have an 85% score on your recommended rules. How you achieve that score depends on which geometries you want to push and which ones you want to relax. This can be seen as an additional level of complexity, but it’s also an additional level of freedom. You can play around with your physical design and still get to tapeout.
Lin: You have to define a very thick interface and define things very clearly. Within the same company you can resolve the problem over lunch. Here you need a very clear explanation.
Geronimi: Unfortunately with double patterning, if you cannot get to signoff you cannot manufacture it.
Aitken: I disagree. When you have some very complicated structure you can sign off and say it passes, and you have no real assurances that it works. That’s where the challenge is.
Geronomi: From a double patterning standpoint, when you look at whether you can decompose it or not, you go to manufacturing with colors expecting the rules to work correctly. At least with single patterning you know that even with very complex rules, you can manufacture the design.
Liebmann: That, to a large extent, is why double patterning is in better shape than DFM. DFM is very vague. Who owns it? Is it really required? Is it optional? With double patterning, it comes down to a double patterning-enhanced rule set. You either pass DRC or not. It’s very clear.
Aitken: but there are some challenges there, too. If you create decomposition and send it to a fab, suppose they recolor it and it fails. Who’s problem is it?
Capodieci: That’s why we have been expanding the safety net of DFM to include additional checks for double patterning. We had to add scores for double patterning. Plus, we are finding that a lot of patterns are derived from decomposition. DFM will have an enhanced role to catch everything to catch the holes left by double patterning. At the end of the day, double patterning needs to come together to create a single mask for future processing. That’s the key. It’s easy to break. The question is, when you put it back together will it yield?