Ira Feldman provides an interesting perspective on last month’s SEMI Industry Strategy Symposium. He notes that numerous speakers including Jon Casey (IBM) and Mike Mayberry (Intel) stated that scaling will continue below the 10 nm process node perhaps to 5 or 7 nm. However, the question raised by both the speakers and the audience was at what cost will this scaling be achieved.
“Long live the FinFET,” says Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc. In this blog post, he describes how designers will have to seek out new tools and methodologies to overcome FinFET design challenges. One example is the adoption of giga-scale parallel SPICE simulators to harness circuit simulation challenges in FinFET designs. Traditional SPICE simulators don’t have the capacity and lack sufficient performance to support FinFET designs, while FastSPICE simulators likely will not meet accuracy requirements, he writes.
Adele Hars of Advanced Substrate News reports that STMicroelectronics will soon be announcing a “major foundry player” that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company’s Q4 and FY13 presentation in Paris on January 28th.
Phil Garrou finishes up his review of the IMAPS 2013 meeting, with an analysis of Xilinx/SPIL results from their 2.5D 28nm FPGA program, a review of the Copper TSV work presented by Nanyang/IME, Canon’s FPA-5510iV and FPA-5510iZ TSA steppers designed to support high density processes and the implementation of 2.5 & 3D technology, and a report on the embedded technology being developed by AT&S.