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What is Your China Strategy?

Wednesday, September 7th, 2016


By Dave Lammers, Contributing Editor

Equipment vendors have a lot on their plates now, with memory customers pushing 3D NAND, foundries advancing to the 7 nm node, and 200mm fabs clamoring to come up with hard-to-find tools.

China, which has renewed its investments in displays, packaging, and both 200mm and 300mm front-end fab capacity, is another challenge.

“All the managers in my company are scrambling to adjust their budgets so they can support China. I can tell you people are booking lots of flights to Shanghai,” said one engineer at a major equipment supplier.

Bill McClean, president of IC Insights (Scottsdale, AZ), said China is fast becoming a center for 3D NAND production, as several companies expand production in China. Intel is converting its Dalian, China fab partly to 3D NAND, and Toshiba might very well make a deal in China to build a 3D NAND fab there, he said.

“China could be the 3D NAND capital of the world,” McClean said at The ConFab conference in Las Vegas. While the U.S. government limits exports of leading-edge technologies on national security concerns, 3D NAND relies more on overlay and etch techniques at relaxed (40nm) design rules, he noted.

“Since the 3D NAND makers are not pushing feature sizes, it doesn’t raise red flags like if Chinese companies wanted FinFET technology. That is when the alarms go off,” McClean said.

However, McClean said the 3D NAND market is not immune to the oversupply issues that now face the DRAM makers. “I’ve seen this rodeo before,” McClean said.

China’s domestic IC market is slightly more than $100 billion, McClean said, while chip production in China was about $13 billion last year, representing just under 5 percent of worldwide production (Figure 1).

Figure 1. Source: IC Insights.

The difference between consumption and domestic production, referred to as the delta, is made up by imports. “This 13 percent (from domestic suppliers) drives the Chinese government crazy. Yes, they will close that gap a little bit, but not to the extent that they think,” McClean told The ConFab audience in mid-June.

Robert Maire, who consulted for SMIC on its initial public offering in the United States, spoke at length about China at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) in Saratoga Springs, N.Y. Amid the mergers and acquisition frenzy of last year, China managed to pull off the acquisitions of CMOS image sensor vendor Omnivision, memory maker ISSI, the RF business of NXP, Pericom Semiconductor, and Mattson Technology. (McClean said he believes that if the Omnivision acquisition were attempted in today’s more China-wary environment that Washington would block the deal).

Maire, principal at Semiconductor Advisors (New York), said China is far behind in its domestic semiconductor production equipment business. “If China has 14nm production capacity, but buys all of its equipment from abroad, it doesn’t really help them that much. China is getting started in equipment, but it has a lot of catching up to do.”

Scott Foster, a partner in market intelligence firm TAP Japan (Tokyo), said China must have an international scope in the equipment sector if it hopes to compete with the likes of Applied, Lam, and other well-established vendors. A few of Japan’s equipment suppliers are succeeding while operating in relatively narrow niches, but overall, competing globally is a challenge for mid-sized Japanese equipment companies. “If this is what is happening to Japanese equipment vendors, what chance do Chinese companies have?” Foster said.

Packaging may prove to be key

Skeptics of China’s prospects might take a long look at China’s success in packaging, an area where China is succeeding, in part by acquisitions of Asia-based companies, notably STATS ChipPAC (Singapore), which was acquired by Jiangsu Changjiang Electronics Technology Co. (JCET) last year. Separately, SMIC and JCET formed a joint venture to focus on chip scale packaging, wafer bumping, and fan-out wafer level packaging. The packaging joint venture is located 90 minutes from Shanghai, said Sonny Hui, senior vice president of worldwide marketing at SMIC.

Jim Walker, the packaging analyst at market research firm Gartner, said China-based packaging is now valued at nearly half (43 percent) of all worldwide packaging value by IDMs and OSATs. While the packaging industry overall is dealing with price pressures, the advent of wafer level packaging, and other forms of multi-chip integration, bodes well for the higher end of the back-end industry.

“As the semiconductor industry matures and Moore’s Law scaling slows, multi-chip integration via packaging is providing system vendors with a faster time-to-market, and a lower-cost means, of solving system-level challenges,” Walker said.

Packaging multiple chips in a module is likely to play a key role in the Internet of Things (IoT) markets, Walker said. Automotive, medical, home, and consumer solutions are all “heavily reliant on packaging,” he said.

Sam Wang, a Gartner analyst who focuses on foundries, pointed out at Semicon West that China’s semiconductor industry faces continued challenges in a hotly contested foundry market. Few China-based foundries have enjoyed the strong growth that SMIC has demonstrated, he said. (SMIC has been “running at very high utilizations, and we are working very hard to solve the problem,” said SMIC’s Hui.)

While SMIC has enjoyed double-digit growth for several years, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total worldwide foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

China-based companies are focusing partly on MEMS and other devices made on 200mm wafers, including analog, sensors, and power. SMIC’s Hui said “most of our customers don’t see much benefit to migrate to 12-inch. 200mm still has a lot of potential; just consider the hundreds of products still made on 180nm technology, which was developed 20 years ago. Many customers still see that as a sweet spot.”

Foster, who has three decades of tech-watching experience from his base in Tokyo, said the 200mm wafer fabs being built in China will make products that “do not need the gigantic scale” required of Intel, TSMC, Samsung and Toshiba. Figure 2, courtesy of SEMI, shows the seventeen 200mm wafer fabs/lines that are expected begin operation in 2015 to 2019. Six of the seventeen will be in China.

Figure 2. Source: SEMI

“After decades of trying, China has found a market-based strategy: building scale and experience from the bottom up. In the long run, this is likely to be far more effective than going out to buy foreign companies,” Foster said.

Display is another area China is counting on. In an Aug. 18 conference call following a strong quarter, Applied Materials chief financial officer Bob Halliday told analysts: “In display, we recorded record orders of $803 million with more than half coming from projects in China.”

The Applied CFO also said, “Just listening to the Chinese government, they’re in this for a long-term and their interest in investing in the semiconductor industry is probably only going to increase.”

Kateeva turns to China funds

China is often lumped together with other Asian nations as a country that has a government-led, me-too, follower mentality. But increasingly, China is either proving innovative itself, or able to quickly adopt innovations from the West.

At the Innovation Forum at Semicon West, Conor Madigan, co-founder of ink jet printer startup Kateeva (Newark, Calif.) spoke about the readiness of Chinese venture capital funds to step in where Silicon Valley-based VCs were overly hesitant. China proved a more receptive place to raise money than the United States, though the early establishment of the M.I.T. spinout did come from U.S. based sources.

After its initial development effort, Kateeva figured it needed more than $100 million to accomplish its goals. After making the rounds to raise funds in the United States without success, Kateeva turned to China, where five different funds eventually became investors.

Asked why Chinese investors were willing to back Kateeva when funds in the United States and other Asian countries were reluctant, Madigan pointed to a confluence of factors.

The Chinese government had identified OLED displays as a focus of its Five Year Plan. The follow-on economic plan further identified inkjet technology as a critical technology. Investors in China favor companies which can provide the equipment for products, such as OLEDs, which have the government’s blessing and financial support. That government support reduced the investment risks in ways that are not readily seen in Japan or the United States, he said.

Madigan had studied OLEDs as an undergraduate at Princeton University, and then studied under an M.I.T. professor who had developed ink jet technology for large formats.

Though an early goal was to use large-format inkjet to deposit the RGB materials in OLEDs, the Kateeva team learned that its YieldJet system could be adapted to solve a more urgent problem: thin film encapsulation (TFE). It “pivoted” on the advice of an early customer, which fortunately already had developed the “ink” which under UV light would form a uniform encapsulation layer for the large OLED substrates required for TVs and other large display applications.

Two display companies in China identified Kateeva as a strategic partner, which allowed Kateeva to raise money from private Chinese VC funds, rather than taking money from regional government funds which might have asked Kateeva to locate its manufacturing operations in their local area.

Madigan also pointed to the tendency of U.S.-based venture capital funds to favor software companies over manufacturing-focused opportunities. As VCs make money in software-related startups, the funds gradually have more partners and investors which favor software because that is what they are familiar with.

VC fund managers with backgrounds in software “want to invest in the space that they understand. In the United States, that often means software, because you pick companies in the space that you understand.”

3D-NAND Deposition and Etch Integration

Thursday, September 1st, 2016


By Ed Korczynski, Sr. Technical Editor

3D-NAND chips are in production or pilot-line manufacturing at all major memory manufacturers, and they are expected to rapidly replace most 2D-NAND chips in most applications due to lower costs and greater reliability. Unlike 2D-NAND which was enabled by lithography, 3D-NAND is deposition and etch enabled. “With 3D-NAND you’re talking about 40nm devices, while the most advanced 2D-NAND is running out of steam due to the limited countable number of stored electrons-per-cell, and in terms of the repeatability due to parasitics between adjacent cells,” reminded Harmeet Singh, corporate vice president of Lam Research in an exclusive interview with SemiMD to discuss the company’s presentation at the Flash Memory Summit 2016.

“We’re in an era where deposition and etch uniquely define the customer roadmap,” said Singh,“and we are the leading supplier in 3D-NAND deposition and etch.” Though each NAND manufacturer has different terminology for their unique 3D variant, from a manufacturing process integration perspective they all share similar challenges in the following simplified process sequences:

1)    Deposition of 32-64 pairs of blanket “mold stack” thin-films,

2)    Word-line hole etch through all layers and selective fill of NAND cell materials, and

3)    Formation of “staircase” contacts to each cell layer.

Each of these unique process modules is needed to form the 3D arrays of NVM cells.

For the “mold stack” deposition of blanket alternating layers, it is vital for the blanket PECVD to be defect-free since any defects are mirrored and magnified in upper-layers. All layers must also be stress-free since the stress in each deposited layer accumulates as strain in the underlying silicon wafer, and with over 32 layers the additive strain can easily warp wafers so much that lithographic overlay mismatch induces significant yield loss. Controlled-stress backside thin-film depositions can also be used to balance the stress of front-side films.

Hole Etch

“The difficult etch of the hole, the materials are different so the challenges is different,” commented Singh about the different types of 3D-NAND now being manufactured by leading fabs. “During this conference, one of our customer presented that they do not see the hole diameters shrinking, so at this point it appears to us that shrinking hole diameters will not happen until after the stacking in z-dimension reaches some limit.”

Tri-Layer Resist (TLR) stacks for the hole patterning allow for the amorphous carbon hardmask material to be tuned for maximum etch resistance without having to compromise the resolution of the photo-active layer needed for patterning. Carbon mask is over 3 microns thick and carbon-etching is usually responsive to temperature, so Lam’s latest wafer-chuck for etching features >100 temperature control zones. “This is an example of where Lam is using it’s processes expertise to optimize both the hardmask etch as well as the actual hole etch,” explained Singh.

Staircase Etch

The Figure shows a simplified cross-sectional schematic of how the unique “staircase” wordline contacts are cost-effectively manufactured. The established process of record (POR) for forming the “stairs” uses a single mask exposure of thick KrF photoresist—at 248nm wavelength—to etch 8 sets of stairs controlled by a precise resist trim. The trimming step controls the location of the steps such that they align with the contact mask, and so must be tightly controlled to minimize any misalignment yield loss.

A) Simplified cross-sectional schematic of the staircase etch for 3D-NAND contacts using thick photoresist, B) which allows for controlled resist trimming to expose the next “stair” such that C) successive trimming creates 8-16 steps from a single initial photomask exposure. (Source: Ed Korczynski)

Lam is working on ways to tighten the trimming etch uniformity such that 16 sets of stairs can be repeatably etched from a single KrF mask exposure. Halving the relative rate of vertical etch to lateral etch of the KrF resist allows for the same resist thickness to be used for double the number of etches, saving lithography cost. “We see an amazing future ahead because we are just at the beginning of this technology,” commented Singh.


Silicon as Disruptive Platform for IoT Applications

Monday, August 29th, 2016


By Ed Korczynski, Sr. Technical Editor

Marie Semeria, chief executive officer of CEA-Leti (, sat down with SemiMD during SEMICON West to discuss how the French R&D and pilot manufacturing campus—located at the foot of the beautiful French alps near Grenoble—is expanding the scope of it’s activities to develop systems solutions for the Internet-of-Things (IoT). Part-1 on hardware/software co-development was published last month.

Korczynski: Regarding ‘IoT’ applications, we expect that chips must be very low cost to be successful, and at the same time the ultimately winning solutions will be those that combine the best functionalities from different technology spaces each in a ‘sweet spot’ of cost to performance. It seems that being able to do it on SOI wafers could produce the right volumes.

Semeria: Yes. It could be enough.

Korczynski: Do you have any feel in advance for how much area of silicon is needed? Some small ADC, an 8-bit micro-controller, and RF components may be done in different processes and then integrated. Is it possible that the total area of silicon needed could be less than a square millimeter?

Semeria: Yes.

Korczynski: Well, if they are that small then we have to remember how many units we’d get from just a single wafer, and there are 24 wafers in a batch…

Semeria: One batch can be enough for one market, depending upon the application.

Korczynski: If this is the case, then even though the concept of purely-additive roll-to-roll processes are attractive, oddly they may be too efficient and produce more units than the world can absorb. If we can do all that we need to do with established silicon wafer fab technology creating ICs smaller than a square millimeter then it will be very cost-effective.

Semeria: Leti’s strategy is to keep the performance of solid-state devices, so not to go to organic electronics. Use silicon as the differentiator to lower the cost, add more functions, and then miniaturize all that can be miniaturized. In this way we are achieving integration of MEMS with small electronics in arrays as small as one millimeter square. When you deal with such small die you can put them inside of flexible materials, inside of a t-shirt and it’s no problem. So that’s our strategy to keep small silicon and put it in clothes, in shoes, in windows, in glasses, and all sorts of flexible materials. When you are thinning substrates for bonding, then the thinned silicon is very flexible.

Korczynski: In 1999 I worked for one of the first companies selling through-silicon via technology, and it was all about backside thinning so I’ve played with flexible wafers.

Semeria: So you know what I mean.

Korczynski: Around 50 microns and below as long as you etch away any grinding defects from the backside it is very strong and very flexible (Fig. 1). At 50 microns the chip is still thick enough to be easily picked-and-placed, but it’s flexible. Below 10 microns the wafer is difficult to handle.

FIGURE 1: 50 micron thin silicon wafers can be strong and very flexible. (Source: Virginia Semiconductor)

Semeria: To maintain the advantage of cost for different applications spaces, we are developing the ‘chiplet’ approach which means a network of chips. It starts with a digital platform, then you add an active interposer to connect different dice. For example you could have 28nm-node on the bottom and a 14nm-node chip on top for some specific function. Then you can put embedded memory and RF connected through the interposer, and it’s the approach that we promote for the first generation of multi-functional integration on digital. Very flexible, cost-effective.

Korczynski: This is using some sort of bus to move information?

Semeria: Yes, this will be an electronic bus for the first generation, as we recently announced. Then a photonics interposer could be used for higher-speed data rate in a future generation. We have a full roadmap with different types of integration schemes. So it’s a way to combine all with silicon. Everything is intended to be integrated into existing 300mm silicon facilities. Some weeks ago we presented the first results showing silicon quantum bits built on 300mm substrates, and fully compatible with CMOS processing. So it’s the way we are going, taking a very disruptive approach using the foundation of proven 300mm silicon processing.

Korczynski: Interesting.

Semeria: For example, regarding driving assistance applications we have to consider fusion integration of different sensors, and complete coverage of the environment with low power-consumption. For computing capacity we developed a completely disruptive approach, very different from Intel and very different from nVidia which use consumer products as the basis for automotive application products. Specifically for automotive we developed a new probabilistic methodology to avoid all of the calculations based on floating-point. In this way we can divide the computing needs of the device by 100, so it’s another example of developing just the right device for the right application adapted for the right environment. So the approach is very different in development for IoT instead of mainstream CMOS.

Korczynski: For automotive there’s such a requirement for reliability, with billions of dollars at stake in product recalls and potential lawsuits, the auto industry is very risk-averse for very good reasons. So historically they’ve always used trailing-edge nodes, and if you want to supply to them you have to commit to 10 or maybe 20 years of manufacturing, and yet we still want to add in advance functionalities. The impression I’ve gotten is that the 28nm FD-SOI platform is fairly ideal here.

Semeria: FD-SOI is very reliable and very efficient. That’s why when we showed our demonstrator at the recent DAC it’s based on the STMicroelectronics micro-controller. It’s very reliable and adaptable for automotive applications.

Korczynski: Is it at 28nm?

Semeria: No, about 40nm now. The latest generation is not needed, because we changed the algorithms so we didn’t need so much capacity in computing. In IoT there is space to use 40nm or 32nm down to 28nm. It’s a great space to use ‘old technologies’ and optimize them with the right algorithms, the right signal-processing, and the right security. So it’s very exciting for Leti because we have all of the key competencies to be able to handle the IoT challenge, and there is a great ability to make various integration schemes depending upon the application. There is a very large space to demonstrate, and to develop new materials.

Korczynski: Does this relate to some recent work I’ve seen from Leti with micro-cantilevers?

Semeria: Yes, this is the work we are doing with CalTech on micro-resonators (Fig. 2).

FIGURE 2: MEMS/NEMS silicon cantilever resonator capable of detecting individual adhered molecules, for integration with digital CMOS in a complete IoT sensing system. (Source: Leti)

Korczynski: Thank you very much for taking the time to discuss these important trends.

Semeria: It is a pleasure.


Fab Facilities Data and Defectivity

Monday, August 1st, 2016


By Ed Korczynski, Sr. Technical Editor

In-the-know attendees at SEMICON West at a Thursday morning working breakfast heard from executives representing the world’s leading memory fabs discuss manufacturing challenges at the 4th annual Entegris Yield Forum. Among the excellent presenters was Norm Armour, managing director worldwide facilities and corporate EHSS of Micron. Armour has been responsible for some of the most famous fabs in the world, including the Malta, New York logic fab of GlobalFoundries, and AMD’s Fab25 in Austin, Texas. He discussed how facilities systems effect yield and parametric control in the fab.

Just recently, his organization within Micron broke records working with M&W on the new flagship Fab 10X in Singapore—now running 3D-NAND—by going from ground-breaking to first-tool-in in less than 12 months, followed by over 400 tools installed in 3 months. “The devil is in the details across the board, especially for 20nm and below,” declared Armour. “Fabs are delicate ecosystems. I’ll give a few examples from a high-volume fab of things that you would never expect to see, of component-level failures that caused major yield crashes.”

Ultra-Pure Water (UPW)

Ultra-Pure Water (UPW) is critical for IC fab processes including cleaning, etching, CMP, and immersion lithography, and contamination specs are now at the part-per-billion (ppb) or part-per-trillion (ppt) levels. Use of online monitoring is mandatory to mitigate risk of contamination. International Technology Roadmap for Semiconductors (ITRS) guidelines for UPW quality (minimum acceptable standard) include the following critical parameters:

  • Resistivity @ 25C >18.0 Mohm-cm,
  • TOC <1.0 ppb,
  • Particles/ml < 0.3 @ 0.05 um, and
  • Bacteria by culture 1000 ml <1.

In one case associated with a gate cleaning tool, elevated levels of zinc were detected with lots that had passed through one particular tool for a variation on a classic SC1 wet clean. High-purity chemistries were eliminated as sources based on analytical testing, so the root-cause analysis shifted to to the UPW system as a possible source. Then statistical analysis could show a positive correlation between UPW supply lines equipped with pressure regulators and the zinc exposure. The pressure regulator vendor confirmed use of zinc-oxide and zinc-stearate as part of the assembly process of the pressure regulator. “It was really a curing agent for an elastomer diaphragm that caused the contamination of multiple lots,” confided Armour.

UPW pressure regulators are just one of many components used in facilities builds that can significantly degrade fab yield. It is critical to implement a rigorous component testing and qualification process prior to component installation and widespread use. “Don’t take anything for granted,” advised Armour. “Things like UPW regulators have a first-order impact upon yield and they need to be characterized carefully, especially during new fab construction and fit up.”

Photoresist filtration

Photoresist filtration has always been important to ensure high yield in manufacturing, but it has become ultra-critical for lithography at the 20nm node and below. Dependable filtration is particularly important because industry lacks in-line monitoring technology capable of detecting particles in the range below ~40nm.

Micron tried using filters with 50nm pore diameters for a 20nm node process…and saw excessive yield losses along with extreme yield variability. “We characterized pressure-drop as a function of flow-rate, and looked at various filter performances for both 20nm and 40nm particles,” explained Armour. “We implemented a new filter, and lo and behold saw a step function increase in our yields. Defect densities dropped dramatically.” Tracking the yields over time showed that the variability was significantly reduced around the higher yield-entitlement level.

Airborne Molecular Contamination (AMC)

Airborne Molecular Contamination (AMC) is ‘public enemy number one’ in 20nm-node and below fabs around the world. “In one case there were forrest fires in Sumatra and the smoke was going into the atmosphere and actually went into our air intakes in a high volume fab in Taiwan thousands of miles away, and we saw a spike in hydrogen-sulfide,” confided Armour. “It increased our copper CMP defects, due to copper migration. After we installed higher-quality AMC filters for the make-up air units we saw dramatic improvement in copper defects. So what is most important is that you have real-time on-line monitoring of AMC levels.”

Building collaborative relationships with vendors is critical for troubleshooting component issues and improving component quality. “Partnering with suppliers like Entegris is absolutely essential,” continued Armour. “On AMCs for example, we have had a very close partnership that developed out of a team working together at our Inotera fab in Taiwan. There are thousands of important technologies that we need to leverage now to guarantee high yields in leading-node fabs.” The Figure shows just some of the AMCs that must be monitored in real-time.

Big Data

The only way to manage all of this complexity is with “Big Data” and in addition to primary process parameter that must be tracked there are many essential facilities inputs to analytics:

  • Environmental Parameters – temperature, humidity, pressure, particle count, AMCs, etc.
  • Equipment Parameters – run state, motor current, vibration, valve position, etc.
  • Effluent Parameters – cooling water, vacuum, UPW, chemicals, slurries, gases, etc.

“Conventional wisdom is that process tools create 90% of your defect density loss, but that’s changing toward facilities now,” said Armour. “So why not apply the same methodologies within facilities that we do in the fab?” SPC is after-the-fact reactive, while APC is real-time fault detection on input variables, including such parameters as vibration or flow-rate of a pump.

“Never enough data,” enthused Armour. “In terms of monitoring input variables, we do this through the PLCs and basically use SCADA to do the fault-detection interdiction on the critical input variables. This has been proven to be highly effective, providing a lot of protection, and letting me sleep better at night.”

Micron also uses these data to provide site-to-site comparisons. “We basically drive our laggard sites to meet our world-class sites in terms of reducing variation on facility input variables,” explained Armour. “We’re improving our forecasting as a result of this capability, and ultimately protecting our fab yields. Again, the last thing a fab manager wants to see is facilities causing yield loss and variation.”


CMOS-Photonics Technology Challenges

Friday, July 8th, 2016


By Ed Korczynski, Sr. Technical Editor

Fig 1

While it is very easy to talk about the potential advantages of CMOS-photonic integration, the design and manufacturing of commercially competitive products has been extraordinarily difficult. It has been well-known that the cost efficiencies of silicon wafers and CMOS fab processes could theoretically be leveraged to create low-cost photonic circuitry. However, the physics of optics is quite different from the physics of electronics, and so there have been unexpected challenges in moving R&D experiments to HVM products. During the Imec Technology Forum in Brussels held this May, Joris Van Campenhout, imec program director for Optical I/O (Fig. 1) sat down with Solid State Technology to discuss recent progress and future plans.

Data centers—also known as “The Cloud”—continue to grow along with associated power-consumptions, so there are strong motivations to find cost-effective ways to replace more of the electrical switches with lower-power optical circuits. Optical connections in modern data centers do not all have the same specifications, with a clear hierarchy based on the 3D grid-like layout of rows of rack-mounted Printed Circuit Boards (PCB). The table shows the basic differences in physical scale and switching speeds required at different levels within the hierarchy.

Data centers—also known as “The Cloud”—continue to grow along with associated power-consumptions, so there are strong motivations to find cost-effective ways to replace more of the electrical switches with lower-power optical circuits. Optical connections in modern data centers do not all have the same specifications, with a clear hierarchy based on the 3D grid-like layout of rows of rack-mounted Printed Circuit Boards (PCB). The table shows the basic differences in physical scale and switching speeds required at different levels within the hierarchy.

DISTANCE 5-500m 0.5-3m 5-50cm 1-50mm
RELATIVE COST $$$$ $$$ $$ $
POWER/Gbps 5mW 1mW 0.5mW 0.1mW

Rack fiberoptic lines connecting the rows of rack-mounted printed-circuit boards (PCB) in data centers represent a major portion of the total investments for capital equipment, so there is a roadmap to keep the same fibers in place while upgrading the speeds of photonic transmit and receive components over time:

40GHz was standard through 2015,

100GHz upgrades in 2016,

400GHz planned by 2019, and

1THz estimated by 2022.

Some companies have tried to develop multi-mode fiber solutions, but imec is working on single-mode. The telecommunications standard for single-mode optical fiber diameter is 9 microns, while multimode today can be up to 50 microns diameter. “Fundamentally single-mode will be the most integrate-able way to try to get that fiber on to a chip,” explained Van Campenhout. “It is difficult enough to get nine micron diameter fibers to couple to sub-micron waveguides on chip.”

Backplane is the PCB-to-PCB connection within one rack, that today uses copper connections running at up to 50 GHz. Imec sees backplane applications as a possible insertion point for CMOS-Photonics, because there are approximately 10X the number of connections compared to rack applications and because the relative cost target calls for new technologies. Imec’s approach uses 56G silicon ring-modulators to shift wavelengths by 0.1% at very low power, knowingly taking on control issues with non-linearity, and high temperature sensitivity. “We’re confident that it can be done,” stated Van Campenhout, “but the question remains if the overhead can be reduced so that the costs are competitive.” The overhead includes the possible need for on-chip thin-film heaters/coolers to be able to control the temperature.

PCB level connections are being pushed by the Consortium for On-Board Optics (COBO), an industry group working to develop a series of specifications to permit the use of board-mounted optical modules in the manufacturing of networked equipment (i.e. switches, servers, etc.). The organization plans to reference industry specifications where possible and develop specifications where required with attention to electrical interfaces, pin-outs, connectors, thermals, etc. for the development of interchangeable and interoperable optical modules that can be mounted onto motherboards and daughtercards.

Luxtera is the commercial market leader for CMOS-Photonic chips used at the Rack level today, and uses ‘active alignment’ meaning that the fiber has to be lit with the laser and then aligning to the waveguides during test and during assembly. Luxtera is fabless and uses Freescale as foundry to build the chip in an established CMOS SOI process flow originally established for high performance microprocessors. The company produces 10G chips today for advanced Ethernet connections, and through a partnership with Molex ships 40G Active Optical Cables.

Chip level optical connections require breakthrough technologies such as indium-phosphide epitaxy on silicon to be able to grow the most efficient electrically-controlled optical switches, instead of having to pick-and-place discrete components aligned with waveguides. Alignment of components is a huge issue for manufacturing and test that adds inherent costs. “The main issue is getting the coupling from the chip to the fiber with low losses, since sub-micron alignment is needed to avoid a 1 dB loss,” summarized Van Campenhout.

Figure 2 shows a simplified functional schematic of a high-capacity optical communications links employing Dense Wavelength Division Multiplexing (DWDM) to combine modulated laser beams of different colors on a single-mode fiber. Luxtera is working on DWDM for increased bandwidth as is imec.

FIGURE 2: Dense Wavelength Division Multiplexing (DWDM) scheme allows multiplication of the total single-mode fiber (SMF) bandwidth by the number of laser colors used. (Source: imec)

Difficult Design

“If you have just a 1 nm variation in the waveguide width, that device’s spectral response will be proportional as a rule of thumb,” explained Van Campenhout. “We can tune for that with a heating element, but then we lose the low-power advantage.” This results in a need for different design-for-manufacturing approaches.

“When we do photonics design we have to have round features or the light will scatter. So when we do mask making we have to use different rules, and we need to educate all of our partners that we are doing photonics,” reminded Van Campenhout. “However there are EDA companies that are becoming aware of these aspect, so things are developing nicely to create a whole ecosystem to be able to build these. We have the first version of a PDK that we use for multi-product-wafer runs, so we can deliver custom chips to partners.”

Mentor Graphics is an imec partner, and the company’s Tom Daspit, marketing manager for Pyxis Design Tools, spoke with Solid State Technology about the special challenges of EDA for photonics. “You’ve now jumped off the cliff of the orthogonal design environment. Light doesn’t bend at 45° let alone 90°. On an IC it’s all orthogonal, while if it’s photonic we have to modify the interconnect so that the final design is a nice curved one.” To produce a smooth curve the EDA tools must fracture it into a small grid for the photomask, so a seemingly simple set of curves can require gigabytes in a final GDSII file.

It was about 4 years ago that some customers began asking Mentor to modify tools to be able to support photonics, and today there are customers large and small, and some are in full volume production for communications applications. “Remember when they building the old Cray supercomputers and they had to account for all wire lengths to handle signal delays, well now with photonics we need to account for waveguide lengths,” commented Daspit.

In full volume products today are likely communications chips. Customers do not typically share product plans, so not sure of applications spaces. Everybody wants to get rid of the Cu in the backpane to eliminate power consumption, but:

“The big application is photonics for sensor integration, with universities leading the way. Medical is a huge new market,” explained Daspit. “The CMOS die could be 130- down to 65nm or maybe 28nm-nm for some digital.” So there are a wide variety of future applications for CMOS-Photonics, and despite the known manufacturing challenges there are already commercial applications in communications.


Closed-Loop DFM Solution Accelerates Yield Ramps

Monday, June 6th, 2016


Mentor Graphics Corp. announced that Samsung Foundry’s closed-Loop design-for-manufacturing (DFM) solution uses production Mentor Calibre and Tessent platforms to accelerate customer yield ramps.

In the Closed-Loop DFM flows, Samsung integrates its DFM kits with its testing and manufacturing expertise to identify integrated circuit design patterns that are most likely to impact manufacturing yield, thereby helping customers improve design quality, yield, and ramp to production.

“We can detect the risks in customer products and prevent them,” said K.K. (Kuang-Kuo) Lin, Director, Foundry Marketing Ecosystem, Samsung Semiconductor. “We have seen yield gain of up to 8.5%. In terms of the post-manufacturing yield analysis, we have seen the benefits of around 2%. These numbers are not guaranteed because each product is different, but from our experience, these are the numbers we have seen.”

The Samsung solution extracts customer yield-averse design patterns, feeds that information forward to optimize manufacturing and testing, and closes the loop with feedback from silicon results for product design and yield improvement. This solution is not only useful to initial customer designs, but it also allows learning from current production designs to be applied to next-generation designs from that same customer across entire product families.

As shown in Figure 1, Samsung’s foundry offerings cover the needs of devices, ranging from the IoT to consumer, mobile computing, high end computing to automotive. The company, which first got into the foundry business in 2005, claims to be the first foundry to have high-k metal gates in production (in 2011), the first foundry to offer FinFET risk production (in 2013) and the first foundry to tape out a 10nm product. “We are also at the forefront of 7nm. We call it 7LPP, which will be based on EUV,” he added.

Figure 1

With the end goal of rapid yield ramp for new production introduction, Samsung turned to Mentor Graphics tools for pre-production DFM, which it calls PRISM (pattern recognition and identity scoring methods), which runs on Mentor’s Calibre platform. For this pre-production phase, “we provide very comprehensive process-aware DFM sign-off kits and optimization flow for the designers so they can double-check and verify, prevent any DFM issues during the design phase,” Lin said.

The other component of closed-loop DFM is in post-manufacturing. Samsung has developed as set of tools called FLARE (Failure analysis And yield Rank Estimation with DFM hotspot database), which runs on Mentor’s Tesset platform.

Figure 2 shows how PRISM and FLARE work together in a closed-loop fashion for pre- and post-production DFM.

Figure 2

“Every design has its idiosyncrasies and its unique signatures because layout designers can be pretty creative,” Lin explained. “We use PRISM to do extensive pattern analysis and then do optimization during the data prep and also use the pattern analysis result to drive in-line inspection.”

Once the wafer is manufactured in the fab, FLARE involves mapping a yield learning database with EDS, (electrical engineering die-sort data). “We’ll combine them to do yield pareto data analysis and also mapping analysis. From those deep learning, we are able to prioritize which part of the fab process we can improve. We can also feedback to the DFM kit which we use in the design phase, which gives the designer feedback on what they can further improve,” Lin said.

At the heard of PRISM is a defect database built from test vehicles and existing products (Figure 3). “We put all the patterns that we know into this defect database,” Lin explained. “We also couple it with some very novel things. We use a layout schematic generator from Mentor to increase the coverage, to enumerate all the possible patterns. And then we also have meta data and simulators to do yield prediction of those known defects from different sources.”

Figure 3

“Once a customer product comes into Samsung foundry, we will check against the known defect database. Then we will do prediction in terms of the process margin and feed-forward this data into the subsequent steps of data prep or retargeting, and in-line inspection so we can prioritize our resources to know what to inspect and what not to in the manufacturing steps,” Lin said (see Figure 4).

Figure 4

“FLARE accelerates the learning in the fab to bring up customer products in our foundry. It helps the customer achieve their time to market. It also saves on fab operation costs, so it’s a win-win situation for everyone,” Lin said.

The Closed-Loop DFM flows are in production use today for customers of Samsung Foundry services. While proven in 14 nm technology, the flows can be used for ICs manufactured with other Samsung process nodes.

At the 2016 Design Automation Conference, Mentor and Samsung are co-hosting a lunch seminar entitled “Accelerate Yield Ramps with Samsung Foundry Closed-Loop DFM and Mentor Tools.” The event is Monday, June 6, from 12:00 to 1:30 PM. Interested customers can register for the event using this registration link.

79 GHz CMOS RADAR Chips for Cars from Imec and Infineon

Tuesday, May 24th, 2016


By Ed Korczynski, Sr. Technical Editor

As unveiled at the annual Imec Technology Forum in Brussels (, Infineon Technologies AG ( and imec ( are working on highly integrated CMOS-based 79 GHz sensor chips for automotive radar applications. Imec provides expertise in high-frequency system, circuit, and antenna design for radar applications, complementing Infineon’s knowledge from the many learnings that go along with holding the world’s top market share in commercial radar sensor chips. Infineon and imec expect functional CMOS sensor chip samples in the third quarter of 2016. A complete radar system demonstrator is scheduled for the beginning of 2017.

Whether or not fully automated cars and trucks will be traveling on roads soon, today’s drivers want more sensors to be able to safely avoid accidents in conditions of limited visibility. Typically, there are up to three radar systems in today’s vehicle equipped with driver assistance functions. In a future with fully automated cars, up to ten radar systems and ten more sensor systems using cameras or lidar ( could be needed. Short-range radar (SRR) would look for side objects, medium-range radar (MRR) would scan widely for objects up to 50m in front and in back, and long-range radar (LRR) would focus up to 250m in front and in back for high-speed collision avoidance.

“Infineon enables the radar-based safety cocoon of the partly and fully automated car,” said Ralf Bornefeld, Vice President & General Manager, Sense & Control, Infineon Technologies AG. “In the future, we will manufacture radar sensor chips as a single-chip solution in a classic CMOS process for applications like automated parking. Infineon will continue to set industry standards in radar technology and quality.”

The Figure shows the evolution of radar technology over the last decades, leading to the current miniaturization using solid-state silicon CMOS. Key to the successful development of this 79 GHz demonstrator was choosing to use 28 nm CMOS technology. Imec has been refining this technology as shown at ISSCC ( for many years, first showing a 28nm transmitter chip in 2013, then showing a 28nm transmit and receive (a.k.a. “transceiver”) chip in 2014, and finally showing a single-chip with a transceiver and analog-digital converters (ADC) and phase-lock loops (PLL) and digital components in 2015. Long-term supply of eventual commercial chips should be ensured by using 28nm technology, which is known as a “long lived” node.

“We are excited to work with Infineon as a valuable partner in our R&D program on advanced CMOS-based 77 GHz and 79 GHz radar technology,” stated Wim Van Thillo, program director perceptive systems at imec. “Compared to the mainstream 24 GHz band, the 77 GHz and 79 GHz bands enable a finer range, Doppler and angular resolution. With these advantages, we aim to realize radar prototypes with integrated multiple-input, multiple-output (MIMO) antennas that not only detect large objects, but also pedestrians and bikers and thus contribute to a safer environment for all.”

Since the aesthetics are always important for buyers, automobile companies have been challenged to integrate all of the desired sensors into vehicles in an invisible manner. “The designers hate what they call the ‘warts’ on car bumpers that are the small holes needed for the ultrasonic sensors currently used,” explained Van Thillo in a press conference during ITF2016.

In an ITF2016 presentation, CEO Reinhard Ploss, discussed how Infineon works with industrial partners to create competitive commercial products. “When we first developed RADAR, there was a collaboration between the Tier-1 car companies and ourselves,” explained Ploss. “The key lies in the algorithms needed to process the data, since the raw data stream is essentially useless. The next generation of differentiation for semiconductors will be how to integrate algorithms. In effect, how do you translate ‘pixels’ into ‘optics’ without an expensive microprocessor?”

Evolution of radar technology over time has reached the miniaturization of 79 GHz using 28nm silicon CMOS technology. Imec is now also working on 140 GHz radar chips. (Source: imec)


Cadence Adds New Tools for Analog Design, Enhances Layout

Wednesday, April 6th, 2016


By Jeff Dorsch, Contributing Editor

Cadence Design Systems today is introducing new tools within its Virtuoso Analog Design Environment (ADE), along with enhancements to the Virtuoso Layout Suite.

New to Virtuoso ADE are the Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier.

“The new Virtuoso ADE Verifier technology and the Virtuoso ADE Assembler technology run plan capability make our design teams more productive,” said Yanqiu Diao, deputy general manager of the Turing Processor business unit at HiSilicon Technologies Co., Ltd. “Through our early use of the new Cadence Virtuoso ADE product suite, we’ve found that we can improve analog IP verification productivity by approximately 30 percent and reduce verification issues by one-half. Our smartphone and network chip projects should benefit from these latest capabilities.”

Steve Lewis, product marketing director for Cadence’s Custom IC & PCB Group, said the electronic design automation company’s Virtuoso ADE L, XL, and GXL tools “will be kept, will be maintained, and taking that technology to the next level.”

Virtuoso ADE Verifier is “the brand-new kid on the block,” Lewis said in an interview. The tool advances analog verification technology, according to Cadence, and offers an integrated dashboard for engineers to employ.

Under international standards for automotive vehicles, medical equipment, military/aerospace systems, and other products, suppliers “have to trace every aspect of your design,” he noted. “All has to be documented.”

The digital side of chip design addressed those issues about a decade ago, according to Lewis. Such recordkeeping and documentation are “far less common on the analog,” he said. “It’s no longer okay to say the analog takes care of itself.”

Changes in analog design projects were typically tracked in spreadsheet programs, which don’t connect to the Virtuoso suite, Lewis noted, adding, “Now, I know who’s working on what.”

The new analog design tools “add a little bit more granularity” with real-number models, Lewis said. “It’s not quite SPICE,” he admitted.

Regarding Virtuoso ADE Assembler, “we made it look like ADE XL,” Lewis said, so users should have a shorter learning curve with the new tool. Virtuoso ADE Explorer provides what Cadence calls a complete corners and Monte Carlo environment for finding and correcting variation problems.

Cadence is also offering a Virtuoso Variation Option, providing fast Monte Carlo analysis for FinFET chips with 16-nanometer or smaller dimensions.

The enhancements in Virtuoso Layout Suite are a 10x to 100x improvement in graphics rendering performance, real-time customization of Module Generators with a simpler and more visual approach; and new structured device-level routing capabilities that are said to enhance routing productivity by up to 50 percent.

“We actually made significant changes in layout for L, XL,” addressing “current techniques, current designs,” Lewis commented.

Cadence Virtuoso Analog Design Environment (ADE): Reimagining analog design with emphasis on usability, performance, and innovation

Goodbye, EDAC; Hello, ESD Alliance

Friday, April 1st, 2016


By Jeff Dorsch, Contributing Editor

The Electronic Design Automation Consortium (EDAC) is no more. The industry organization, founded in 1989, is changing its name to the Electronic System Design Alliance, or ESD Alliance.

The name change is being accompanied by an expansion of the organization’s charter. Having taken on semiconductor intellectual property several years ago, the ESD Alliance will also address advanced packaging and embedded software, according to Robert Smith, who took over last year as executive director of EDAC. The ESD Alliance will also welcome service companies that offer design know-how and resources.

The alliance’s launch was marked by an evening event on Wednesday (March 30) at the SEMI headquarters in San Jose, Calif., where the ESD Alliance has its offices. In attendance at the social gathering were several EDAC directors, including Simon Segars, chief executive officer of ARM Holdings; Wally Rhines, chairman and CEO of Mentor Graphics; Lip-Bu Tan, president and CEO of Cadence Design Systems; and Aart de Geus, chairman and co-CEO of Synopsys.

“We’re part of this large ecosystem,” Bob Smith said Wednesday evening, adding, “Semiconductors – they need design.” He recognized by name many of the people involved in EDAC and now the ESD Alliance.

A slide presentation at the event began with “Kingdom of Rain,” by The The, segueing to “Love Shack” by the B-52’s – two songs dating to 1989, the year EDAC was formed. That also was the year Taylor Swift was born, one slide noted.

In 2016, marked musically by Mark Ronson’s “Uptown Funk” in the slide show, the ESD Alliance is taking the place of the EDA Consortium.

New Materials: A Paradox of the Unknown

Thursday, March 17th, 2016


By Pete Singer, Editor-in-Chief

The semiconductor industry has slowly been implementing a growing array of new materials in an effort to boost speed and performance, reduce power consumption and reduce leakage. From the 1960s through the 1990s, only a handful of materials were used, most notably silicon, silicon oxide, silicon nitride and aluminum. Soon, by 2020, more than 40 different materials will be in high-volume production, including more exotic materials such as hafnium, ruthenium, zirconium, strontium, complex III-Vs (such as InGaAs), cobalt and SiC (Figure 1).

Figure 1

At the same time, semiconductor manufacturing processes are executed at the atomic level. Atomic layer deposition, atomic layer etching and atomic layer epitaxy are now common.

One of the challenges with new materials and atomic-level processing is that new and unexpected reactions can occur due to the trace impurities in the gases used during production. These impurities may be organic materials or trace levels of oxygen, nitrogen or other elements.

Jean-Charles Cigal

Jean-Charles Cigal, market development manager at Linde in Pullach, Germany, said a growing concern is that gases that have the same specification as before suddenly are not working the same way. “There are a lot of impurities that weren’t a problem before. They are now reacting because you have new materials on the wafer,” he said. “Process engineers don’t know what to look at in terms of impurities. That’s the paradox of the unknown.”

To help customers avoid such problems, gas supplier Linde has implemented tools commonly used in the semiconductor industry, including statistical process control (SPC), statistical quality control (SQC) and a lab information management system (LIMS). “The advantage of having this statistical process strategy is the ability to more rapidly correct any quality issue,” Cigal said.

A “fingerprinting” strategy also comes into play. “We’re using broad spectrum analyzers to get a lot of data and check everything possible. We want to do detection and correction of any quality issue before it reaches the fab,” Cigal said. If an unexpected quality issue is later identified at the fab, Linde can step in with forensic analysis using a database of information.

It is not cost-effective to simply specify higher and higher levels of purity. Instead, Cigal says targeted specifications are now the norm. “In the past, people were asking for the highest purity. Give me a 7.0 silane. Now they are saying OK, give me a silane with 5.0 but I don’t want this organic material,” he said. Linde’s HiQ portfolio offers more than 100 different pure gases such as HiQ Nitrogen 5.0 and HiQ Argon 6.0. Purity is commonly expressed as a two digit number. For example, Helium with a purity of 99.9996% would be described as HiQ Helium 5.6 with the 5 representing the number of nines, while the 6 represents the first digit following the nines.

“What we want ultimately is to get a full picture of what is inside (the gas) and to make the customer aware,” Cigal said. “We don’t know everything about the customers’ processes, but Linde is building large database that will help electronics manufacturers identify what impurities might react in certain processes.”

Customers are now asking for specifications just under the detection limits. We are continuously acquiring analytical tools that will help them to better understand the composition of their materials, which ultimately helps to improve their manufacturing yield.

The semiconductor industry demands very high-purity materials and yet electronics materials suppliers often receive raw materials of very low quality. To ensure that customers get the high-quality materials they require, Linde takes on the responsibility of being the quality gate keeper and controls the whole supply chain – from the source, through purification, and transportation.

Editor’s Note: Jean-Charles Cigal is currently Market Development Manager at Linde Electronics. In his role, Jean-Charles supports electronics customers and equipment manufacturers to achieve their roadmap with the introduction of new processes and materials. He joined Linde as principal technologist in 2009, where he was technology consultant for the semiconductor and the photovoltaic industry.  Prior to joining the Linde Group, Jean-Charles worked several years as senior process engineer in the semiconductor industry. He owns a M.Sc. in Applied Physics from Pierre et Marie Curie University, Paris, France, and a PhD in Applied Physics from Eindhoven University of Technology, the Netherlands.

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