Part of the  

Solid State Technology


The Confab


About  |  Contact

Posts Tagged ‘SST Top Story Right’

Next Page »

Silicon Photonics Technology Developments

Thursday, April 6th, 2017


By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.


SiPs Simplify Wireless IoT Design

Thursday, February 16th, 2017


By Dave Lammers, Contributing Editor

It takes a range of skills to create a successful business in the Internet of Things space, where chips sell for a few dollars and competition is intense. Circuit design and software support for multiple wireless standards must combine with manufacturing capabilities.

Daniel Cooley, senior vice president of IoT products at Silicon Labs

Daniel Cooley, senior vice president and general manager of IoT products at Silicon Labs (Austin, Tx.), said three trends are impacting the manufacture of IoT end-node devices, which usually combine an MCU, an RF transceiver, and embedded flash memory.

“There is an explosion in the amount of memory on embedded SoCs, both RAM and non-volatile memory,” said Cooley. Today’s multi-protocol wireless software stacks, graphics processing, and security requirements routinely double or quadruple the memory sizes of the past.

Secondly, while IoT edge devices continue to use trailing-edge technologies, nonetheless they also are moving to more advanced nodes. However, that movement is partially gated by the availability of embedded flash.

Thirdly, pre-certified system-in-package (SiP) solutions, running a proven software stack, “are becoming much more important,” Cooley said. These SiPs typically encapsulate an MCU, an integrated antenna and shielding, power management, crystal oscillators, and inductors and capacitors. While Silicon Labs has been shipping multi-chip modules for many years, SiPs are gaining favor in part because they can be quickly deployed by engineers with relatively little expertise in wireless development, he said.

“Personally, I believe that very advanced SIPs increasingly will be standard products, not anything exotic. They are a complete solution, like a PCB module, but encased with a molding compound. The SiP manufacturers are becoming very sophisticated, and we are ready to take that technology and apply it more broadly,” he said.

For example, Silicon Labs recently introduced a Bluetooth SiP module measuring 6.5 by 6.5 mm, designed for use in sports and fitness wearables, smartwatches, personal medical devices, wireless sensor nodes, and other space-constrained connected devices.

“We have built multi-chip packages – those go back to the first products of the company – but we haven’t done a fully certified module with a built-in antenna until now. A SiP module simplifies the go-to-market process. Customers can just put it down on a PCB and connect power and ground. Of course, they can attach other chips with the built-in interfaces, but they don’t need anything else to make the Bluetooth system work,” Cooley said.

“Designing with a certified SiP module supports better data throughput, and improves reliability as well. The SiP approach is especially beneficial for end-node customers which “haven’t gone through the process of launching a wireless product in in the market,” Cooley said.

System-in-package (SiP) solutions ease the design cycle for engineers using Bluetooth and low low-energy wireless networks. (Source: Silicon Laboratories).

The SiP packages a wireless SoC with an antenna and multiple other components in a small footprint.

Control by voice

The BGM12x Blue Gecko SiP is aimed at Bluetooth-enabled applications, a genre that is rapidly expanding as ecosystems like the Amazon Echo, Apple HomeKit, and Google Home proliferate.

The BGM12x Blue Gecko SiP is aimed at Bluetooth-enabled applications

Matt Maupin is Silicon Labs’ product marketing manager for mesh networking products, which includes SoCs and modules for low-power Zigbee and Thread wireless connectivity. Asked how a home lighting system, for example, might be connected to one of the home “ecosystems” now being sold by Amazon, Apple, Google, Nest, and others, Maupin said the major lighting suppliers, such as OSRAM, Philips, and others, often use Zigbee for lighting, rather than Bluetooth, because of Zigbee’s mesh networking capability. (Some manufactures use Bluetooth low energy (BLE) for point-to-point control from a phone.)

“The ability for a device to connect directly relies on the same protocols being used. Google and Amazon products do not support Zigbee or Thread connectivity at this time,” Maupin explained.

Normally, these lighting devices are connected to a hub. For example, Amazon’s Echo and Google’s Home “both control the Philips lights through the Philips hub. Communication happens over the Ethernet network (wireless or wired depending on the hub).  The Philips hub also supports HomeKit so that will work as well,” he said.

Maupin’s home configuration is set up so the Philips lights connect via Zigbee to the Philips hub, which connects to an Ethernet network. An Amazon Echo is connected to the Ethernet Network by WiFi.

“I have the Philips devices at home configured via their app. For example, I have lights in my bedroom configured differently for me and my wife. With voice commands, I can control these lamps with different commands such as ‘Alexa, turn off Matt’s lamp,’ or ‘Alexa, turn off the bedroom lamps.’”

Alexa communicates wirelessly to the Ethernet Network, which then goes to the Philips hub (which is sold under the brand name Philips Hue Bridge) via Ethernet, where the Philips hub then converts that to Zigbee to control that actual lamps. While that sounds complicated, Maupin said, “to consumers, it is just magic.”

A divided IoT market

Sandeep Kumar, senior vice president of worldwide operations

IoT systems can be divided into the high-performance number crunchers which deal with massive amounts of data, and the “end-node” products which drive a much different set of requirements. Sandeep Kumar, senior vice president of worldwide operations at Silicon Labs, said RF, ultra-low-power processes and embedded NVM are essential for many end-node applications, and it can take several years for foundries to develop them beyond the base technology becoming available.

“40nm is an old technology node for the big digital companies. For IoT end nodes where we need a cost-effective RF process with ultra-low leakage and embedded NVM, the state of the art is 55nm; 40 nm is just getting ready,” Kumar said.

Embedded flash or any NVM takes as long as it does because, most often, it is developed not by the foundries themselves but by independent companies, such as Silicon Storage Technology. The foundry will implement this IP after the foundry has developed the base process. (SST has been part of Microchip Technology since 2010.) Typically, the eFlash capability lags by a few years for high-volume uses, and Kumar notes that “the 40nm eFlash is still not in high-volume production for end-node devices.”

Similarly, the ultra-low-leakage versions of a technology node take time and equipment investments, as well as cooperation from IP partners. Foundry customers and the fabless design houses must requalify for the low-leakage processes. “All the models change and simulations have to be redone,” Kumar said.

“We need low-leakage for the end applications that run on a button cell (battery), so that a security door or motion sensor, for example, can run for five to seven years. After the base technology is developed, it typically takes at least three years. If 40nm was available several years ago, the ultra-low-leakage process is just becoming available now.

“And some foundries may decide not to do ultra-low-leakage on certain technology nodes. It is a big capital and R&D investment to do ultra-low-leakage. Foundries have to make choices, and we have to manage that,” Kumar said.

The majority of Silicon Labs’ IoT product volume is in 180nm, while other non-IoT products use a 55nm process. The line of Blue Gecko wireless SoCs currently is on 90nm, made in 300mm fabs, while new designs are headed toward more advanced process nodes.

Because 180nm fabs are being used for MEMS, sensors and other analog-intensive, high-volume products, there is still “somewhat of a shortage” of 180nm wafers, Kumar said, though the situation is improving. “It has gotten better because TSMC and other foundries have added capacity, having heard from several customers that the 180nm node is where they are going to stay, or at least stay longer than they expected. While the foundries have added equipment and capital, it is still quite tight. I am sure the big MEMS and sensor companies are perfectly happy with 180nm,” Kumar said.

A testing advantage

IoT is a broad-based market with thousands of customers and a lot of small volume customizations. Over the past decade Silicon Labs has deployed a proprietary ultra-low-cost tester, developed in-house and used in internal back-end operations in Austin and Singapore at assembly and test subcontractors and at a few outside module makers as well. The Silicon Labs tester is much more cost effective than commercially available testers, an important cost advantage in a market where a wireless MCU can sell in small volumes to a large number of customers for just a few dollars.

“Testing adds costs, and it is a critical part of our strategy. We use our internally developed tester for our broad-based products, and it is effective at managing costs,” Kumar said.

High-NA EUV Lithography Investment

Monday, November 28th, 2016


By Ed Korczynski, Sr. Technical Editor

As covered in a recent press release, leading lithography OEM ASML invested EUR 1 billion in cash to buy 24.9% of ZEISS subsidiary Carl Zeiss SMT, and committed to spend EUR ~760 million over the next 6 years on capital expenditures and R&D of an entirely new high numerical aperture (NA) extreme ultra-violet (EUV) lithography tool. Targeting NA >0.5 to be able to print 8 nm half-pitch features, the planned tool will use anamorphic mirrors to reduce shadowing effects from nanometer-scale mask patterns. Clever design and engineering of the mirrors could allow this new NA >0.5 tool to be able to achieve wafer throughputs similar to ASML’s current generation of 0.33 NA tools for the same source power and resist speed.

The Numerical Aperture (NA) of an optical system is a dimensionless number that characterizes the range of angles over which the system can accept or emit light. Higher NA systems can resolve finer features by condensing light from a wider range of angles. Mirror surfaces to reflect EUV “light” are made from over 50 atomic-scale bi-layers of molybdenum (Mo) and silicon (Si), and increasing the width of mirrors to reach higher NA increases the angular spread of the light which results in shadows within patterns.

In the proceedings of last year’s European Mask and Lithography Conference, Zeiss researchers reported on  “Anamorphic high NA optics enabling EUV lithography with sub 8 nm resolution” (doi:10.1117/12.2196393). The abstract summarizes the inherent challenges of establishing high NA EUVL technology:

For such a high-NA optics a configuration of 4x magnification, full field size of 26 x 33 mm² and 6’’ mask is not feasible anymore. The increased chief ray angle and higher NA at reticle lead to non-acceptable mask shadowing effects. These shadowing effects can only be controlled by increasing the magnification, hence reducing the system productivity or demanding larger mask sizes. We demonstrate that the best compromise in imaging, productivity and field split is a so-called anamorphic magnification and a half field of 26 x 16.5 mm² but utilizing existing 6’’ mask infrastructure.

Figure 1 shows that ASML plans to introduce such a system after the year 2020, with a throughput of 185 wafers-per-hour (wph) and with overlay of <2 nm. Hans Meiling, ASML vice president of product management EUV, in an exclusive interview with Solid State Technology explained why >0.5 NA capability will not be upgradable on 0.33 NA tools, “the >0.5NA optical path is larger and will require a new platform. The anamorphic imaging will also require stage architectural changes.”

Fig.1: EUVL stepper product plans for wafers per hour (WPH) and overlay accuracy include change from 0.33 NA to a new >0.5 NA platform. (Source: ASML)

Overlay of <2 nm will be critical when patterning 8nm half-pitch features, particularly when stitching lines together between half-fields patterned by single-exposures of EUV. Minimal overlay is also needed for EUV to be used to cut grid lines that are initially formed by pitch-splitting ArFi. In addition to the high NA set of mirrors, engineers will have to improve many parts of the stepper to be able to improve on the 3 nm overlay capability promised for the NXE:3400B 0.33 NA tool ASML plans to ship next year.

“Achieving better overlay requires improvements in wafer and reticle stages regardless of NA,” explained Meiling. “The optics are one of the many components that contribute to overlay. Compare to ArF immersion lithography, where the optics NA has been at 1.35 for several generations but platform improvements have provided significant overlay improvements.”

Manufacturing Capability Plans

Figure 2 shows that anamorphic systems require anamorphic masks, so moving from 0.33 to >0.5 NA requires re-designed masks. For relatively large chips, two adjacent exposures with two different anamorphic masks will be needed to pattern the same field area which could be imaged with lower resolution by a single 0.33 NA exposure. Obviously, such adjacent exposures of one layer must be properly “stitched” together by design, which is another constraint on electronic design automation (EDA) software.

Fig.2: Anamorphic >0.5 NA EUVL system planned by ASML and Zeiss will magnify mask images by 4x in the x-direction and 8x in the y-direction. (Source: Carl Zeiss SMT)

Though large chips will require twice as many half-field masks, use of anamorphic imaging somewhat reduces the challenges of mask-making. Meiling reminds us that, “With the anamorphic imaging, the 8X direction conditions will actually relax, while the 4X direction will require incremental improvements such as have always been required node-on-node.”

ASML and Zeiss report that ideal holes which “obscure” the centers of mirrors can surprisingly allow for increased transmission of EUV by each mirror, up to twice that of the “unobscured” mirrors in the 0.33 NA tool. The holes allow the mirrors to reflect through each-other, so they all line up and reflect better. Theoretically then each >0.5 NA half-field can be exposed twice as fast as a 0.33 NA full-field, though it seems that some system throughput loss will be inevitable. Twice the number of steps across the wafer will have to slow down throughput by some percent.

White two stitched side-by-side >0.5 NA EUVL exposures will be challenging, the generally known alternatives seem likely to provide only lower throughputs and lower yields:

*   Double-exposure of full-field using 0.33 NA EUVL,

*   Octuple-exposure of full-field using ArFi, or

*   Quadruple-exposure of full-field using ArFi complemented by e-beam direct-writing (EbDW) or by directed self-assembly (DSA).

One ASML EUVL system for HVM is expected to cost ~US$100 million. As presented at the company’s October 31st Investor Day this year, ASML’s modeling indicates that a leading-edge logic fab running ~45k wafer starts per month (WSPM) would need to purchase 7-12 EUV systems to handle an anticipated 6-10 EUV layers within “7nm-node” designs. Assuming that each tool will cost >US$100 million, a leading logic fab would have to invest ~US$1 billion to be able to use EUV for critical lithography layers.

With near US$1 billion in capital investments needed to begin using EUVL, HVM fabs want to be able to get productive value out of the tools over more than a single IC product generation. If a logic fab invests US$1 billion to use 0.33 NA EUVL for the “7nm-node” there is risk that those tools will be unproductive for “5nm-node” designs expected a few years later. Some fabs may choose to push ArFi multi-patterning complemented by another lithography technology for a few years, and delay investment in EUVL until >0.5 NA tools become available.


Air-Gaps for FinFETs Shown at IEDM

Friday, October 28th, 2016


By Ed Korczynski, Sr. Technical Editor

Researchers from IBM and Globalfoundries will report on the first use of “air-gaps” as part of the dielectric insulation around active gates of “10nm-node” finFETs at the upcoming International Electron Devices Meeting (IEDM) of the IEEE ( Happening in San Francisco in early December, IEDM 2016 will again provide a forum for the world’s leading R&D teams to show off their latest-greatest devices, including 7nm-node finFETs by IBM/Globalfoundries/Samsung and by TSMC. Air-gaps reduce the dielectric capacitance that slows down ICs, so their integration into transistor structures leads to faster logic chips.

History of Airgaps – ILD and IPD

As this editor recently covered at SemiMD, in 1998, Ben Shieh—then a researcher at Stanford University and now a foundry interface for Apple Corp.—first published (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) on the use of controlled pitch design combined with CVD dielectrics to form “pinched-off keyholes” in cross-sections of inter-layer dielectrics (ILD).

In 2007, IBM researchers showed a way to use sacrificial dielectric layers as part of a subtractive process that allows air-gaps to be integrated into any existing dielectric structure. In an interview with this editor at that time, IBM Fellow Dan Edelstein explained, “we use lithography to etch a narrow channel down so it will cap off, then deliberated damage the dielectric and etch so it looks like a balloon. We get a big gap with a drop in capacitance and then a small slot that gets pinched off.

Intel presented on their integration of air-gaps into on-chip interconnects at IITC in 2010 but delayed use until the company’s 14nm-node reached production in 2014. 2D-NAND fabs have been using air-gaps as part of the inter-poly dielectric (IPD) for many years, so there is precedent for integration near the gate-stack.

Airgaps for finFETs

Now researchers from IBM and Globalfoundries will report in (IEDM Paper #17.1, “Air Spacer for 10nm FinFET CMOS and Beyond,” K. Cheng et al) on the first air-gaps used at the transistor level in logic. Figure 1 shows that for these “10nm-node” finFETs the dielectric spacing—including the air-gap and both sides of the dielectric liner—is about 10 nm. The liner needs to be ~2nm thin so that ~1nm of ultra-low-k sacrificial dielectric remains on either side of the ~5nm air-gap.

Fig.1: Schematic of partial air-gaps only above fin tops using dielectric liners to protect gate stacks during air-gap formation for 10nm finFET CMOS and beyond. (source: IEDM 2016, Paper#17.1, Fig.12)

These air-gaps reduced capacitance at the transistor level by as much as 25%, and in a ring oscillator test circuit by as much as 15%. The researchers say a partial integration scheme—where the air-gaps are formed only above the tops of fin— minimizes damage to the FinFET, as does the high-selectivity etching process used to fabricate them.

Figure 2 shows a cross-section transmission electron micrograph (TEM) of what can go wrong with etch-back air-gaps when all of the processes are not properly controlled. Because there are inherent process:design interactions needed to form repeatable air-gaps of desired shapes, this integration scheme should be extendable “beyond” the “10-nm node” to finFETs formed at tighter pitches. However, it seems likely that “5nm-node” logic FETs will use arrays of horizontal silicon nano-wires (NW), for which more complex air-gap integration schemes would seem to be needed.

Fig.2: TEM image of FinFET transistor damage—specifically, erosion of the fin and source-drain epitaxy—by improper etch-back of the air-gaps at 10nm dimensions. (source: IEDM 2016, Paper#17.1, Fig.10)


Has SOI’s Turn Come Around Again?

Monday, October 10th, 2016


By David Lammers, Contributing Editor

When analyst Linley Gwennap is asked about the chances that fully-depleted silicon-on-insulator (FD-SOI) technology will make it in the marketplace, he gives a short history lesson.

First, he makes clear that the discussion is not about “the older SOI,” – the partially depleted SOI that required designers to deal with the so-called “kink effect.” The FD-SOI being offered by STMicroelectronics and Samsung at 28nm design rules, and by GlobalFoundries at 22nm and 12nm, is a different animal: a fully depleted channel, new IP libraries, and no kink effect.

Bulk planar CMOS transistor scaling came to an end at 28nm, and leading-edge companies such as Intel, TSMC, Samsung, and GlobalFoundries moved into the finFET realm for performance-driven products, said Gwennap, founder of The Linley Group (Mountain View, Calif.) and publisher of The Microprocessor Report, said,

While FD-SOI at the 28nm node was offered by STMicrelectronics, with Samsung coming in as a second source, Gwennap said 28nm FD-SOI was not differentiated enough from 28nm bulk CMOS to justify the extra design and wafer costs. “When STMicro came out with 28 FD, it was more expensive than bulk CMOS, so the value proposition was not that great.”

NXP uses 28nm FD-SOI for its iMX 7 and iMX 8 processors, but relatively few other companies did 28nm FD-SOI designs. That may change as 22nm FD-SOI offers a boost in transistor density, and a roadmap to tighter design rules.

“For planar CMOS, Moore’s Law came to a dead end at 28nm. Some companies have looked at finFETs and decided that the cost barrier is just too high. They don’t have anywhere to go; for a few years now those companies have been at 28nm, they can’t justify the move on to finFETs, and they need to figure out how they can offer something new to their customers. For those companies, taking a risk on FD-SOI is starting to look like a good idea,” he said.

A cautious view

Joanne Itow, foundry analyst at Semico Research (Phoenix), also has been observing the ups and downs of SOI technology over the last two decades. The end of the early heyday, marked by PD-SOI-based products from IBM, Advanced Micro Devices, Freescale Semiconductor, and several game system vendors, has led Itow to take a cautious, Show-Me attitude.

“The SOI proponents always said, ‘this is the breakout node,’ but then it didn’t happen. Now, they are saying the Fmax has better results than finFETs, and while we do see some promising results, I’m not sure everybody knows what to do with it. And there may be bottlenecks,” such as the design tools and IP cores.

Itow said she has talked to more companies that are looking at FD-SOI, and some of them have teams designing products. “So we are seeing more serious activity than before,” Itow said. “I don’t see it being the main Qualcomm process for high-volume products like the applications processors in smartphones. But I do see it being looked at for IoT applications that will come on line in a couple of years. And these things always seem to take longer than you think,” she said.

Sony Corp. has publicly discussed a GPS IC based on 28nm FD-SOI that is being deployed in a smartwatch sold by Huami, a Chinese brand, which is touting the long battery life of the watch when the GPS function is turned on.

GlobalFoundries claims it has more than 50 companies in various stages of development on its 22FDX process, which enters risk production early next year, and the company plans a 12nm FDX offering in several years.

IP libraries put together

The availability of design libraries – both foundation IP and complex cores – is an issue facing FD-SOI. Gwennap said GlobalFoundries has worked with EDA partners, and invested in an IP development company, Invecas, to develop an IP library for its FDX technology. “Even though GlobalFoundries is basically starting from scratch in terms of putting together an IP library, it doesn’t take that long to put together the basic IP, such as the interface cells, that their customers need.

“There is definitely going to be an unusual thing that probably will not be in the existing library, something that either GlobalFoundries or the customers will have to put together. Over time, I believe that the IP portfolio will get built out,” Gwennap said.

The salaries paid to design engineers in Asia tend to be less than half of what U.S.-based designers are paid, he noted. That may open up companies “with a lower cost engineering team” in India, China, Taiwan, and elsewhere to “go off in a different direction” and experiment with FD-SOI, Gwennap said.

Philippe Flatresses, a design architect at STMicro, said with the existing FDSOI ecosystem it is possible to design a complete SoC, including processor cores from ARM Ltd., high speed interfaces, USB, MIPI, memory controllers, and other IP from third-party providers including Synopsys and Cadence. Looking at the FD-SOI roadmap, several technology derivatives are under development to address the RF, ultra-low voltage, and other markets. Flatresses said there is a need to extend the IP ecosystem in those areas.

Wafer costs not a big factor

There was a time when the approximately $500 cost for an SOI wafer from Soitec (Grenoble, France) tipped the scales away from SOI technology for some cost-sensitive applications. Gwennap said when a fully processed 28nm planar CMOS wafer cost about $3,000 from a major foundry, that $500 SOI wafer cost presented a stumbling block to some companies considering FD-SOI.

Now, however, a fully-processed finFET wafer costs $7,000 or more from the major foundries, Gwennap said, and the cost of the SOI wafer is a much smaller fraction of the total cost equation. When companies compare planar FD-SOI to finFETs, that $500 wafer cost, Gwennap said, “just isn’t as important as it used to be. And some of the other advantages in terms of cost savings or power savings are pretty attractive in markets where cost is important, such as consumer and IoT products. They present a good chance to get some key design wins.”

Soitec claims it can ramp up to 1.5 million FD-SOI wafers a year with its existing facility in 18 months, and has the ability to expand to 3 million wafers if market demand expands.

Jamie Schaeffer, the FDX program manager at GlobalFoundries, acknowledges that the SOI wafers are three to four times more expensive than bulk silicon wafers. Schaeffer said a more important cost factor is in the mask set. A 22FDX chip with eight metal layers can be constructed with “just 39 mask layers, compared with 60 for a finFET design at comparable performance levels.” And no double patterning is required for the 22FDX transistors.

Technology advantages claimed

Soitec senior fellow Bich-Yen Nguyen, who spent much of her career at Freescale Semiconductor in technology development, claims several technical advantages for FD-SOI.

FD-SOI has a high transconductance-to-drain current ratio, is superior in terms of the short channel effect, and has a lower fringing and effective capacitance and lower gate resistance, due partly to a gate-first process approach to the high-k/metal gate steps, Nguyen said.

Back and forward biasing is another unique feature of FD-SOI. “When you apply body-bias, the fT and fmax curves shift to a lower Vt.  This is an additional benefit allowing the RF designer to achieve higher fT and fmax at much lower gate voltage (Vg) over a wider Vg range.  That is a huge benefit for the RF designer,” she said. Figure 1 illustrates the unique benefit of back-bias.

Figure 1. The unique benefit of back-bias is illustrated. Source: GlobalFoundries.

“To get the full benefit of body bias for power savings or performance improvement, the design teams must consider this feature from the very beginning of product development,” she said. While biasing does not require specific EDA tools, and can be achieve with an extended library characterization, design architects must define the best corners for body bias in order to gain in performance and power. And design teams must implement “the right set of IPs to manage body biasing,” such as a BB generator, BB monitors, and during testing, a trimming methodology.

Nguyen acknowledged that finFETs have drive-current advantages. But compared with bulk CMOS, FD-SOI has superior electrostatics, which enables scaling of analog/RF devices while maintaining a high transistor gain. And drive current increases as gate length is scaled, she said.

For 14/16 nm finFETs, Nguyen said the gate length is in the 25-30 nm range. The 22FDX transistors have a gate length in the 20nm range. “The very short gate length results in a small gate capacitance, and total lower gate resistance,” she said.

For fringing capacitance, the most conservative number is that 22nm FD-SOI is 30 percent lower than leading finFETs, though she said “finFETs have made a lot of progress in this area.”

Analog advantages

It is in the analog and RF areas that FD-SOI offers the most significant advantages, Nguyen said. The fT and fMAX of 350 and 300 GHz, respectively, have been demonstrated by GlobalFoundries for its 22nm FD-SOI technology. For analog devices, she claimed that FD-SOI offers better transistor mismatch, high intrinsic device gain (Gm/Gds ratio), low noise, and flexibility in Vt tuning. Figure 2 shows how 22FDX outperforms finFETs for fT/fMax.

Figure 2. 22FDX outperforms finFETs for fT/fMax. Source: GlobalFoundries.

“FDSOI is the only device architecture that meets all those requirements. Bulk planar CMOS suffers from large transistor mismatch due to random dopant fluctuation and low device gain due to poor electrostatics. FinFET technology improves on electrostatics but it lacks the back bias capability.”

The undoped channel takes away the random doping effect of a partially depleted (doped) channel, reducing variation by 50-60 percent.

Analog designers using FD-SOI, she said, have “the ability to tune the Vt by back-bias to compensate for process mismatch or drift, and to offer virtually any Vt desired. Near-zero Vt can also be achieved in FD-SOI, which enables low voltage analog design for low power consumption applications.”

“If you believe the future is about mobility, about more communications and low power consumption and cost sensitive IoT chips where analog and RF is about 50 percent of the chip, then FD-SOI has a good future.

“No single solution can fit all. The key is to build up the ecosystem, and with time, we are pushing that,” she said.

D2S Releases 4th-Gen IC Computational Design Platform

Friday, September 30th, 2016


By Ed Korczynski, Sr. Technical Editor

D2S ( recently released the fourth generation of its computational design platform (CDP), which enables extremely fast (400 Teraflops) and precise simulations for semiconductor design and manufacturing. The new CDP is based on NVIDIA Tesla K80 GPUs and Intel Haswell CPUs, and is architected for 24×7 cleanroom production environments. To date, 14 CDPs across four platform generations are in use by customers around the globe, including six of the latest fourth generation. In an exclusive interview with SemiMD, D2S CEO Aki Fujimura stated, “Now that GPUs and CPUs are fast-enough, they can replace other hardware and thereby free up engineering resources to focus on adding value elsewhere.”

Mask data preparation (MDP) and other aspects of IC design and manufacturing require ever-increasing levels of speed and reliability as the data sets upon which they must operate grow larger and more complex with each device generation. The Figure shows a mask needed to print arrays of sub-wavelength features includes complex curvilinear shapes which must be precisely formed even though they do not print on the wafer. Such sub-resolution assist features (SRAF) increase in complexity and density as the half-pitch decreases, so the complexity of mask data increases far more than the density of printed features.

Sub-wavelength lithography using 193nm wavelength requires ever-more complex masks to repeatably print ever smaller half-pitch (HP) features, as shown by (LEFT) a typical mask composed of complex nested curves and dots which do not print (RIGHT) in the array of 32nm HP contacts/vias represented by the small red circles. (Source: D2S)

GPUs, which were first developed as processing engines for the complex graphical content of computer games, have since emerged as an attractive option for compute-intensive scientific applications due in part to their ability to run many more computing threads (up to 500x) compared to similar-generation CPUs. “Being able to process arbitrary shapes is something that mask shops will have to do,” explained Fujimura. “The world could go 193nm or EUV at any particular node, but either way there will be more features and higher complexity within the features, and all of that points to GPU acceleration.”

The D2S CDP is engineered for high reliability inside a cleanroom manufacturing environment. A few of the fab applications where CDPs are currently being used include:

  • model-based MDP for leading-edge designs that require increasingly complex mask shapes,
  • wafer plane analysis of SEM mask images to identify mask errors that print, and
  • inline thermal-effect correction of eBeam mask writers to lower write times.

“The amount of design data required to produce photomasks for leading-edge chip designs is increasing at an exponential rate, which puts more pressure on mask writing systems to maintain reasonable write times for these advanced masks. At the same time, writing these masks requires higher exposure doses and shot counts, which can cause resist proximity heating effects that lead to mask CD errors,” stated Noriaki Nakayamada, group manager at NuFlare Technology. “D2S GPU acceleration technology significantly reduces the calculation time required to correct these resist heating effects. By employing a resist heating correction that includes the use of the D2S CDP as an OEM option on our mask writers, NuFlare estimates that it can reduce CD errors by more than 60 percent, and reduce write times by more than 20 percent.”

In the E-beam Initiative 2015 survey, the most advanced reported mask-set contained >100 masks of which ~20% could be considered ‘critical’. The just released 2016 survey disclosed that the most complex single-layer mask design written last year required 16 TB of data, however platforms like D2S’ CDP have been used to accelerate writing such that the average reported write times have decreased to a weighted average of 4 hours. Meanwhile, the longest reported mask write time decreased from 72 to 48 hours.

Linde Launches Asian R&D Center in Taiwan

Friday, September 23rd, 2016


By Ed Korczynski, Sr. Technical Editor

Timed in coordination with SEMICON Taiwan 2016 happening in early September, The Linde Group launched a new electronics R&D Center in Taichung, Taiwan. “We had a fabulous opening, with 35 to 40 customers and 20 people from the Taiwanese government such as ITRI,” said Carl Jackson (Fig. 1), Head of Electronics, Technology and Innovation at The Linde Group, in an exclusive interview with SemiMD. This new R&D center represents an investment of approximately EUR 5m to support local customers and development partners throughout the Asia Pacific region with its state-of-the-art analytical and product development laboratory.

FIG1: Carl Jackson, Head of Electronics, Technology and Innovation, LindeGroup. (Source: The Linde Group)

Linde has dozens of labs around the world supporting different industries, all of which work in coordination with three main centers termed ‘hubs’ located in New Jersey, Munich, and Shanghai. This new electronics lab in Taichung will support customers in China, Malaysia, Singapore, South Korea, and of course Taiwan. Working closely with local research partners and customers, the new center will also support development of local supply chains and local special gases manufacturing capabilities. “Customers do prefer a local supply-chain. There are examples in China where they’re even specifying a geographical limit around their fab, and if you’re outside that limit you can’t supply the materials,” said Jackson.

As a major step in collaborating with key regional partners in Taiwan, Linde is also entering into a collaboration agreement with the Industry Technology Research Institute (ITRI) of Taiwan. Jia-Ruey Duann, the vice president of ITRI, stated, “ ITRI values the cooperation on Electronic Specialty Gases (ESG) Production & Analysis with The Linde Group, and we look forward to working together to develop new products and services that benefit Taiwan’s electronics industry.”

Supporting Asia Pacific region

The R&D Center is part of an ongoing expansion and investment in the Asia Pacific region for Linde Electronics. Last year Linde commissioned the world’s largest on-site fluorine plant to supply SK Hynix, in addition to bringing multiple new electronics project on-stream in Asia. This year Linde announced that they have been awarded multiple gas and chemical supply wins for a number of world-leading photovoltaic cell manufacturers in Southeast Asia. “We’re talking about customer-specific applications in specific market segments,” explained Jackson. “They come to us with specific problems and the purpose of this lab is to find solutions.”

While this new lab supports manufacturing customers in LED, FPD, and PV industries, most of the demand for new materials comes from IC fabs. “Semiconductors always drive the materials focus, because it’s rare to find unique demands in the other markets,” said Jackson. “However, the scale can be much larger in the other segments, and that can drive improvements in gases used in semiconductor fabs. An example is ammonia which is used in huge volumes by LED fabs, and similarly when thin-film solar was happening there was huge demand for germane.”

Linde assists customers in realizing continuous technology progress through improvements in the ability to reduce chemical variability in existing products and in the development of new materials that are critical to support customers’ technology roadmaps. “We feel as thought we need to be better positioned to be able to support customers when they require it,” said Jackson. “Quite frankly, some materials don’t travel well. I’m not suggesting that suddenly we’ll start supplying everything locally, but this facility will help us start supplying customers throughout Asia.”

The Linde Electronics R&D Center (Fig. 2) will be used for improvement of product quality through advanced synthesis, purification, packaging and new applications development. These improvements are enabled by Linde’s advanced analytical processes and quality control systems that verify compositions and manage impurities.

FIG2: New electronics R&D center in Taichung, Taiwan will support customers throughout the Asia Pacific region. (Source: The Linde Group)

Analysis and Synthesis

“The way that we have it configured it has two distinct features that work together, but the main focus is on analysis and that’s where the main investment has been made,” explained Jackson. “We think that we probably have the most advanced lab in Asia and perhaps in the world. At least for the materials portfolio that we have we can do ‘finger-printing’ analysis, including all the trace-elements and all the metals, which is to say all the things that can potentially affect process.”

The second feature of this lab is the ability to create experimental quantities of completely new chemical and blends to meet the needs of customers working in advanced device R&D and in pilot-line production. The lab features new purification and new synthesis technologies that work on small quantities of materials. “One capability we have is to do binary- or mixed-component blends,” elaborated Jackson. “In terms of purification, we have a bench-scale set-up with absorbance and distillation, but generally that would be done somewhere else. That’s the advantage of being connected to the global network of labs.”

“There are unique requirements for every fab in every industry,” reminded Jackson. “For example, nitrous-oxide is a key critical-material for OLED manufacturing and you must maintain repeatability in every cylinder, in every truck, and down every pipe. How do you reduce the variability in the molecule regardless of the supply mode? Having the ability to do in-depth analysis certainly gives us a leg up.”

Since sustainability of the supply-chain is always essential, one trend is HVM fabs today is the consideration of recover methods for critical gases such as argon, helium, and neon. “In some cases it works, and particularly as the scale continues to grow. Being able to use the expertise from our Linde Engineering colleagues and scaling it to the right size for semiconductor manufacturing is really important for us.”


What is Your China Strategy?

Wednesday, September 7th, 2016


By Dave Lammers, Contributing Editor

Equipment vendors have a lot on their plates now, with memory customers pushing 3D NAND, foundries advancing to the 7 nm node, and 200mm fabs clamoring to come up with hard-to-find tools.

China, which has renewed its investments in displays, packaging, and both 200mm and 300mm front-end fab capacity, is another challenge.

“All the managers in my company are scrambling to adjust their budgets so they can support China. I can tell you people are booking lots of flights to Shanghai,” said one engineer at a major equipment supplier.

Bill McClean, president of IC Insights (Scottsdale, AZ), said China is fast becoming a center for 3D NAND production, as several companies expand production in China. Intel is converting its Dalian, China fab partly to 3D NAND, and Toshiba might very well make a deal in China to build a 3D NAND fab there, he said.

“China could be the 3D NAND capital of the world,” McClean said at The ConFab conference in Las Vegas. While the U.S. government limits exports of leading-edge technologies on national security concerns, 3D NAND relies more on overlay and etch techniques at relaxed (40nm) design rules, he noted.

“Since the 3D NAND makers are not pushing feature sizes, it doesn’t raise red flags like if Chinese companies wanted FinFET technology. That is when the alarms go off,” McClean said.

However, McClean said the 3D NAND market is not immune to the oversupply issues that now face the DRAM makers. “I’ve seen this rodeo before,” McClean said.

China’s domestic IC market is slightly more than $100 billion, McClean said, while chip production in China was about $13 billion last year, representing just under 5 percent of worldwide production (Figure 1).

Figure 1. Source: IC Insights.

The difference between consumption and domestic production, referred to as the delta, is made up by imports. “This 13 percent (from domestic suppliers) drives the Chinese government crazy. Yes, they will close that gap a little bit, but not to the extent that they think,” McClean told The ConFab audience in mid-June.

Robert Maire, who consulted for SMIC on its initial public offering in the United States, spoke at length about China at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) in Saratoga Springs, N.Y. Amid the mergers and acquisition frenzy of last year, China managed to pull off the acquisitions of CMOS image sensor vendor Omnivision, memory maker ISSI, the RF business of NXP, Pericom Semiconductor, and Mattson Technology. (McClean said he believes that if the Omnivision acquisition were attempted in today’s more China-wary environment that Washington would block the deal).

Maire, principal at Semiconductor Advisors (New York), said China is far behind in its domestic semiconductor production equipment business. “If China has 14nm production capacity, but buys all of its equipment from abroad, it doesn’t really help them that much. China is getting started in equipment, but it has a lot of catching up to do.”

Scott Foster, a partner in market intelligence firm TAP Japan (Tokyo), said China must have an international scope in the equipment sector if it hopes to compete with the likes of Applied, Lam, and other well-established vendors. A few of Japan’s equipment suppliers are succeeding while operating in relatively narrow niches, but overall, competing globally is a challenge for mid-sized Japanese equipment companies. “If this is what is happening to Japanese equipment vendors, what chance do Chinese companies have?” Foster said.

Packaging may prove to be key

Skeptics of China’s prospects might take a long look at China’s success in packaging, an area where China is succeeding, in part by acquisitions of Asia-based companies, notably STATS ChipPAC (Singapore), which was acquired by Jiangsu Changjiang Electronics Technology Co. (JCET) last year. Separately, SMIC and JCET formed a joint venture to focus on chip scale packaging, wafer bumping, and fan-out wafer level packaging. The packaging joint venture is located 90 minutes from Shanghai, said Sonny Hui, senior vice president of worldwide marketing at SMIC.

Jim Walker, the packaging analyst at market research firm Gartner, said China-based packaging is now valued at nearly half (43 percent) of all worldwide packaging value by IDMs and OSATs. While the packaging industry overall is dealing with price pressures, the advent of wafer level packaging, and other forms of multi-chip integration, bodes well for the higher end of the back-end industry.

“As the semiconductor industry matures and Moore’s Law scaling slows, multi-chip integration via packaging is providing system vendors with a faster time-to-market, and a lower-cost means, of solving system-level challenges,” Walker said.

Packaging multiple chips in a module is likely to play a key role in the Internet of Things (IoT) markets, Walker said. Automotive, medical, home, and consumer solutions are all “heavily reliant on packaging,” he said.

Sam Wang, a Gartner analyst who focuses on foundries, pointed out at Semicon West that China’s semiconductor industry faces continued challenges in a hotly contested foundry market. Few China-based foundries have enjoyed the strong growth that SMIC has demonstrated, he said. (SMIC has been “running at very high utilizations, and we are working very hard to solve the problem,” said SMIC’s Hui.)

While SMIC has enjoyed double-digit growth for several years, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total worldwide foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

China-based companies are focusing partly on MEMS and other devices made on 200mm wafers, including analog, sensors, and power. SMIC’s Hui said “most of our customers don’t see much benefit to migrate to 12-inch. 200mm still has a lot of potential; just consider the hundreds of products still made on 180nm technology, which was developed 20 years ago. Many customers still see that as a sweet spot.”

Foster, who has three decades of tech-watching experience from his base in Tokyo, said the 200mm wafer fabs being built in China will make products that “do not need the gigantic scale” required of Intel, TSMC, Samsung and Toshiba. Figure 2, courtesy of SEMI, shows the seventeen 200mm wafer fabs/lines that are expected begin operation in 2015 to 2019. Six of the seventeen will be in China.

Figure 2. Source: SEMI

“After decades of trying, China has found a market-based strategy: building scale and experience from the bottom up. In the long run, this is likely to be far more effective than going out to buy foreign companies,” Foster said.

Display is another area China is counting on. In an Aug. 18 conference call following a strong quarter, Applied Materials chief financial officer Bob Halliday told analysts: “In display, we recorded record orders of $803 million with more than half coming from projects in China.”

The Applied CFO also said, “Just listening to the Chinese government, they’re in this for a long-term and their interest in investing in the semiconductor industry is probably only going to increase.”

Kateeva turns to China funds

China is often lumped together with other Asian nations as a country that has a government-led, me-too, follower mentality. But increasingly, China is either proving innovative itself, or able to quickly adopt innovations from the West.

At the Innovation Forum at Semicon West, Conor Madigan, co-founder of ink jet printer startup Kateeva (Newark, Calif.) spoke about the readiness of Chinese venture capital funds to step in where Silicon Valley-based VCs were overly hesitant. China proved a more receptive place to raise money than the United States, though the early establishment of the M.I.T. spinout did come from U.S. based sources.

After its initial development effort, Kateeva figured it needed more than $100 million to accomplish its goals. After making the rounds to raise funds in the United States without success, Kateeva turned to China, where five different funds eventually became investors.

Asked why Chinese investors were willing to back Kateeva when funds in the United States and other Asian countries were reluctant, Madigan pointed to a confluence of factors.

The Chinese government had identified OLED displays as a focus of its Five Year Plan. The follow-on economic plan further identified inkjet technology as a critical technology. Investors in China favor companies which can provide the equipment for products, such as OLEDs, which have the government’s blessing and financial support. That government support reduced the investment risks in ways that are not readily seen in Japan or the United States, he said.

Madigan had studied OLEDs as an undergraduate at Princeton University, and then studied under an M.I.T. professor who had developed ink jet technology for large formats.

Though an early goal was to use large-format inkjet to deposit the RGB materials in OLEDs, the Kateeva team learned that its YieldJet system could be adapted to solve a more urgent problem: thin film encapsulation (TFE). It “pivoted” on the advice of an early customer, which fortunately already had developed the “ink” which under UV light would form a uniform encapsulation layer for the large OLED substrates required for TVs and other large display applications.

Two display companies in China identified Kateeva as a strategic partner, which allowed Kateeva to raise money from private Chinese VC funds, rather than taking money from regional government funds which might have asked Kateeva to locate its manufacturing operations in their local area.

Madigan also pointed to the tendency of U.S.-based venture capital funds to favor software companies over manufacturing-focused opportunities. As VCs make money in software-related startups, the funds gradually have more partners and investors which favor software because that is what they are familiar with.

VC fund managers with backgrounds in software “want to invest in the space that they understand. In the United States, that often means software, because you pick companies in the space that you understand.”

3D-NAND Deposition and Etch Integration

Thursday, September 1st, 2016


By Ed Korczynski, Sr. Technical Editor

3D-NAND chips are in production or pilot-line manufacturing at all major memory manufacturers, and they are expected to rapidly replace most 2D-NAND chips in most applications due to lower costs and greater reliability. Unlike 2D-NAND which was enabled by lithography, 3D-NAND is deposition and etch enabled. “With 3D-NAND you’re talking about 40nm devices, while the most advanced 2D-NAND is running out of steam due to the limited countable number of stored electrons-per-cell, and in terms of the repeatability due to parasitics between adjacent cells,” reminded Harmeet Singh, corporate vice president of Lam Research in an exclusive interview with SemiMD to discuss the company’s presentation at the Flash Memory Summit 2016.

“We’re in an era where deposition and etch uniquely define the customer roadmap,” said Singh,“and we are the leading supplier in 3D-NAND deposition and etch.” Though each NAND manufacturer has different terminology for their unique 3D variant, from a manufacturing process integration perspective they all share similar challenges in the following simplified process sequences:

1)    Deposition of 32-64 pairs of blanket “mold stack” thin-films,

2)    Word-line hole etch through all layers and selective fill of NAND cell materials, and

3)    Formation of “staircase” contacts to each cell layer.

Each of these unique process modules is needed to form the 3D arrays of NVM cells.

For the “mold stack” deposition of blanket alternating layers, it is vital for the blanket PECVD to be defect-free since any defects are mirrored and magnified in upper-layers. All layers must also be stress-free since the stress in each deposited layer accumulates as strain in the underlying silicon wafer, and with over 32 layers the additive strain can easily warp wafers so much that lithographic overlay mismatch induces significant yield loss. Controlled-stress backside thin-film depositions can also be used to balance the stress of front-side films.

Hole Etch

“The difficult etch of the hole, the materials are different so the challenges is different,” commented Singh about the different types of 3D-NAND now being manufactured by leading fabs. “During this conference, one of our customer presented that they do not see the hole diameters shrinking, so at this point it appears to us that shrinking hole diameters will not happen until after the stacking in z-dimension reaches some limit.”

Tri-Layer Resist (TLR) stacks for the hole patterning allow for the amorphous carbon hardmask material to be tuned for maximum etch resistance without having to compromise the resolution of the photo-active layer needed for patterning. Carbon mask is over 3 microns thick and carbon-etching is usually responsive to temperature, so Lam’s latest wafer-chuck for etching features >100 temperature control zones. “This is an example of where Lam is using it’s processes expertise to optimize both the hardmask etch as well as the actual hole etch,” explained Singh.

Staircase Etch

The Figure shows a simplified cross-sectional schematic of how the unique “staircase” wordline contacts are cost-effectively manufactured. The established process of record (POR) for forming the “stairs” uses a single mask exposure of thick KrF photoresist—at 248nm wavelength—to etch 8 sets of stairs controlled by a precise resist trim. The trimming step controls the location of the steps such that they align with the contact mask, and so must be tightly controlled to minimize any misalignment yield loss.

A) Simplified cross-sectional schematic of the staircase etch for 3D-NAND contacts using thick photoresist, B) which allows for controlled resist trimming to expose the next “stair” such that C) successive trimming creates 8-16 steps from a single initial photomask exposure. (Source: Ed Korczynski)

Lam is working on ways to tighten the trimming etch uniformity such that 16 sets of stairs can be repeatably etched from a single KrF mask exposure. Halving the relative rate of vertical etch to lateral etch of the KrF resist allows for the same resist thickness to be used for double the number of etches, saving lithography cost. “We see an amazing future ahead because we are just at the beginning of this technology,” commented Singh.


Silicon as Disruptive Platform for IoT Applications

Monday, August 29th, 2016


By Ed Korczynski, Sr. Technical Editor

Marie Semeria, chief executive officer of CEA-Leti (, sat down with SemiMD during SEMICON West to discuss how the French R&D and pilot manufacturing campus—located at the foot of the beautiful French alps near Grenoble—is expanding the scope of it’s activities to develop systems solutions for the Internet-of-Things (IoT). Part-1 on hardware/software co-development was published last month.

Korczynski: Regarding ‘IoT’ applications, we expect that chips must be very low cost to be successful, and at the same time the ultimately winning solutions will be those that combine the best functionalities from different technology spaces each in a ‘sweet spot’ of cost to performance. It seems that being able to do it on SOI wafers could produce the right volumes.

Semeria: Yes. It could be enough.

Korczynski: Do you have any feel in advance for how much area of silicon is needed? Some small ADC, an 8-bit micro-controller, and RF components may be done in different processes and then integrated. Is it possible that the total area of silicon needed could be less than a square millimeter?

Semeria: Yes.

Korczynski: Well, if they are that small then we have to remember how many units we’d get from just a single wafer, and there are 24 wafers in a batch…

Semeria: One batch can be enough for one market, depending upon the application.

Korczynski: If this is the case, then even though the concept of purely-additive roll-to-roll processes are attractive, oddly they may be too efficient and produce more units than the world can absorb. If we can do all that we need to do with established silicon wafer fab technology creating ICs smaller than a square millimeter then it will be very cost-effective.

Semeria: Leti’s strategy is to keep the performance of solid-state devices, so not to go to organic electronics. Use silicon as the differentiator to lower the cost, add more functions, and then miniaturize all that can be miniaturized. In this way we are achieving integration of MEMS with small electronics in arrays as small as one millimeter square. When you deal with such small die you can put them inside of flexible materials, inside of a t-shirt and it’s no problem. So that’s our strategy to keep small silicon and put it in clothes, in shoes, in windows, in glasses, and all sorts of flexible materials. When you are thinning substrates for bonding, then the thinned silicon is very flexible.

Korczynski: In 1999 I worked for one of the first companies selling through-silicon via technology, and it was all about backside thinning so I’ve played with flexible wafers.

Semeria: So you know what I mean.

Korczynski: Around 50 microns and below as long as you etch away any grinding defects from the backside it is very strong and very flexible (Fig. 1). At 50 microns the chip is still thick enough to be easily picked-and-placed, but it’s flexible. Below 10 microns the wafer is difficult to handle.

FIGURE 1: 50 micron thin silicon wafers can be strong and very flexible. (Source: Virginia Semiconductor)

Semeria: To maintain the advantage of cost for different applications spaces, we are developing the ‘chiplet’ approach which means a network of chips. It starts with a digital platform, then you add an active interposer to connect different dice. For example you could have 28nm-node on the bottom and a 14nm-node chip on top for some specific function. Then you can put embedded memory and RF connected through the interposer, and it’s the approach that we promote for the first generation of multi-functional integration on digital. Very flexible, cost-effective.

Korczynski: This is using some sort of bus to move information?

Semeria: Yes, this will be an electronic bus for the first generation, as we recently announced. Then a photonics interposer could be used for higher-speed data rate in a future generation. We have a full roadmap with different types of integration schemes. So it’s a way to combine all with silicon. Everything is intended to be integrated into existing 300mm silicon facilities. Some weeks ago we presented the first results showing silicon quantum bits built on 300mm substrates, and fully compatible with CMOS processing. So it’s the way we are going, taking a very disruptive approach using the foundation of proven 300mm silicon processing.

Korczynski: Interesting.

Semeria: For example, regarding driving assistance applications we have to consider fusion integration of different sensors, and complete coverage of the environment with low power-consumption. For computing capacity we developed a completely disruptive approach, very different from Intel and very different from nVidia which use consumer products as the basis for automotive application products. Specifically for automotive we developed a new probabilistic methodology to avoid all of the calculations based on floating-point. In this way we can divide the computing needs of the device by 100, so it’s another example of developing just the right device for the right application adapted for the right environment. So the approach is very different in development for IoT instead of mainstream CMOS.

Korczynski: For automotive there’s such a requirement for reliability, with billions of dollars at stake in product recalls and potential lawsuits, the auto industry is very risk-averse for very good reasons. So historically they’ve always used trailing-edge nodes, and if you want to supply to them you have to commit to 10 or maybe 20 years of manufacturing, and yet we still want to add in advance functionalities. The impression I’ve gotten is that the 28nm FD-SOI platform is fairly ideal here.

Semeria: FD-SOI is very reliable and very efficient. That’s why when we showed our demonstrator at the recent DAC it’s based on the STMicroelectronics micro-controller. It’s very reliable and adaptable for automotive applications.

Korczynski: Is it at 28nm?

Semeria: No, about 40nm now. The latest generation is not needed, because we changed the algorithms so we didn’t need so much capacity in computing. In IoT there is space to use 40nm or 32nm down to 28nm. It’s a great space to use ‘old technologies’ and optimize them with the right algorithms, the right signal-processing, and the right security. So it’s very exciting for Leti because we have all of the key competencies to be able to handle the IoT challenge, and there is a great ability to make various integration schemes depending upon the application. There is a very large space to demonstrate, and to develop new materials.

Korczynski: Does this relate to some recent work I’ve seen from Leti with micro-cantilevers?

Semeria: Yes, this is the work we are doing with CalTech on micro-resonators (Fig. 2).

FIGURE 2: MEMS/NEMS silicon cantilever resonator capable of detecting individual adhered molecules, for integration with digital CMOS in a complete IoT sensing system. (Source: Leti)

Korczynski: Thank you very much for taking the time to discuss these important trends.

Semeria: It is a pleasure.


Next Page »