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Photonics in Silicon R&D Toward Tb/s

Tuesday, January 3rd, 2017

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By Ed Korczynski, Sr. Technical Editor

The client:server computing paradigm colloquially referred to as the “Cloud” results in a need for extremely efficient Cloud server hardware, and from first principles the world can save a lot of energy resources if servers run on photonics instead of electronics. Though the potential for cost-savings is well known, the challenge of developing cost-effective integrated photonics solutions remains. Today, discrete compound-semiconductor chips function as transmitters, multiplexers (MUX), and receivers of photons, while many global organizations pursue the vision of lower-cost integrated silicon (Si) photonics circuits.

Work on photonics chips—using light as logic elements in an integrated circuit—built in silicon (Si) has accelerated recently with announcements of new collaborative research and development (R&D) projects. Leti, an institute of CEA Tech, announced the launch of a European Commission Horizon 2020 “COSMICC” project to enable mass commercialization of Si-photonics-based transceivers to meet future data-transmission requirements in data centers and super computing systems.

The Leti-coordinated COSMICC project will combine CMOS electronics and Si-photonics with innovative fiber-attachment techniques to achieve 1 Tb/s data rates. These scalable solutions will provide performance improvement an order of magnitude better than current VCSELs transceivers, and the COSMICC-developed technology will address future data-transmission needs with a target cost per bit that traditional wavelength-division multiplexing (WDM) transceivers cannot meet. The project’s 11 partners from five countries are focusing on developing mid-board optical transceivers with data rates up to 2.4 Tb/s with 200 Gb/s per fiber using 12 fibers. The devices will consume less than 2 pJ/bit. and cost approximately 0.2 Euros/Gb/s.

Figure 1: Schematic of COSMICC on-board optical transceiver at 2.4 Tb/s using 50 Gbps/wavelength, 4 CWDM wavelengths per fiber, 12 fibers for transmission and 12 fibers for reception. (Source: Leti)

A first improvement will be the introduction of a silicon-nitride (SiN) layer that will allow development of temperature-insensitive MUX/DEMUX devices for coarse WDM operation, and will serve as an intermediate wave-guiding layer for optical input/output. The partners will also evaluate capacitive modulators, slow-wave depletion modulators with 1D periodicity, and more advanced approaches. These include GeSi electro-absorption modulators with tunable Si composition and photonic crystal electro-refraction modulators to make micrometer-scale devices. In addition, a hybrid III-V on Si laser will be integrated in the SOI/SiN platform in the more advanced transmitter circuits.

Meanwhile in the United States, Coventor, Inc. is collaborating with the Massachusetts Institute of Technology (MIT) on photonics modeling. MIT is a key player in the AIM Photonics program, a federally funded, public-private partnership established to advance domestic capabilities in integrated photonic technology and strengthen high-tech U.S.-based manufacturing. Coventor will provide its SEMulator3D process modeling platform to model the effect of process variation in the development of photonic integrated components.

“Coventor’s technical expertise in predicting the manufacturability of advanced technologies is outstanding. Our joint collaboration with Coventor will help us develop new design methods for achieving high yield and high performance in integrated photonic applications,” said Professor Duane Boning of MIT. Boning is an expert at modeling non-linear effects in processing, many years after working on the semiconductor industry’s reference model for the control of chemical-mechanical planarization (CMP) processing.

—E.K.

MRAM Takes Center Stage at IEDM 2016

Monday, December 12th, 2016

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By Dave Lammers, Contributing Editor

The IEDM 2016 conference, held in early December in San Francisco, was somewhat of a coming-out party for magneto-resistive memory (MRAM). The MRAM presentations at IEDM were complemented by a special MRAM-focused poster session – organized by the IEEE Magnetics Society in cooperation with the IEEE Electron Devices Society (EDS) – with 33 posters and a lively crowd.

And in the opening keynote speech of the 62nd International Electron Devices Meeting, Seok-hee Lee, executive vice president at SK Hynix (Seoul), set the stage by saying that the race is on between DRAM and emerging memories such as MRAM. “Originally, people thought that DRAM scaling would stop. Then engineers in the DRAM and NAND worlds worked hard and pushed out the end further in the future,” he said.

While cautioning that MRAM bit cells are larger than in DRAM and thus more more costly, Lee said MRAM has “very strong potential in embedded memory.”

SK Hynix is not the only company with a full-blown MRAM development effort underway. Samsung, which earlier bought MRAM startup Grandis and which has a materials-related research relationship with IBM, attracted a standing-room-only crowd to its MRAM paper at IEDM. TSMC is working with TDK on its program, and Sony is using 300mm wafers to build high-performance MRAMs for startup Avalanche Technology.

And one knowledgeable source said “the biggest processor company also has purchased a lot of equipment” for its MRAM development effort.

Dave Eggleston, vice president of emerging memory at GlobalFoundries, said he believes GlobalFoundries is the furthest along on the MRAM optimization curve, partly due to its technology and manufacturing partnership with Everspin Technologies (Chandler, Ariz.). Everspin has been working on MRAM for more than 20 years, and has shipped nearly 60 million discrete MRAMs, largely to the cache buffering and industrial markets.

GlobalFoundries has announced plans to use embedded STT-MRAM in its 22FDX platform, which uses fully-depleted SOI technology, as early as 2018.

Future versions of MRAM– such as spin orbit torque (SOT) MRAM and Voltage Controlled MRAM — could compete with SRAM and DRAM. Analysts said today’s spin-transfer torque STT-MRAM – referring to the torque that arises from the transfer of electron spins to the free magnetic layer — is vying for commercial adoption as ever-faster processors need higher performance memory subsystems.

STT-MRAM is fast enough to fit in as a new memory layer below the processor and the SRAM-based L1/L2 cache layers, and above DRAM and storage-level NAND flash layers, said Gary Bronner, vice president of research at Rambus Inc.

With good data retention and speed, and medium density, MRAM “may have advantages in the lower-level caches” of systems which have large amounts of on-chip SRAM, Bronner said, due in part to MRAM’s smaller cell size than six-transistor SRAM. While DRAM in the sub-20nm nodes faces cost issues as its moves to more complex capacitor structures, Bronner said that “thus far STT-MRAM) is not cheaper than DRAM.”

IBM researchers, which pioneered the spin-transfer torque approach to MRAM, are working on a high-performance MRAM technology which could be used in servers.

As of now, MRAM density is limited largely by the size of the transistors required to drive sufficient current to the magnetic tunnel junction (MTJ) to flip its magnetic orientation. Dan Edelstein, an IBM fellow working on MRAM development at IBM Research, said “it is a tall order for MRAM to replace DRAM. But MRAM could be used in system-level memory architectures and as an embedded memory technology.”

PVD and etch challenges

Edelstein, who was a key figure in developing copper interconnects at IBM some twenty years ago, said MRAM only requires a few extra mask layers to be integrated into the BEOL in logic. But there remain major challenges in improving the throughput of the PVD deposition steps required to deposit the complex material stack and to control the interfacial layers.

The PVD steps must deposit approximately 30 layers and control them to Angstrom-level precision. Deposition must occur under very low base pressure, and in oxygen- and water-vapor free environments. While tool vendors are working on productization of 300mm MRAM deposition tools, Edelstein said keeping particles under control and minimizing the maintenance and chamber cleaning are all challenging.

Etching the complex materials stack is even harder. Chemical RIE is not practical for MRAMs at this point, and using ion beam etching (IBE) presents challenges in terms of avoiding re-deposition of material sputtered off during the IBE etch steps for the high-aspect-ratio MTJs.

For the tool vendors, MRAMs present challenges as companies go from R&D to high-volume manufacturing, Edelstein said.

A Samsung MRAM researcher, Y.J. Song, briefly described IBE challenges during an IEDM presentation describing an embedded STT-MRAM with a respectable 8-Mbit density and a cell size of .0364 sq. micron. “We worked to optimize the contact etching,” using IBE etch during the patterning steps, he said. The short fail rate was reduced, while keeping the processing temperature at less than 350°C, Song said.

Samsung embedded an STT-MRAM module in the copper back end of the line (BEOL) of a 28nm logic process. (Source: Samsung presentation at IEDM 2016).

Many of the presentations at IEDM described improvements in key parameters, such as the tunnel magnetic resistance (TMR), cell size, data retention, and read error rates at high temperatures or low operating voltages.

An SK Hynix presentation described a 4-Gbit STT-MRAM optimized as a stand-alone, high-density memory. “There still are reliability issues for high-density MRAM memory,” said SK Hynix’s S.-W. Chung. The industry needs to boost the TMR “as high as possible” and work on improving the “not sufficiently long” retention times.

At high temperatures, error rates tend to rise, a concern in certain applications. And since devices are subjected to brief periods of high temperatures during reflow soldering, that issue must be dealt with as well, detailed by a Bosch presentation at IEDM.

Cleans and encapsulation important

Gouri Sankar Kar, who is coordinating the MRAM research program at the Imec consortium (Leuven, Belgium), said one challenge is to reduce the cell size and pitch without damaging the magnetic properties of the magnetic tunnel junction. For the 28nm logic node, embedded MRAM would be in the range of a 200nm pitch and 45nm critical dimensions (CDs). At the IEDM poster session, Imec presented an 8nm cell size STT-MRAM that could intersect the 10nm logic node, with the MRAM pitch in the 100nm range. GlobalFoundries, Micron, Qualcomm, Sony and TSMC are among the participants in the Imec MRAM effort.

Kar said in addition to the etch challenges, post-patterning treatment and the encapsulation liner can have a major impact on MTJ materials selection. “Some metals can be cleaned immediately, and some not. For the materials stack, patterning (litho and etch) and clean optimization are crucial.”

“Chemical etch (RIE) is not really possible at this stage. All the tool vendors are working on physical sputter etch (IBE) where they can limit damage. But I would say all the major tool vendors at this point have good tools,” Kar said.

To reach volume manufacturing, tool vendors need to improve the tool up-time and reduce the maintenance cycles. There is a “tail bits” relationship between the rate of bit failures and the health of the chambers that still needs improvement. “The cleanup steps after etching are very, very critical” to the overall effort to improving the cost effectiveness of MRAM, Kar said, adding that he is “very positive” about the future of MRAM technology.

A complete flow at AMAT

Applied Materials is among the equipment companies participating in the Imec program, with TEL and Canon-Anelva also heavily involved. Beyond that, Applied has developed a complete MRAM manufacturing flow at the company’s Dan Maydan Center in Santa Clara, and presented its cooperative work with Qualcomm on MRAM development at IEDM.

In an interview, Er-Xuan Ping, the Applied Materials managing director in charge of memory and materials technologies, said about 20 different layers, including about ten different materials, must be deposited to create the magnetic tunnel junctions. As recently as a few years ago, throughput of this materials stack was “extremely slow,” he said. But now Applied’s multi-cathode PVD tool, specially developed for MRAM deposition, can deposit 5 Angstrom films in just a few seconds. Throughput is approaching 20 wafers per hour.

Applied Materials “basically created a brand-new PVD chamber” for STT-MRAM, and he said the tool has a new e-chuck, optimized chamber walls and a multi-cathode design.

The MRAM-optimized PVD tool does not have an official name yet, and Ping said he refers to it as multi-cathode PVD. With MRAM requiring deposition of so many different metals and other materials, the Applied tool does not require the wafer to be moved in and out, increasing efficiency. The shape and structure of the chamber wall, Ping said, allow absorption of downstream plasma material so that it doesn’t come back as particles.

For etch, Applied has worked to create etching processes that result in very low bit failure rates, but at relatively relaxed pitches in the 130-200nm range. “We have developed new etch technologies so we don’t think etch will be a limiting factor. But etch is still challenging, especially for cells with 50nm and smaller cell sizes. We are still in unknown territory there,” said Ping.

Jürgen Langer, R&D manager at Singulus Technology (Frankfurt, Germany), said Singulus has developed a production-optimized PVD tool which can deposit “30 material layers in the Angstrom range. We can get 20 wafers per hour throughputs, so I would say this is not a beta tool, it is for production.”

Jürgen Langer, R&D manager, presented a poster on MRAM deposition from Singulus Technology (Frankfurt, Germany).

Where does it fit?

Once the production challenges of making MRAM are ironed out, the question remains: Where will MRAM fit in the systems of tomorrow?

Tom Coughlin, a data storage consultant based in Atascadero, Calif., said embedded MRAM “could have a very important effect for industrial and consumer devices. MRAM could be part of the memory cache layers, providing power advantages over other non-volatile devices.” And with its ability to power on and power off without expending energy, MRAM could reduce overall power consumption in smart phones, cutting in to the SRAM and NOR sectors.

“MRAM definitely has a niche, replacing some DRAM and SRAM. It may replace NOR. Flash will continue for mass storage, and then there is the 3D Crosspoint from Intel. I do believe MRAM has a solid basis for being part of that menagerie. We are almost in a Cambrian explosion in memory these days,” Coughlin said.

Process Control Deals with Big Data, Busy Engineers

Tuesday, November 22nd, 2016

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By Dave Lammers, Contributing Editor

Turning data into insights that will improve fab productivity is one of the semiconductor industry’s biggest opportunities, one that experts say requires a delicate mix between automation and human expertise.

A year ago, after the 2015 Advanced Process Control (APC) conference in Austin, attendees said one of their challenges was that it takes too long to create the fault detection and classification (FDC) models that alert engineers when something is amiss in a process step.

“The industry listened,” said Brad van Eck, APC conference co-chairman. Participants at the 2016 APC in Phoenix heard progress reports from device makers as diverse as Intel, Qorvo, Seagate, and TSMC, as well as from key APC software vendors including Applied Materials, Bistel, and others.

Steve Chadwick, principal engineer for manufacturing IT at Intel, described the challenge in a keynote address. IC manufacturers which have spent billions of dollars on semiconductor equipment are seeking new ways to maximize their investments.

Steve Chadwick

“We all want to increase our quality, make the product in the best time, get the most good die out, and all of that. Time to market can be a game changer. That is universal to the manufacturing space,” Chadwick said.

“Every time we have a new generation of processor, we double the data size. Roughly a gigabyte of information is collected on every wafer, and we sort thousands of wafers a day,” Chadwick said. The result is petabytes of data which needs to be stored, analyzed, and turned into actionable “wisdom.”

Intel has invested in data centers located close their factories, making sure they have the processing power to handle data coming in from roughly 5 billion sensor data points collected each day at a single Intel factory.

“We have to take all of this raw data that we have in a data store and apply some kind of business logic to it. We boil it down to ‘wisdom,’ telling someone something they didn’t know beforehand.”

In a sense, technology is catching up, as Hadoop and several other data search engines are adopted to big data. Also, faster processors allow servers to analyze problems in 15 seconds or less, compared to several hours a few years ago.

Where all of this gets interesting is in figuring out how to relate to busy engineers who don’t want to be bothered with problems that don’t directly concern them. Chadwick detailed the notification problem at Intel fabs, particularly as engineers use smart phones and tablets to receive alarms. “Engineers are busy, and so you only tell them something they need to know. Sometimes engineers will say, ‘Hey, Steve, you just notified my phone of 500 things that I can’t do anything about. Can you cut it out?’”

Notification must be prioritized, and the best option in many cases is to avoid notifiying a person at all, instead sending a notification to an expert system. If that is not an option, the notification has to be tailored to the device the engineer is using. Intel is moving quickly to HTML 5-based data due largely to its portability across multiple devices, he added.

With more than half a million ad hoc jobs per week, Intel’s approach is to keep data and analysis close to the factory, processing whenever possible in the local geography. Instead of shipping data to a distant data center for analysis, the normal procedure is to ship the small analysis code to a very large data set.

False positives decried

Fault detection and classification (FDC) models are difficult to create and oftentimes overly sensitive, resulting in false alarms. These widely used, manually created FDC models can take two weeks or longer to set up. While they take advantage of subject-matter-expert (SME) knowledge and are easy to understand, tool limits tend to be costly to set up and manage, with a high level of false positives and missed alarms.

An Applied Materials presentation — by Parris Hawkins, James Moyne, Jimmy Iskandar, Brad Schulze, and Mike Armacost – detailed work that Applied is doing in cooperation with process control researchers at the University of Cincinnati. The goal is to develop next-generation FDC that leverages Big Data, prediction analytics, and expert engineers to combine automated model development with inputs from human experts.

Fully automated solutions are plagued with significant false positives/negatives, and are “generally not very useful,” said Hawkins. By incorporating metrology and equipment health data, a form of “supervised” model creation can result in more accurate process controls, he said.

The model creation effort first determines which sensors and trace features are relevant, and then optimizes the tool limits and other parameters. The goal is to find the optimum between too-wide limits that fail to alert when faults are existent, and overly tight limits which set off false alarms too often.

Next-generation FDC would leverage Big Data and human expertise. (Source: Applied Materials presentation at APC 2016).

Full-trace FDC

BISTel has developed an approach called Dynamic Full Trace FDC. Tom Ho, president of BISTel USA, presented the work in conjunction with Qorvo engineers, where a beta version of the software is being used.

Tom Ho

Ho said Dynamic Full Trace FDC starts with the notion that the key to manufacturing is repeatability, and in a stable manufacturing environment “anything that differs, isn’t routine, it is an indication of a mis-process and should not be repeatable. Taking that concept, then why not compare a wafer to everything that is supposed to repeat. Based on that, in an individual wafer process, the neighboring wafer becomes the model.”

The full-trace FDC approach has a limited objective: to make an assessment whether the process is good or bad. It doesn’t recommend adjustments, as a run-to-run tool might.

The amount of data involved is small, because it is confined to that unique process recipe. And because the neighboring trace is the model, there is no need for the time-consuming model creation mentioned so often at APC 2016. Compute power can be limited to a personal computer for an individual tool.

Ho took the example of an etch process that might have five recipe steps, starting with pumping down the chamber to the end point where the plasma is turned off. Dynamic full-trace FDC assumes that most wafers will receive a good etch process, and it monitors the full trace to cover the entire process.

“There is no need for a model, because the model is your neighboring trace,” he said. “It definitely saves money in multiple ways. With the rollout of traditional FDC, each tool type can take a few weeks to set up the model and make sure it is running correctly. For multiple tool types that can take a few months. And model maintenance is another big job,” he said.

For the most part, the dynamic full-trace software runs on top of the Bistel FDC platform, though it could be used with another FDC vendor “if the customer has access to the raw trace data,” he said.

2D Materials May Be Brittle

Tuesday, November 15th, 2016

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By Ed Korczynski, Sr. Technical Editor

International researchers using a novel in situ quantitative tensile testing platform have tested the uniform in-plane loading of freestanding membranes of 2D materials inside a scanning electron microscope (SEM). Led by materials researchers at Rice University, the in situ tensile testing reveals the brittle fracture of large-area molybdenum diselenide (MoSe2) crystals and measures their fracture strength for the first time. Borophene monolayers with a wavy topography are more flexible.

A communication to Advanced Materials online (DOI: 10.1002/adma.201604201) titled “Brittle Fracture of 2D MoSe2” by Yinchao Yang et al. disclosed work by researchers from the USA and China led by Department of Materials Science and NanoEngineering Professor Jun Lou at Rice University, Houston, Texas. His team found that MoSe2 is more brittle than expected, and that flaws as small as one missing atom can initiate catastrophic cracking under strain.

“It turns out not all 2D crystals are equal. Graphene is a lot more robust compared with some of the others we’re dealing with right now, like this molybdenum diselenide,” says Lou. “We think it has something to do with defects inherent to these materials. It’s very hard to detect them. Even if a cluster of vacancies makes a bigger hole, it’s difficult to find using any technique.” The team has posted a short animation online showing crack propagation.

2D Materials in a 3D World -222

While all real physical things in our world are inherently built as three-dimensional (3D) structures, a single layer of flat atoms approximates a two-dimensional (2D) structure. Except for special superconducting crystals frozen below the Curie temperature, when electrons flow through 3D materials there are always collisions which increase resistance and heat. However, certain single layers of crystals have atoms aligned such that electron transport is essentially confined within the 2D plane, and those electrons may move “ballistically” without being slowed by collisions.

MoSe2 is a dichalcogenide, a 2D semiconducting material that appears as a graphene-like hexagonal array from above but is actually a sandwich of Mo atoms between two layers of Se chalcogen atoms. MoSe2 is being considered for use as transistors and in next-generation solar cells, photodetectors, and catalysts as well as electronic and optical devices.

The Figure shows the micron-scale sample holder inside a SEM, where natural van der Waals forces held the sample in place on springy cantilever arms that measured the applied stress. Lead-author Yang is a postdoctoral researcher at Rice who developed a new dry-transfer process to exfoliate MoSe2 from the surface upon which it had been grown by chemical vapor deposition (CVD).

Custom built micron-scale mechanical jig used to test mechanical properties of nano-scale materials. (Source: Lou Group/Rice University)

The team measured the elastic modulus—the amount of stretching a material can handle and still return to its initial state—of MoSe2 at 177.2 (plus or minus 9.3) gigapascals (GPa). Graphene is more than five times as elastic. The fracture strength—amount of stretching a material can handle before breaking—was measured at 4.8 (plus or minus 2.9) GPa. Graphene is nearly 25 times stronger.

“The important message of this work is the brittle nature of these materials,” Lou says. “A lot of people are thinking about using 2D crystals because they’re inherently thin. They’re thinking about flexible electronics because they are semiconductors and their theoretical elastic strength should be very high. According to our calculations, they can be stretched up to 10 percent. The samples we have tested so far broke at 2 to 3 percent (of the theoretical maximum) at most.”

Borophene

“Wavy” borophene might be better, according to finding of other Rice University scientists. The Rice lab of theoretical physicist Boris Yakobson and experimental collaborators observed examples of naturally undulating metallic borophene—an atom-thick layer of boron—and suggested that transferring it onto an elastic surface would preserve the material’s stretchability along with its useful electronic properties.

Highly conductive graphene has promise for flexible electronics, but it is too stiff for devices that must repeatably bend, stretch, compress, or even twist. The Rice researchers found that borophene deposited on a silver substrate develops nanoscale corrugations, and due to weak binding to the silver can be exfoliated for transfer to a flexible surface. The research appeared recently in the American Chemical Society journal Nano Letters.

Rice University has been one of the world’s leading locations for the exploration of 1D and 2D materials research, ever since it was lucky enough to get a visionary genius like Richard Smalley to show up in 1976, so we should expect excellent work from people in their department of Materials Science and NanoEngineering (CSNE). Still, this ground-breaking work is being done in labs using tools capable of handling micron-scale substrates, so even after a metaphorical “path” has been found it will take a lot of work to build up a manufacturing roadway capable of fabricating meter-scale substrates.

—E.K.

Multibeam Patents Direct Deposition & Direct Etch

Monday, November 14th, 2016

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By Ed Korczynski, Sr. Technical Editor

Multibeam Corporation of Santa Clara, California recently announced that its e-beam patent portfolio—36 filed and 25 issued—now includes two innovations that leverage the precision placement of electrons on the wafer to activate chemical processes such as deposition and etch. As per the company’s name, multi-column parallel processing chambers will be used to target throughputs usable for commercial high-volume manufacturing (HVM) though the company does not yet have a released product. These new patents add to the company’s work in developing Complementary E-Beam Lithography (CEBL) to reduce litho cost, Direct Electron Writing (DEW) to enhance device security, and E-Beam Inspection (EBI) to speed defect detection and yield ramp.

The IC fab industry’s quest to miniaturize circuit features has already reached atomic scales, and the temperature and pressure ranges found on the surface of our planet make atoms want to move around. We are rapidly leaving the known era of deterministic manufacturing, and entering an era of stochastic manufacturing where nothing is completely determined because atomic placements and transistor characteristics vary within distributions. In this new era, we will not be able to guarantee that two adjacent transistors will function the same, which can lead to circuit failures. Something new is needed. Either we will have to use new circuit design approaches that require more chip area such as “self-healing” or extreme redundancy, or the world will have to inspect and repair transistors within the billions on every HVM chip.

In an exclusive interview with Solid State Technology, David K. Lam, Multibeam Chairman, said, “We provide a high-throughput platform that uses electron beams as an activation mechanism. Each electron-beam column integrates gas injectors, as well as sensors, which enable highly localized control of material removal and deposition. We can etch material in a precise location to a precise depth. Same with deposition.” Lam (Sc.D. MIT) was the founder and first CEO of Lam Research where he led development and market penetration of the IC fab industry’s first fully automated plasma etch system, and was inducted into the Silicon Valley Engineering Hall of Fame in 2013.

“Precision deposition using miniature-column charged particle beam arrays” (Patent #9,453,281) describes patterning of IC layers by either creating a pattern specified by the design layout database in its entirety or in a complementary fashion with other patterning processes. Reducing the total number of process steps and eliminating lithography steps in localized material addition has the dual benefit of reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Furthermore, highly localized, precision material deposition allows for controlled variation of deposition rate and enables creation of 3D structures such as finFETs and NanoWire (NW) arrays.

Deposition can be performed using one or more multi-column charged particle beam systems using chemical vapor deposition (CVD) alone or in concert with other deposition techniques. Direct deposition can be performed either sequentially or simultaneously by multiple columns in an array, and different columns can be configured and/or optimized to perform the same or different material depositions, or other processes such as inspection and metrology.

“Precision substrate material removal using miniature-column charged particle beam arrays” (Patent #9,466,464) describes localized etch using activation electrons directed according to the design layout database so that etch masks are no longer needed. Figure 1 shows that costs are reduced and edge placement accuracy is improved by eliminating or reducing errors associated with photomasks, litho steps, and hard masks. With highly localized process control, etch depths can vary to accommodate advanced 3D device structures.

Fig.1: Comparison of (LEFT) the many steps needed to etch ICs using conventional wafer processing and (RIGHT) the two simple steps needed to do direct etching. (Source: Multibeam)

“We aren’t inventing new etch chemistries, precursors or reactants,” explained Lam. “In direct etch, we leverage developments in reactive ion etching and atomic layer etch. In direct deposition, we leverage work in atomic layer deposition. Several research groups are also developing processes specifically for e-beam assisted etch and deposition.”

The company continues to invent new hardware, and the latest critical components are “kinetic lens” which are arrangements of smooth and rigid surfaces configured to reflect gas particles. When fixed in position with respect to a gas injector outflow opening, gas particles directed at the kinetic lens are collimated or redirected (e.g., “focused”) towards a wafer surface or a gas detector. Generally, surfaces of a kinetic lens can be thought of as similar to optical mirrors, but for gas particles. A kinetic lens can be used to improve localization on a wafer surface so as to increase partial pressure of an injected gas in a target area. A kinetic lens can also be used to increase specificity and collection rate for a gas detector within a target frame.

Complementary Lithography

Complementary lithography is a cost-effective variant of multi-patterning where some other patterning technology is used with 193nm ArF immersion (ArFi) to extend the resolution limit of the latter. The company’s Pilot™ CEBL Systems work in coordination with ArFi lithography to pattern cuts (of lines in a “1D lines-and-cuts” layout) and holes (i.e., contacts and vias) with no masks. These CEBL systems can seamlessly incorporate multicolumn EBI to accelerate HVM yield ramps, using feedback and feedforward as well as die-to-database comparison.

Figure 2 shows that “1D” refers to 1D gridded design rule. In a 1D layout, optical pattern design is restricted to lines running in a single direction, with features perpendicular to the 1D optical design formed in a complementary lithography step known as “cutting”. The complementary step can be performed using a charged particle beam lithography tool such as Multibeam’s array of electrostatically-controlled miniature electron beam columns. Use of electron beam lithography for this complementary process is also called complementary e-beam lithography, or CEBL. The company claims that low pattern-density layers such as for cuts, one multi-column chamber can provide 5 wafers-per-hour (wph) throughput.

Fig.2: Complementary E-Beam Lithography (CEBL) can be used to “cut” the lines within a 1D grid array previously formed using ArF-immersion (ArFi) optical steppers. (Source: Multibeam)

Direct deposition can be used to locally interconnect 1D lines produced by optical lithography. This is similar in design principle to complementary lithography, but without using a resist layer during the charged particle beam phase, and without many of the steps required when using a resist layer. In some applications, such as restoring interconnect continuity, the activation electrons are directed to repair defects that are detected during EBI.

—E.K.

Applied Materials Intros High Res E-Beam Inspection System

Monday, July 11th, 2016

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Applied Materials, Inc. introduced its next-generation e-beam inspection system that offers resolution down to 1nm. This allows users to detect the most challenging “killer” defects that other technologies cannot find, and to monitor process marginality to rapidly resolve ramp issues and achieve higher yields. Called PROVision™, the system offers 3x faster throughput over existing e-beam hotspot inspection tools.

Ram Peltinov, senior director, strategic marketing for the Process Diagnostics and Control Group at Applied Materials, said the development of the new system was driven by a number of new challenges: Structures and defects are now too small for optical resolution; multi-patterning triggers a need for massive measurements; and 3D architectures limit the ability to detect and measure.

“FinFETs are becoming increasingly complex, the multi-patterning creates multiple steps, the DRAM aspect ratios are getting very high and the VNAND is going vertical,” he said. “All these changes are happening in parallel and this creates great opportunity for metrology and inspection,” he said. According to Gartner, the market for e-beam inspection systems has tripled in the last five years, from $81M in 2010 to $241M in 2015.

The system’s high current density (beam current per sampling area) eliminates the sampling/throughput tradeoff of previous systems, allowing the fastest sampling throughput at its 1nm resolution. Imaging capabilities encompass techniques such as see-through, high aspect ratio, 360° topography, and back-scattered electron detection.

“It allows them to capture defects they couldn’t see before,” Peltinov said. The system can detect, for example, epi-overgrowth in FinFETs. “While the epi overgrowth is clearly visible on the PROVision, it’s almost impossible to see in conventional EBI. Without the resolution and the special imaging, it’s very difficult to catch that.”

“They can also increase their sampling with the faster throughput on the most challenging layers. This also helps them reveal process signatures of their most subtle process variation,”  Peltinov added. Massive sampling reveals hidden process trends and “signatures” that help identify sources of abnormalities, and shorten the time to root cause from days to minutes.

Applied Materials Releases Selective Etch Tool

Wednesday, June 29th, 2016

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By Ed Korczynski, Sr. Technical Editor

Applied Materials has disclosed commercial availability of new Selectra(TM) selective etch twin-chamber hardware for the company’s high-volume manufacturing (HVM) Producer® platform. Using standard fluorine and chlorine gases already used in traditional Reactive Ion Etch (RIE) chambers, this new tool provides atomic-level precision in the selective removal of materials in 3D devices structures increasingly used for the most advanced silicon ICs. The tool is already in use at three customer fabs for finFET logic HVM, and at two memory fab customers, with a total of >350 chambers planned to have been shipped to many customers by the end of 2016.

Figure 1 shows a simplified cross-sectional schematic of the Selectra chamber, where the dashed white line indicates some manner of screening functionality so that “Ions are blocked, chemistry passes through” according to the company. In an exclusive interview with Solid State Technology, company representative refused to disclose any hardware details. “We are using typical chemistries that are used in the industry,” explained Ajay Bhatnagar, managing director of Selective Removal Products for Applied Materials. “If there are specific new applications needed than we can use new chemistry. We have a lot of IP on how we filter ions and how we allow radicals to combine on the wafer to create selectivity.”

FIG 1: Simplified cross-sectional schematic of a silicon wafer being etched by the neutral radicals downstream of the plasma in the Selectra chamber. (Source: Applied Materials)

From first principles we can assume that the ion filtering is accomplished with some manner of electrically-grounded metal screen. This etch technology accomplishes similar process results to Atomic Layer Etch (ALE) systems sold by Lam, while avoiding the need for specialized self-limiting chemistries and the accompanying chamber throughput reductions associated with pulse-purge process recipes.

“What we are doing is being able to control the amount of radicals coming to the wafer surface and controlling the removal rates very uniformly across the wafer surface,” asserted Bhatnagar. “If you have this level of atomic control then you don’t need the self-limiting capability. Most of our customers are controlling process with time, so we don’t need to use self-limiting chemistry.” Applied Materials claims that this allows the Selectra tool to have higher relative productivity compared to an ALE tool.

Due to the intrinsic 2D resolutions limits of optical lithography, leading IC fabs now use multi-patterning (MP) litho flows where sacrificial thin-films must be removed to create the final desired layout. Due to litho limits and CMOS device scaling limits, 2D logic transistors are being replaced by 3D finFETs and eventually Gate-All-Around (GAA) horizontal nanowires (NW). Due to dielectric leakage at the atomic scale, 2D NAND memory is being replaced by 3D-NAND stacks. All of these advanced IC fab processes require the removal of atomic-scale materials with extreme selectivity to remaining materials, so the Selectra chamber is expected to be a future work-horse for the industry.

When the industry moves to GAA-NW transistors, alternating layers of Si and SiGe will be grown on the wafer surface, 2D patterned into fins, and then the sacrificial SiGe must be selectively etched to form 3D arrays of NW. Figure 2 shows the SiGe etched from alternating Si/SiGe stacks using a Selectra tool, with sharp Si corners after etch indicating excellent selectivity.

FIG 2: SEM cross-section showing excellent etch of SiGe within alternating Si/SiGe layers, as will be needed for Gate-All-Around (GAA) horizontal NanoWire (NW) transistor formation. (Source: Applied Materials)

“One of the fundamental differences between this system and old downstream plasma ashers, is that it was designed to provide extreme selectivity to different materials,” said Matt Cogorno, global product manager of Selective Removal Products for Applied Materials. “With this system we can provide silicon to titanium-nitride selectivity at 5000:1, or silicon to silicon-nitride selectivity at 2000:1. This is accomplished with the unique hardware architecture in the chamber combined with how we mix the chemistries. Also, there is no polymer formation in the etch process, so after etching there are no additional processing issues with the need for ashing and/or a wet-etch step to remove polymers.”

Systems can also be used to provide dry cleaning and surface-preparation due to the extreme selectivity and damage-free material removal.  “You can control the removal rates,” explained Cogorno. “You don’t have ions on the wafer, but you can modulate the number of radicals coming down.” For HVM of ICs with atomic-scale device structures, this new tool can widen process windows and reduce costs compared to both dry RIE and wet etching.

—E.K.

Pattern Matching Tackles IC Verification and Manufacturing Problems

Monday, June 6th, 2016

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Mentor Graphics Corporation announced that customers and ecosystem partners are expanding their use of Calibre Pattern Matching solution to overcome previously intractable IC verification and manufacturing problems. The solution is integrated into the Mentor® Calibre nmPlatform solution, creating a synergy that drives these new applications at IC design companies and foundries, across multiple process nodes.

Calibre Pattern Matching technology supplements multi-operational text-based design rules with an automated visual geometry capture and compare process. This visual approach is both very powerful in its ability to capture complex pattern relationships, and to work within mixed tool flows, making it much easier for Mentor customers to create new applications to solve difficult problems. Because it is integrated into the Calibre nmPlatform toolset, the Calibre Pattern Matching functionality can leverage the industry-leading performance and accuracy of all Calibre tools and flows to create new opportunities for design-rule checking (DRC), reliability checking, DFM, yield enhancement, and failure analysis.

“Our customers count on eSilicon’s design services, IP, and ecosystem management to help them succeed in delivering market-leading ICs,” said Deepak Sabharwal, general manager, IP products & services at eSilicon. “We use Calibre Pattern Matching to create and apply a Calibre-based yield-detractor design kit that helps identify and eliminate design patterns that impact production ramp-up time.”

Since its introduction, use models for Calibre Pattern Matching technology have rapidly expanded, solving problems that were previously too complex or time-consuming to be implemented. New use cases include the following:

  • Physical verification of IC designs with curved structures—for analog, high-power, radio frequency (RF) and microelectromechanical (MEMS) circuitry—is extremely difficult with products designed to work with rectilinear design data. Calibre customers are automating that verification using a combination of Calibre Pattern Matching technology and other Calibre tools for much greater efficiency and accuracy, especially when compared to manual techniques.
  • Calibre Pattern Matching technology can be used to quickly locate and remove design patterns that are known or suspected of  being difficult to manufacture (“yield detractors”). Foundries or design companies create libraries of yield detractor patterns that are specific to a process node or a particular design methodology. Samsung Foundry used this approach in its Closed-Loop DFM solution to help its customers ramp to volume faster, and reduce process-design variability.
  • Some customers use Calibre Pattern Matching technology with Calibre Auto-Waivers™ functionality to define a specific context for waiving a DRC violation. This enhancement allows for automatic filtering of those violations for significant time savings and improved design quality.

“To help our customers create manufacturing-ready designs, we use Calibre Pattern Matching to create and use a yield detractor database to fix most of the litho hotspots in the block level. Then we perform fast signoff DFM litho checking at the chip level using an integrated solution with Calibre Pattern Matching and Calibre LFD” said Min-Hwa Chi, senior vice president, SMIC. “By offering a solution for manufacturability robustness that is built on the Calibre platform, we are seeing ready customer adoption of SMIC’s DFM solution.”

With the Calibre Pattern Matching tool, design companies can now optimize their physical verification checking to their unique design styles. The tool is easy to adopt because it doesn’t rely on expertise in scripting languages. Instead, any engineer can readily define a visual pattern that captures the designer’s expertise in the critical geometries and context for that configuration.

“With the growing adoption of Calibre Pattern Matching technology, Mentor continues to help our customers address increasing design complexity, regardless of the process node they are targeting,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “By incorporating the Calibre Pattern Matching tool, the Calibre platform becomes an even more valuable bridge between design and manufacturing for the ecosystem.”

At the 2016 Design Automation Conference, Mentor has a Calibre Pattern Matching presentation on Tuesday, June 7 at 3PM in the Mentor booth #949. Register for the session using the registration form.

https://www.mentor.com/events/design-automation-conference/schedule

New Tungsten Barrier/Liner, Fill Processes Reduce Resistance and Increase Yield

Friday, June 3rd, 2016

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By Pete Singer, Editor-in-Chief

Today’s most advanced chips pack two billion transistors on a die size of 100 mm2. Considering transistors are three terminal devices, that equates to six billion contacts to those transistors, which connect to 10-15 Layers of stacked wiring. Although the wiring is copper, the contacts at the transistor level and the so-called local interconnect level just above the contact level are made of tungsten (Figure 1). Although tungsten has slightly higher resistance than copper, the danger of copper contamination killing the transistor is such that tungsten is still used.

Figure 1. The contact (black area) is the first, smallest, most critical connection between the transistor and interconnect wiring. Source: TECHINSIGHTS

Two looming problems are that contact resistance is going up, to the point where it will soon be higher than that of the transistor (Figure 2). Yield is also at risk since just one bad contact can cause entire portions of the chip to fail. “Not only are there a lot of these contacts, they’re very challenging to make because they are so small and getting even smaller with each node,” said Jonathan Bakke, Global Product Manager, Transistor and Interconnect Group, Applied Materials.

Figure 2. At the 10nm node and beyond, contact and plug resistance is expected to rise exponentially and dominate.

Applied Materials recently launched two new products aimed at reducing contact resistance and improving yield in tungsten contacts. The Applied Endura® Volta™ CVD W product results in a new tungsten-based material that serves as both a barrier and a liner, enabling the lower resistance W fill to be three times wider than in traditional process flows. The end result is an increase of up to 90% in contact resistance. The Applied Centura® iSprint™ ALD/CVD SSW (seam-suppressed tungsten) product achieves bottom-up gap fill in tungsten contact CVD processes, reducing seams and voids, which increases yield.

The traditional process flow to from a contact has been to deposit a layer of titanium to form a silicide layer by reacting with the silicon, followed by a TiN barrier. This barrier film prevents the diffusion of fluorine into the silicon of the transistor from the tungsten hexafluoride (WF6) used to deposit the subsequent tungsten contact fill. Because tungsten doesn’t grow directly on TiN, a seed layer of W is typically deposited by ALD before the WF6 CVD bulk fill.

Two challenges associated with this approach is that the barrier and liner have not scaled – they have been made as thin as possible, but they’ve reached a limit. The TiN barrier is typically around 30-40Å and the liner film another 20Å. As a result, the volume of the overall plug made of the more desirable, lower resistance W is reduced. “The TiN and tungsten based liner are both high resistance layers. The more volume they occupy, the more they contribute to resistance,” Bakke said.

The second challenge is that, because the W CVD process results in a conformal fill, where all sides grow at the same rate, a seam is often formed in the middle of the contact. Or, even worse, the top closes before the W completely fills the contact hole, resulting in a void. Both seams and voids can be exposed or breached during the subsequent chemical mechanical planarization (CMP) step. “The contacts or local interconnects are becoming much smaller with each node and they’re getting more challenging to fill with low resistance material and without seams or voids,” Bakke said. Figure 3 shows common problems with resistance and yield.

Figure 3: Barriers and liners don't scale, leaving less room for low resistance W fill. Seams and voids can cause yield problems.

Seams and voids can lead to yield problems such as overly high contact resist or even open contacts. If even a few of the 6 billion contacts on a chip fail, there can a big impact on yield. One study (Figure 4), shows that even at the 20nm node, one defect in a billion can lead to a yield loss of 15% or more. “This tells you that you really have to have perfect gap fill. If one contact goes, it can knock out an entire portion of the device and make it inoperable,” Bakke said.

Figure 4. Source: Nvidia

Enter the Applied Endura® Volta™ CVD W and the Applied Centura® iSprint™ ALD/CVD SSW (seam-suppressed tungsten).

A process has been developed for the Endura – Applied’s platform for metal deposition, including PVD and CVD – to deposit a tungsten-based CVD film that serves as both the barrier layer and the liner layer. At around the 30Å thickness that would be typical of just the barrier, and it’s as effective a barrier as TiN. “We’re doing materials engineering to create the first new liner for tungsten plug in 10 years,” Bakke said. This means more of the volume of the contact consists of the lower resistivity W fill (Figure 5). “You can actually triple the tungsten fill width at the 15 nm node. You get a lot more low-resistance material in there. Beyond that, it’s a simpler process flow, by removing the one layer, the liner,” Bakke added.

Figure 5

Figure 6 shows how the new W-based barrier/liner compares to the standard flow. The tungsten-based film is 75% lower in resistitivity that the TiN (left). At thicknesses which are relevant for the 10nm node, an 80% reduction in total stack resistivity is seen (right).

Figure 6

Perhaps even more important is the contact resistance, as shown in Figure 7, which charts contact resistance vs critical dimension. “By the time you’re getting to the 10 and 7nm node thicknesses, you actually have a big drop in resistivity up to about 90% reduction in resistance at the 7nm node thicknesses,” Bakke explained.

Figure 7

One reason why plug resistance is becoming more important is indicated by the orange line in Fig. 7, which shows silicide contact resistance. “For a long time, the silicide was the big contributor to the transistor contact total resistance. Manufacturers spent a lot time trying to decrease that resistance as they scaled. There’s a cross-over point (blue line) where the plug starts become of higher resistance than the contact. We need to focus on bring the plug resistance back down so it’s not the major contributor to the total resistance,” Bakke said.

Figure 8 shows the end result, with a clean interface between both the tungsten and underlying tungsten layer. “The Volta W adheres very well to dielectric sidewalls. And the W fill is able to deposit on the Volta W and give good gap fill performance,” said Bakke. “It’s also able to survive all the post-processing steps, such as CMP and deposition of copper.”

Figure 8. Degas, clean and Volta W are integrated in the Endura platform.

The Applied Centura® iSprint™ ALD/CVD SSW process uses a “special treatment” after the liner (or barrier/liner in the case of Volta W) to suppress growth on the field and induce growth in a bottom-up fashion (Figure 9). This bottom-up growth eliminates seams and voids. “Because you have a more robust fill, you get an improved yield because you don’t breach the contact or local interconnect during the CMP step,” Bakke said. “This is the first bottom-up tungsten CVD in high volume manufacturing,” he added.

Figure 9. Bottom-up fill is shown in a diagram (top) and in an actual structure.

Bakke wouldn’t say what the special treatment was, but a patent search revealed a possible approach, involving activated nitrogen where the activated nitrogen is deposited preferentially on the surface regions.

Rhines Expounds on the Deconsolidation of the Semiconductor Industry

Wednesday, April 27th, 2016

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By Jeff Dorsch, Contributing Editor

“By 2020, we are all going to work for the same company,” Wally Rhines, chairman and chief executive officer of Mentor Graphics, said Tuesday morning (April 26) in his keynote presentation at Mentor’s U2U user conference in Santa Clara, Calif.

Taking “Merger Mania” as his theme, the veteran electronic design automation and semiconductor executive reviewed the merger-and-acquisition activity of 2015, some of which is extending into this year. Rhines noted that several of the big acquiring companies in last year’s wave of industry consolidation had names beginning with the letter “M,” while some of the acquired chip enterprises had names beginning with the letter “A.” That, he joked, was the genesis of “M&A” in 2015.

On a more serious note, the Mentor CEO challenged the conventional wisdom that the industry experienced unprecedented deal-making and combination in 2015. The number of deals involved, 30, wasn’t a record, he said. It was the “magnitude” of valuations in those transactions, with a number of multibillion-dollar acquisitions, he added.

The top 10 semiconductor suppliers in the world have changed dramatically since the 1950s, as the industry has transitioned from germanium transistors to silicon-based integrated circuits made with a bipolar process, metal-oxide-semiconductor memory chips, memories/microprocessors, and system-on-a-chip devices, according to Rhines.

The industry market share of the top 50 chip companies has actually declined for many years, through 2014, he noted. “We’re still on a deconsolidation path,” Rhines asserted. “The dynamics of the industry change.”

While the industry was selling 50 percent of its chips for computing applications a decade ago, and 25 percent for communications, the trend has lately shifted, with communications overtaking computers as the leading application, although the line between communications and computing is getting blurrier, Rhines noted.

“Why the acceleration in mergers?” Rhines wondered. The chief factors generally credited are economies of scale, financial leverage, and regulatory/government mandates, he listed.

Despite all the combinations over the years, there is scant evidence that mergers always mean higher profit margins, compared with revenue figures, Rhines said. “There is no correlation between size and profits,” he noted. “It’s not an automatic formula for success. Maybe scale isn’t the answer.”

A more compelling reason for the wave of mergers is “very cheap money,” with historically low rates on corporate loans, Rhines noted. Tax advantages, especially on tax-inversion deals, seem to be fading as an incentive to merge, as the federal government is making it more difficult for large corporations to move their headquarters out of the United States and minimize their tax obligations to the U.S., according to Rhines.

That brings in the consideration of regulations and government mandates. China is engaged in a five-year program to create “greater self-sufficiency” for its domestic semiconductor industry, the Mentor CEO said. Instead of directly subsidizing the growth of semiconductor manufacturers and chip-related suppliers, China’s central government is taking equity stakes in private-equity firms that are making investments in the semiconductor industry, sometimes seeking to acquire companies in the U.S. and around the world, or to take an ownership stake in key companies.

Research and development spending by semiconductor companies goes up and down depending on industry revenue, yet it generally remains flat as a percentage of revenue – typically around 14 percent of revenue, according to Rhines.

Still, “long-term interest rates can’t stay low forever,” he concluded. “Merger mania will be limited.”

In an interview following his keynote, Rhines expounded on the theme of the learning curve – a concept that encompasses Moore’s Law and other observations of technological change. In addition to talking about the learning curve in his keynote, Rhines also wrote about in a recent blog post.

Moore’s Law presents a “limited set of knobs to turn,” he observed. For years, “the most productive thing to do is shrink” the dimensions of ICs, he said. While the demise of Moore’s Law has long been predicted, “the cost per switch/transistor will always be going down,” he added. “You will always see an improvement.”

The Internet of Things is widely touted as the next market to boost the fortunes of the semiconductor industry. IoT could force the industry to “improve enough to enable another application, like wireless,” Rhines said.

In general, the industry is facing substantial manufacturing challenges in getting down to the 16/14-nanometer process node and smaller dimensions. “Every generation has a new physics problem to solve,” Rhines observed. “Complexity grows.”

Chip designers and manufacturers are now dealing with electromigration issues and thermal problems, he noted. EDA is taking on these challenges while also pivoting to the wider considerations of system design, rather than chip or board design, Rhines said.

“Forty percent of our revenue comes from system design,” the Mentor CEO said. Designing systems for automotive vehicles, military/aerospace systems, medical equipment, and other areas represents a $2.5 trillion market in total, compared with about $350 billion for semiconductors, on an annual basis.

Faced with declining revenue and profitability in the 2016 fiscal year, Mentor Graphics offered a voluntary early retirement program for veteran employees, and dozens of them took the buyout benefits, Rhines noted. This represented “a forcible evolution of the company,” he said. “We were going to lose a significant amount of corporate learning.”

While somewhere between 110 and about 200 employees took early retirement, Mentor actually increased its headcount last year, from 5,558 full-time positions as of January 31, 2015, to around 5,700 positions on January 31, 2016.

What about retirement for Rhines, who will celebrate his 70th birthday in November of this year? “I haven’t actually thought about it,” he said in the interview. While carefully noting, “I serve at the will of the board,” Rhines added, “I’m not looking for another job.” He still has the “energy level” for all those red-eye flights to meet with customers, he said. “I don’t play golf,” Rhines commented. “I like a lot of pressure, crises. I love the relationships I have with customers, employees.”

The Rhines keynote was followed Tuesday morning by a keynote from Zach Shelby, vice president of marketing for the Internet of Things at ARM Holdings, who spoke on “Driving Beyond IoT.”

Shelby noted the history of computing, communications, and networking in recent decades. “It takes an ecosystem,” he asserted. ARM, he said, is not just a fabless semiconductor company; “we’re silicon-less,” he said, since ARM is involved in developing and licensing technology for other companies to use. The IC design company works with operators of cloud services, network operators, system integrators and end-users around the world, according to Shelby.

The industry trend is going “from embedded to connected, reaching millions of developers,” he said.

While some see automotive vehicles as “expensive mobile phones,” Shelby said, “They’re becoming autonomous drones.” He added, “The auto is the ultimate intelligent connected device.”

Rhines and Shelby later participated in an afternoon panel session titled “Ripple or Tidal Wave: What’s Driving the Next Wave of Innovation and Semiconductor Revenue?” Also on the panel were James Hogan of Vista Ventures, Brad Howe of Altera, and Kelvin Low of Samsung Semiconductor.

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