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Posts Tagged ‘SPIL’

Blog review September 8, 2014

Monday, September 8th, 2014

Jeff Wilson of Mentor Graphics writes that, in IC design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Is 3D NAND a Disruptive Technology for Flash Storage? Absolutely! That’s the view of Dr. Er-Xuan Ping of Applied Materials. He said a panel at the 2014 Flash Memory Summit agreed that 3D NAND will be the most viable storage technology in the years to come, although our opinions were mixed on when that disruption would be evident.

Phil Garrou takes a look at some of the “Fan Out” papers that were presented at the 2014 ECTC, focusing on STATSChipPAC (SCP) and the totally encapsulated WLP, Siliconware (SPIL) panel fan-out packaging (P-FO), Nanium’s eWLB Dielectric Selection, and an electronics contact lens for diabetics from Google/Novartis.

Ed Koczynski says he now knows how wafers feel when moving through a fab. Leti in Grenoble, France does so much technology integration that in 2010 it opened a custom-developed people-mover to integrate cleanrooms (“Salles Blanches” in French) it calls a Liaison Blanc-Blanc (LBB) so workers can remain in bunny-suits while moving batches of wafers between buildings.

Handel Jones of IBS provides a study titled “How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales” that concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics.

Gabe Moretti of Chip Design blogs that a grown industry looks at the future, not just to short term income.  EDA is demonstrating to be such an industry with significant participation by its members to foster and support the education of its future developers and users through educational licenses and other projects that foster education.

Blog review February 3, 2014

Monday, February 3rd, 2014

Ira Feldman provides an interesting perspective on last month’s SEMI Industry Strategy Symposium. He notes that numerous speakers including Jon Casey (IBM) and Mike Mayberry (Intel) stated that scaling will continue below the 10 nm process node perhaps to 5 or 7 nm. However, the question raised by both the speakers and the audience was at what cost will this scaling be achieved.

“Long live the FinFET,” says Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc. In this blog post, he describes how designers will have to seek out new tools and methodologies to overcome FinFET design challenges. One example is the adoption of giga-scale parallel SPICE simulators to harness circuit simulation challenges in FinFET designs. Traditional SPICE simulators don’t have the capacity and lack sufficient performance to support FinFET designs, while FastSPICE simulators likely will not meet accuracy requirements, he writes.

Adele Hars of Advanced Substrate News reports that STMicroelectronics will soon be announcing a “major foundry player” that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company’s Q4 and FY13 presentation in Paris on January 28th.

Phil Garrou finishes up his review of the IMAPS 2013 meeting, with an analysis of Xilinx/SPIL results from their 2.5D 28nm FPGA program, a review of the Copper TSV work presented by Nanyang/IME, Canon’s FPA-5510iV and FPA-5510iZ TSA steppers designed to support high density processes and the implementation of 2.5 & 3D technology, and a report on the embedded technology being developed by AT&S.