By Mark LaPedus

Extreme ultraviolet (EUV) lithography is late for the 10nm node and could possibly miss the window for that insertion point, according to a lithographer at a panel discussion at last week’s SPIE/BACUS Photomask Technology conference in Monterey, Calif.

The IC industry has various EDA, lithographic, photomask and other solutions in place If EUV remains delayed, but the challenges will continue to mount in the multi-patterning era, according to panelists at the event. The panel was entitled “Will optical patterning solutions be ready if EUV lithography continues to be delayed?”

During the panel and the SPIE/BACAS event in general, there were rumblings that EUV is delayed — again. Analysts believe that EUV may be too late for the 14nm node, but now there are growing fears that the technology is in danger of missing the 10nm window.

“It’s clear that EUV will be late for our 10nm node,” said Allen Gabor, senior patterning program manager in advanced lithography at IBM, during the panel.

In a brief interview after the panel, Gabor said IBM has not totally dismissed or counted out using EUV for the 10nm node. “If it is ready, we will use it,” he said, without elaborating.

During the panel, he presented a slide of what appeared to be IBM’s lithography roadmap. At 10nm, EUV and 193nm immersion are still in the mix. Other leading-edge chipmakers, including GlobalFoundries, Intel, Micron, TSMC, Samsung, SK Hynix, Toshiba and others, have not publically indicated that EUV will be late for 14nm or 10nm.

The sole EUV tool supplier, ASML Holding, is expected to ship its NXE:3300B, a full-blown, 13.5nm EUV production tool, later this year. In January, ASML promised an acceptable throughput of 69 wafers an hour for the tool.

Amid ongoing delays for the EUV light source from Cymer, ASML in July lowered its targets and promised a throughput in the “30ish” range in terms of wafers per hour this year. It’s possible that ASML may not deliver 70 wafers per hour for the machine until 2014, according to C.J. Muse, an analyst with Barclays Capital, in a recent research note.

Intel’s recent decision to invest as much as $4.1 billion in ASML has raised overall confidence levels in EUV lithography. TSMC and Samsung have also invested in the Dutch-based lithography giant. ASML has said it needs to reach 250 Watts of average source power to achieve the 125 wph throughputs sought by its early customers—roughly 10x today’s situation.

The IC industry hopes that EUV will be ready at 14nm. But if EUV misses 14nm, and is inserted at 10nm, it still could be an expensive solution. Since EUV has a wavelength of 13.5nm, EUV will require some form of a double-patterning scheme at 10nm, IBM’s Gabor said.

In any case, leading-edge chipmakers may be forced to extend 193nm immersion much further than previously expected. Chip makers will also utilize a double-patterning scheme, such as sidewall image transfer or self-aligned double patterning, litho-etch-litho-etch (LELE), or self-aligned vias, he said.

“Without EUV, scaling beyond the 10nm node will require frequency multiplication,” he said. In that scenario, vendors may have to resort to self-aligned quadruple pattering or directed self-assembly (DSA), he said.

Impact on mask makers

The shift towards the multi-patterning era has some major ramifications for the EDA, photomask and other industries. EDA houses, for example, are readying their multi-patterning tools. But verification costs and optical proximity correction (OPC) run times are expected to soar at the 10nm and 7nm nodes.

“The total run times scales in accordance with the number of patterning steps,” said Yuri Granik, chief scientist within the Design to Silicon Division at Mentor Graphics. “Double patterning alone and SRAFs will increase OPC run times.”

There’s good and bad news for photomask makers and associated tool vendors. In traditional single exposure processing, an IC maker uses one mask. In doubling patterning, an IC maker uses two separate masks to design a device, which boosts production costs. Triple-pattering will require three masks and so on.

In double patterning (two separate mask sets), photomask makers could write the layers in sequential steps with one e-beam tool. In a more likely scenario, a mask maker would simultaneously utilize two e-beams to process each mask to speed up the process.

In multiple patterning, mask makers could see their capital costs soar, as they may end up buying twice as many e-beam tools than before. On a positive note, e-beam makers are seeing robust demand, said Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks.

The trouble is that e-beams are not keeping up with Moore’s Law.  From 2001 to 2005, write times were constant, averaging some 8 hours per mask set, Kalk said. But from 2007 to 2012, the average write times rose to about 10 hours per mask set, he said. “The write times will increase dramatically over the decade,” he said during the panel.

Aki Fujimura, chairman and chief executive of D2S, also painted a sobering picture. E-beam throughputs are increasing by a factor of only one-half, but data volumes are increasing by a factor of two, and mask complexity is jumping by 2x to 5x, he said during the panel.

This week, D2S rolled out one solution to the problem. It introduced TrueMask MDP, a model‐based mask data preparation (MB‐MDP) technology. Developed to address mask designs at 20nm and beyond, TrueMask MDP reduces e-beam shot count to cut mask write times by 20% to 30%.

Still, there is a crying need for multi-beam mask writers to boost write times. One vendor, Austria-based IMS, has been developing a so-called electron multibeam Mask Exposure Tool (eMET) for the fabrication of leading-edge masks and templates. The company has completed a concept 50keV eMET. Through a programmable aperture plate, the eMET would provide 264,144 programmable beams with 20nm and 10nm beam sizes.

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has joined IMS’ multibeam mask writer development collaboration. Earlier this year, IMS said Dai Nippon Printing Co. Ltd. (DNP) joined a collaborative effort, backed by Intel and Photronics, to advance IMS’s electron multibeam mask writer tool.

Advantest and Vistec are also developing similar multi-beam tools. It’s unlikely that the multi-beam tools will be ready at 10nm. “They should be ready for 7nm,” Toppan’s Kalk said.

By Marc D. Levenson

Does the transition to 450mm wafers offer the ultimate opportunity to switch to maskless lithography (ML2)? That was the suggestion made by Burn Lin, senior director of micropatterning at TSMC in his keynote for the SPIE Alternative Lithography Conference in San Jose Feb. 14. The 450mm transition would appear to require expensive development of a variety of patterning tools and resists if a conventional mix-and-match strategy were employed. Since multi-electron beam lithography can be used to write any layer, one 450mm e-beam direct-write tool could pattern them all, and for 30% lower cost at any production volume. Only one machine would have to be engineered and only a few resists formulated.

The architecture of Lin’s tool would be similar to a multi-column version of KLA-Tencor’s ReBL system, with several wafers on a rotating stage and up to 36 columns, each supporting one million independent beams. Direct write with continuous stage motion on all levels would allow devices to break out of the standard 26 x 33mm field, with consequent efficiency improvements. The issue, as always in electron beam lithography, would be throughput. Lin claimed that could be addressed by scaling the number of columns and stages.  Mass production would reduce tool cost to $500,000 per wafer per hour. Lin claimed that by the time 450mm came along, the CD would be 10nm or below, making his suggested ML2 architecture the least challenging and most economical of the available options.

Other advocates of ML2 and alternative lithographies seemed less visionary. The KLA-Tencor presentations on ReBL emphasized the steps needed to re-target the DARPA-funded 45nm program towards commercial viability at 16nm or so in 2015. Regina Freed described how returning to linear stage motion reduced risk and complexity with the lower stage velocity needed for 1nm CDU and overlay at 16nm. There still could be 36 columns and the throughput target  would be 100 wph.

Mark McCord of KLA-Tencor described the hardware evolution towards high-volume manufacturing (HVM). Going to linear stages simplified the data channel, allowing re-use of data, but still required a 6 Gb/s channel  for each column. The key element of the reflective million pixel design is the Digital Pixel Generator (DPG), which consists of a 248×4096 CMOS shift register underlying a 1.6mm MEMS electron lens array. McCord showed that the first CMOS chips are now working, producing a checkerboard pattern that was focused onto the wafer plane and scrolled at stage speed to facilitate time domain integration (TDI) of the exposure. At designed demagnification, the pixels would be 6nm and edges would be placed to <1nm by using 31 different dose levels. If all goes well, a TDI-exposed wafer would appear soon, and the end of 2012 would see a 100kV 100X demagnification machine with 4 wafers and four 4^th generation columns working simultaneously to yield 4-8 wafers/hour using 30mC/cm² resist.

E- Beam Initiative

At the annual E-Beam Initiative lunch Managing Director Aki Fujimura noted that his organization is an educational platform for all electron-beam applications with 42 member companies, and open to all. In 2012, he predicted that the design for e-beam program (DFeB) would demonstrate mask-CD uniformity improvement on the first full-chip model based mask data preparation (MB-MDP) example. Ryan Pearman of D2S described how MB-MDF facilitated the use of overlapping circular shots to draw curved and diagonal mask features with better edge definition and uniformity. Both shot count and edge placement errors are reduced when circles replace rectangles stitched together at corners, according to Pearman.

Mike Smayling of Tela Technologies described how e-beam lithography could be used for the tiny and difficult “cut” operations in proposed 11nm complimentary lithography. In this system, proposed by Yan Borodowski of Intel and already being used by that company, all circuit features begin as linear and uniform line-and-space gratings. The gratings are then cut into useful circuit elements by subsequent exposures. The problem has been that up to 5 additional optical exposures would be needed to make all necessary circuit geometries because of the fundamental ~80nm limit on the minimum resolved pitch of each optical exposure.

Complementary Lithography process with 193nm immersion lithography. Different colors denote each of the 4 cut-mask exposures. (Courtesy Intel)

Smayling pointed out that an e-beam system could write all of the cuts at once, using Tela’s patented system, which would be much faster than writing the entire pattern. No e-beam system has yet been optimized for this specialized application, but he showed an example of an 11nm grating with cuts made using a Vistec electron lithography system at Cea-Leti .

Later in the conference, Kenji Abe described more   esthetic 22nm and 11nm line-and-cut results achieved on a multi-column cell projection prototype by a team from eBI member Advantest and TEL. In the first stage, the line grating was written by TEL’s self aligned double or quadruple patterning process. Then one beam of the Advantest MCC-POC EdBW tool cut line ends with 5nm overlay accuracy using either a positive or negative tone process. Development etching and subsequent processing resulted in controllable line end spacings down to 13nm. Abe pointed out that such a tool could cut the gate and M1 patterns anticipated for the 11nm node. Other papers from Advantest recommended design and resist innovations that would facilitate EbDW with character projection. The goal is 100 WPH at the 14nm node in a 150 beam, 10 cluster system with 100B shots/wafer, and 75mC/cm² resist. The drastic shot reduction required may first prove feasible in complementary lithography.

SPIE 2012 AL EUVL Conference Review

By M. David Levenson

The top concerns for advocates of EUV Lithography now involve the mask or its lagging infrastructure, and so it was appropriate that the 2011 SPIE Photomask Technology (BACUS) Conference concluded with a special session entitled, “Is it too late to panic?  EUV is Real!”

According to session organizer Frank Abboud of Intel, the purpose was to highlight how the total mask paradigm change required by the adoption of reflective EUVL masks with 1nm precision would create new opportunities for maskmakers and their suppliers. Other speakers were not so sanguine. Defect-free EUV masks will be needed for volume manufacturing in 2014, but today are impossible, they claimed.

Bill Arnold, chief scientist of ASML, spoke first at the session, pointing out that alternatives to EUVL are not compelling. The 15nm half-pitch (hp) word lines needed soon for NAND flash memories will need 17 process steps (and four masks) if implemented using 193nm immersion exposure and quadruple patterning. Such complex methods cannot be supported by NAND flash pricing.

According to Arnold, ASML has built six NXE:3100 1^st generation EUVL scanners and has shipped three to customers. They have demonstrated useable process windows at 21nm hp, and have printed 18nm hp structures using a slow (70mJ/cm²) inorganic resist with dipole illumination. Future ASML tools will have larger numerical apertures and fancier illumination options, facilitating shrinks to the 8nm node in 2018 and perhaps beyond – if masks are available – Arnold said.

Throughput and line edge roughness remain issues, but secondary to defect-free mask yield. According to Arnold, the first installed machines produce only 5-6 wph, but ASML is working with three suppliers of EUV sources to upgrade power and believes it is on track to meeting current targets. There is a trade-off involving resist sensitivity, resolution and line edge roughness. Low sensitivity resists give lower throughput but better resolution and edge roughness. So, the resist chemists have to improve their products, too.

Brian Haas

Brian Haas, vice president and general manager of KLA-Tencor’s Reticle & Photomask Inspection Division (RAPID),
pointed out that the industry consensus was all in favor of EUVL in 2008, but the R&D decisions made recently by semiconductor manufacturers have emphasized alternatives such as multiple patterning and e-beam direct write. That perceived diminution in resolve has discouraged suppliers of the very mask making, inspection and repair technologies that are needed for EUVL success. Haas pointed out a very clear chicken and egg conundrum: If the EUVL wafer stepper throughput stays low (and the chip yield lower), few masks will be ordered and the market for mask making tools will be tiny. Mask tool makers won’t even recover the NRE needed to develop those few unique tools and so won’t build them, he argued.

On the other hand, if EUV stepper throughput exceeds 150 good wafers per hour in actual production, EUVL will be cost-effective for most manufacturing, and many masks will be ordered. The market for KLA-Tencor’s 7XX Series Actinic Inspection Tools will be huge and Haas’s RAPID Division will thrive even with affordable prices. So, where will it begin? Haas suggested an initial target of 80 wph for high-volume manufacturing in 2020. The later that throughput is achieved, the higher the costs of achieving it. According to Haas, the industry needs a credible economic model for EUVL infrastructure and the resolve to persist in it.  Haas concluded, “EUVL is an economic imperative.”   He suggested the industry just needs to “man up.”

Oliver Kienzle, managing director of Carl Zeiss Semiconductor Metrology Systems, described how his company (which is already making the optics used in the ASML EUV steppers) is working to solve the EUV mask defectivity problem. They are developing an EUV aerial image metrology system (AIMS) based on an existing discharge plasma source (with adaptive optics to correct for its wobble) that will review 50 prospective defect sites an hour by simulating EUV stepper imaging.

Kienzle predicted that the first tool would be shipped in 3Q2014. If defects are found to be printable, the Zeiss MeRit HR 32 repair system (which includes an in-situ AFM) can deposit or ablate the absorber to correct the problem. Even phase-shifts due to substrate bumps can be “repaired” though a compensating edge profile change, Kienzle claimed. Of course an EUV-AIMS would then be needed qualify the repaired mask.

Since EUV masks may never have pellicle protection, repeated qualifications will be needed to avoid wasted stepper time due to contamination and soft defects. Sheng-Ji Chin of TSMC pointed out that test wafer printing is 50X too slow and expensive. He suggested that in-building EUV mask shops might be a partial solution until the EUV-AIMS actually becomes available.

Hiraota Morimoto of Toppan (whose mask facilities are located outside customer fabs) was upbeat about EUVL masks for the 2x nm and 1x nm nodes. He pointed out that mask inspection had completely changed because only reflected radiation inspection was now possible. Nevertheless some DUV inspection tools proved adequate for first-generation EUV masks, even finding phase defects 1.2nm high with diameters around 50nm. If existing DUV equipment can be used, producing 1 EUVL mask/month would be economic break even, but more than 20/month would be needed to justify dedicated actinic tools, according to Morimoto. In conclusion, he predicted that defect-free masks would be available in 2013-14, but seemed to joke about their affordability.

Byung-Gook Kim of Samsung was upbeat on the prospects for using EUV to make 22nm DRAMs, based on experience with one of the first EUVL steppers to be delivered. His main concern was the source, rather than the mask. Kim pointed out that the phase defects all result from bumps on the substrate surface, under the multi-layer reflector, and thus they can be (in principle) polished away or hidden. Two existing inspection tools can locate the ones likely to print – those larger than 20nm. Fewer than 10 percent of the blank defects actually print, Kim reported.  Pattern defects are different, but can be found at 22nm and repaired. DRAM redundancy helps yield, which is at 88% of the targeted value now. He predicts that masks with one printable defect per plate will be available in late 2012 and effectively defect free DRAM masks will appear by the second half of 2013. That, however, assumes that multilayer (phase) defects are reduced by a factor of 100 to no more than 2 per blank.

So, the consensus appeared to be that at present it is not too late to panic, at least not about the technology. Even if EUVL is delayed again, alternative methods will take the mask making and semiconductor industries to the next node or two. EUV mask quality is improving. The economics, however, is more problematic. If defect-free EUV masks can be delivered in volume without respins in 2014, then EUVL will be competitive. If not, it will be too late to panic.

By David Lammers

With customer interest in EUV lithography accelerating, Applied Materials will introduce its Tetra EUV mask etcher at the SPIE Bacus mask technology conference this week in Monterey, Calif.

Last September, Applied introduced the Tetra X etcher for conventional masks, aimed partly at the market for transmissive masks used in double and triple patterning with immersion 193 scanners.

“As soon as we finished Tetra X, our customers were pushing us extremely hard to make sure we were ready for EUV within the next year,” said Amitabh Sabharwal, general manager of the mask etch products division at Applied. The current hurry-up atmosphere contrasts with several years of delays to EUV readiness, he added.

“At this stage, all the customers doing EUV are accelerating at the same pace. Until last year I was hesitant to release a EUV product, to invest a bunch of dollars into it. Now, we see a strong customer pull from all sides,” he said.

EUV masks are patterned on the same MoSi multi-layer reflective surfaces seen on the EUV optics. The reflective mask blanks introduce certain end point control challenges, and the much higher cost of the blanks puts severe requirements on the mask etcher in terms of defects and contamination.

With EUV, there are “significant changes in the photomask itself, how it is going to be handled and cleaned. For the first time, we are dealing with a non-pellicle mask, and to a mask with more than three to four layers on it,” he said.

The biggest challenge is the switch from the well-understood chrome absorber material used for decades with transmissive masks to a tantalum absorber for EUV masks. Applied has some experience etching tantalum in IC applications, and it began its EUV mask development program six years ago, in 2005. Nevertheless, the industry knowledge base with etching chrome is deep and wide, while the experience with tantalum etch is relatively recent.

Chrome is a difficult material to etch, with relatively small differences between the etch rates of the absorber and the resist pattern. While tantalum is easier to etch, tantalum tends to generate more debris than chrome.

Banqiu Wu, chief technology officer of Applied’s mask and TSV etch division, said the chemistries for tantalum and chrome are quite different. The use of tantalum-based absorber materials required a complete redesign of the reactor in order to achieve a uniform etch rate. Improving control of the byproducts coming off the mask was another key objective in order to keep defects to a minimum.

Optimizing the substrate movement, the RF power, the rate of turning the plasma on and off, the line edge roughness (LER), all had to be “optimized very carefully so we get minimum defects,” Sabharwal said.

In a temporary sense, EUV masks present fewer OPC challenges. Today’s transmissive masks have lines at the relatively relaxed dimensions of 200, 400, or even 600 nm. But the OPC features include hammerheads and serifs with features in the range of 40-50-60nm, critical dimensions which require tight control by the etching system. EUV lithography is likely to come in with relatively relaxed OPC features, but as design rules move to 11nm and beyond even EUV will require complex OPC features.

Sabharwal said the biggest challenge facing mask makers is the high cost of the substrates. The mask etcher must work nearly perfectly.

Today, it is “fairly well known how to build chrome transmissive masks. With the EUV reflective masks, to produce a defect-free mask is extremely complicated,” he said. A particle on one layer of the Bragg reflector can be encapsulated by subsequent layers, resulting in a “big hump” at the substrate’s surface which is often difficult to repair.

“From our side, our customers are very tough on us for defects,” he said.

A transmissive mask coming out of the Tetra mask etcher. (Source: Applied Materials)

by Ed Korczynski

Lithography is where design meets manufacturing, and so the SPIE Advanced Lithography (AL) conference this year was where Applied Materials and Magma Design Automation chose to launch their new collaborative solution to the problem of managing yield data when ramping the most complex ICs in high-volume manufacturing (HVM). As device features continue to shrink ever smaller than the 193nm of ArF steppers, process windows continue to shrink to reveal complex interdependent yield loss mechanisms. Add in new materials and evolving device structures, and the industry must be able to learn quickly about new yield-loss mechanisms and then efficiently pass that learning back to designers.

In an exclusive meeting with SemiMD during SPIE, representatives of the two companies explained that this new effort is not directed toward solving random yield defects—due to particles for example—but systematic defects due to intrinsic process-design interactions. With ever smaller process windows and interdependencies, maintaining past yields with established design-rule check (DRC) software, “isn’t possible without new methodology,” explained Erez Paran, Applied Materials’ Integrated Solutions Manager, Process Diagnostics and Control. “This solution is intended to enable manufacturing below the 20nm node.”

The companies report seeing a growing gap between simulation and actual manufacturing data. Even with the best optical-proximity correction (OPC) and other reticle-enhancement techniques (RET), masks still have yield-loss “hot spots” when printed into resist in real fabs. Consequently, unlike the traditional way of doing pre-tapeout simulation, this simulation is post-tapeout to be closer to real fab results. GlobalFoundries has reportedly been working with this for over a year now.

Yield management in deep-sub-micron IC fabs only gets more challenging. The traditional method of “binning” yield loss mechanisms starts to fail when the number of bins explodes, and just because a bin appears more frequently does not mean it will be the most critical. As an almost trivial example, post-OPC masks today include “dummy structures” that can short together without loosing any yield. Not all functional paths can be considered to be critical paths, and sorting the critical from the non-critical is one of the key filters to manage the data volume. The software dashboard provides automated visualization tools to overlay inspection data on design information (figure).

Applied and Magma use the Knights Data Base (KGD) as the foundation for managing yield in 20nm node and beyond ICs (source: Applied Materials)

The inspection data shows geometries where there are particular process window limits. Since the limit is systematic and the process is necessarily inflexible, the only possible fix must come from the design using something like additional OPC. With proper data management, the information can be fed further backward within the EDA flow to modify the library level for additional designs. “So it’s sort of short-loop for immediate work, and helps designs go faster for future products in the same process node,” explained Paran.

Knights Data Base (KDB)—part of Magma since the 2006 acquisition of Knights Technology—is the foundation of this new yield management solution. “It’s not only a depository, but a well mined and well correlated data base at the bottom of it all,” said Ankush Oberai, general manager and vice president of Magma’s Fab Analysis Business Unit, “and that’s what makes our solution unique. There’s a lot of input from Applied Materials to this, it’s not just cobbling the two companies’ stuff together.”

The smallest pixel in the inspection tool is ~100nm today, and since some fabs are engaged with 20nm node pilot work, Erez explained that, “if you look at the number of structures you have today there can be five. So it becomes a matter of image processing, algorithms, search-engines, correlation-engines.”

The data base can compare inspection information to more than just a GDSII mask layout, including netlist levels. “Today, there is no single-pattern that can reflect the whole design, so it’s becoming more and more difficult,” said Oberai. “We can overlay the defect map on the layout map, and the layout map is now hierarchical and enriched with critcal path information.”

New fabless business models

When is a design closed? It used to be that passing DRC for a given process-design kit (PDK) meant that a chip should yield. Now the industry faces a time of complexities when designs to be modeled rely on multi-variate simulations based on statistics with varying degrees of confidence.

If following the PDK is necessary but not sufficient, then how can a small team of fabless designers get their chip to yield in a fab? “You can see a new market emerging of small and medium sized companies taking new designs and mediating or cleaning them for manufacturing,” explained Oberai. “You see many more starts ups at the chip level, the entry barrier is becoming lower.” However, the cost to get a lithography mask-set written for advanced IC manufacturing is still probably a million dollars.

Once all these changes have been absorbed, it will invariably be time for yet additional methodology innovation to manage ever increasing yield complexity. “Geometries are not going to stop shrinking, says Oberai, and expects only more data streams to be managed since, “Insitu sensor technologies will take a greater role so we can have predictive data.”