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Blog review March 9, 2015

Monday, March 9th, 2015

Pete Singer is delighted to announce the keynotes and other speakers for The ConFab 2015, to be held May 19-22 at The Encore at The Wynn in Las Vegas. The line-up includes Ali Sebt, President and CEO of Renesas America, Paolo Gargini, Chairman of the ITRS and Subramani Kengeri, Vice President, Global Design Solutions at GLOBALFOUNDRIES.

Mark Simmons, Product Marketing Manager, Calibre Manufacturing Group, Mentor Graphics writes about cutting fab costs and turn-around time with smart, automated resource management. He notes that the competition for market share is brutal for both the pure-play and independent device manufacturer (IDM) foundries. Success involves tuning a lot of knobs and dials. One of the important knobs is the ability to continually meet or exceed aggressive time-to-market schedules.

Paul Stockman, Commercialization Manager, Linde Electronics blogs that there is an increasing demand for and focus on sustainable manufacturing that will contribute to a greening of semiconductors. This greening must be robust and responsive to change and cannot constrain the individual processes or operation of a fab.

Applied Materials’ Max McDaniel writes on the quest for more durable displays. He says the same innovators who created such amazingly thin, light and highly functional smartphones (with the help of Applied Materials display technology) are already developing durability improvements that may eliminate the need for protective covers.

Batteries? We don’t need no stinking batteries, says Ed Korczynski. We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources.

With the 2015 SPIE Advanced Lithography (AL) conference around the corner, some people have asked me what remaining EUVL challenges need to be addressed to ensure it will be ready for mass production later this year or next.  Vivek Bakshi of EUV Litho, Inc. provides thoughts on this topic and what he expects to hear at the conference.

Phil Garrou continues his look at presentations from the Grenoble SEMI 3D Summit which took place in January, focusing on an interesting presentation by ATREG consultants on the future of Assembly & Test.

On Tuesday, January 20, President Obama once again stood before a joint session of Congress to deliver a State of the Union Address.  With the newly seated Republican-controlled Congress and his Cabinet present, the President discussed topics ranging from the current state of the economy to foreign affairs and his ideas on how to move the nation forward.  Jamie Girard of SEMI was pleased to hear that the President supported multiple policy goals including expansion of free trade, corporate tax reform, support for basic science research and development and others.

SPIE Advanced Lithography conference concludes

Friday, February 27th, 2015

By Jeff Dorsch, contributing editor

Exposures, and reducing their cost, were a theme running through the 2015 SPIE Advanced Lithography Symposium this week in San Jose, Calif., the center of Silicon Valley.

Doubts about the continued viability of Moore’s Law abound as the 50th anniversary of Gordon Moore’s historic article for Electronics magazine draws near. Lithographers are under immense industry pressure to lower the operating costs of lithography cells in the fab while increasing wafer throughput.

“Enabling,” “productivity,” and “stability” were watchwords frequently repeated throughout the conference. The various merits (and occasional demerits) of electron-beam, extreme-ultraviolet, 193i immersion and nanoimprint lithography technologies were debated and touted over four days.

One of the technical sessions closing out Wednesday at the San Jose Convention Center was devoted to papers on “Multibeam Lithography,” especially e-beam direct-write technology, which has been seen as “pie in the sky” for many years, yet seems closer to realization than before.

Hans Loeschner of IMS Nanofabrication described how his company’s e-beam tool has progressed from alpha to beta status this year, and predicted it would be ready for production applications in 2016. Altera, CEA-Leti, and MAPPER Lithography presented a total of three papers on MAPPER’s FLX-1200 e-beam direct-write system, saying it is better able to make chips with 20-nanometer features than an immersion lithography system.

The eBeam Initiative held its annual luncheon at SPIE Advanced Lithography on Tuesday, emphasizing how multibeam mask writing, model-based mask data preparation, and complex inverse lithography technology can enable continued density scaling at the 10-nanometer process node.

“We have reached a point with traditional rules-based designs where the rules are so conservative and the implementation costs are so high that the semiconductor industry has started to lose the economic benefits of scaling to smaller design nodes for system-on-chip designs,” D2S CEO Aki Fujimura said in a statement. “A simulation-based approach combining complex ILT, MB-MDP and existing variable shaped beam mask writers in parallel with the impending emergence of multibeam mask writing are providing platforms to enable the semiconductor industry to reverse this trend and reactivate the density benefits associated with Moore’s Law.”

EUV, another technology that has had a long gestation, was the subject of a conference track over all four days, with photomask and photoresist issues being discussed in several sessions.

The news that Taiwan Semiconductor Manufacturing was able to process 1,022 wafers in 24 hours with ASML Holding’s NXE:3300B scanner was the talk of the SPIE conference on Tuesday, the first day of the two-day exhibition, which had about 60 companies occupying booths. ASML didn’t declare an end to development of its EUV systems, saying there is more work to be done. This includes development of a pellicle for the scanner’s reticles and working with resist suppliers on formulas for EUV resists.

While improvements in all types of lithographies were discussed at the conference, there was increased interest in directed self-assembly, which employs polymers to get molecules to arrange themselves in lines and spaces with a patterning guide. Advances in reducing the defectivity of DSA were reported by imec, Merck, and Tokyo Electron.

Global interest in DSA over the past four years has accelerated due to “other things getting delayed,” said Tom Ferry of Synopsys. Among other initiatives, the electronic design automation software and services company was talking about how its S-Litho molecular simulator, S-Litho shape optimizer, and Proteus ILT guide patterning tool can help enable DSA research and development, design, and manufacturing.

The Belgium-based imec was a big contributor to conference presentations, with a first author on 18 papers and posters, and a co-author of 25 publications.

While EUV garnered headlines during SPIE Advanced Lithography, the Cymer subsidiary of ASML was at the conference to talk about its third-generation XLR 700ix light source for deep-ultraviolet lithography systems. Ted Cacouris of Cymer said, “10 nanometer is basically done with DUV. It could go to 7 nanometer; immersion could be extended. It could be complementary to EUV.”

Cymer also announced its DynaPulse program, an upgrade for its OnPulse subscription service for maintenance and repair of light sources. In 2012, prior to the company’s acquisition by ASML, Cymer derived nearly 70 percent of its light-source revenue from the OnPulse service program.

It’s been an interesting week, with about 2,400 attendees from around the world gathering for the premier lithography conference of the year. They will convene again a year from now to learn what’s new in lithography.

Learning to live with negative tone

Friday, February 27th, 2015

By Jeff Dorsch, contributing editor

In lithography for manufacturing semiconductors, a negative tone can be a positive attribute.

Negative-tone photoresists can be used in electron-beam, extreme-ultraviolet, and immersion lithography to improve contrast prior to the etching process. Multiple papers and posters on the topic were presented at this week’s SPIE Advanced Lithography Symposium in San Jose, Calif.

Tuesday morning at the conference saw an entire session devoted to “Negative Tone Materials.” Other papers on the subject were scattered throughout technical sessions covering EUV resists.

Negative-tone resists are especially useful in argon fluoride immersion lithography, according to George Bailey of Synopsys. Contrast loss can result in rounding off of features, and negative-tone resist can aid in keeping features sharp through etch, he noted.

“The technology has been around for a long time,” said Tom Ferry of Synopsys. “First there was negative resist, then positive resist.”

Directed Self Assembly Hot Topic at SPIE

Wednesday, February 25th, 2015

By Jeff Dorsch, contributing editor

At this week’s SPIE Advanced Lithography Symposium in San Jose, Calif., the hottest three-letter acronym is less EUV and more DSA, as in directed self-assembly.

Extreme-ultraviolet lithography continues to command much attention, yet this conference is awash in papers about DSA, which dominates the “Alternative Lithographic Technologies” track of technical sessions. The two-day poster sessions feature 15 posters about DSA. Thursday’s conference sessions include three separate sessions devoted to “DSA Design for Manufacturability” and one for “DSA Modeling.”

With semiconductor industry anxiety rising at the prospect of quadruple-patterning and the slow yet steady progress of EUV technology, directed self-assembly is being hailed and recognized as a way to simplify chip manufacturing at the low end of the nanoscale era.

Before the conference got under way, imec reported on making significant progress in DSA technology, specifically reducing the defectivity associated with the process. Working with Tokyo Electron Ltd. (TEL) and Merck, which acquired AZ Electronic Materials last year, imec has come up with a DSA solution for a via patterning process that they say is compatible with the 7-nanometer process node. The partners are targeting the manufacture of DRAMs using 193nm immersion scanners.

“Over the past few years, we have realized a reduction of DSA defectivity by a factor 10 every six months,” imec’s An Steegen said in a statement. “Together, with Merck and Tokyo Electron, providing state-of-the-art DSA materials and processing equipment, we are looking ahead at two different promising DSA processes that will further improve defectivity values in the coming months. Our processes show the potential to achieve single-digit defectivity values in the near future without any technical roadblocks lying ahead.”

Kurt Ronse of imec describes DSA as utilizing two polymers to get molecules to array in lines or spaces. The issue has been to avoid the creation of holes that don’t fit the guided pattern, resulting in defects.

“All the big [chip] companies are having their internal developments on DSA,” Ronse said at SPIE. “All the memory companies are interested; Micron is in our program.”

While DSA is being implemented with 193 immersion equipment at the outset, there is the possibility of working with EUV scanners in the future, according to Ronse, and imec has an extensive EUV research and development program, he noted.

DSA started to emerge as a technology of note at the 2011 SPIE Advanced Lithography conference, Ronse said, which resulted in imec initiating its program in the field. There has been a significant amount of progress in the past two years, he added.

The momentum behind DSA R&D led to the establishment of the 1st International Symposium on DSA, scheduled for October 26-27, 2015, in Leuven, Belgium. Partnering with imec on the conference are CEA-Leti, EIDEC, and Sematech.

DSA – it’s one TLA you’ll hear a lot about in the years to come.

Proponents of EUV, immersion lithography face off at SPIE

Wednesday, February 25th, 2015

By Jeff Dorsch, contributing editor

The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium in San Jose, Calif.

Extreme-ultraviolet lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing.

On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

There are other lithography technologies being discussed at the conference, of course. They are bit players in the drama, so to speak, although there is a lot of discussion and buzz about directed self-assembly technology this week.

ASML broke big news on Tuesday morning, reporting that Taiwan Semiconductor Manufacturing was able to expose more than 1,000 wafers in one day this year with ASML’s NXE:3300B EUV system. “During a recent test run on an NXE:3300B EUV system we exposed 1,022 wafers in 24 hours with sustained power of over 90 watts,” Anthony Yen, TSMC’s director of research and development, said at SPIE.

While ASML was obviously and justifiably proud of this milestone, after achieving its 2014 goal of producing 500 wafers per day, it cautioned that more development remains for EUV technology.

“The test run at TSMC demonstrates the capability of the NXE:3300B scanner, and moves us closer to our stated target of sustained output of 1,000 wafers per day in 2015,” ASML’s Hans Meiling, vice president service and product marketing EUV, said in a statement. “We must continue to increase source power, improve system availability, and show this result at multiple customers over multiple days.”

The day before, Cymer announced the first shipment of its XLR 700ix light source, which is said to improver scanner throughput and process stability for manufacturing chips with 14-nanometer features. The company also debuted DynaPulse as an upgrade option for its OnPulse customers. The XLR 700ix and DynaPulse together are said to offer better on-wafer critical dimension uniformity and provide stable on-wafer performance.

Another revelation at SPIE is that SK Hynix has been working with the NXE:3300, too, and is pleased with the system’s capabilities. According to Chang-Moon Lim, who spoke Monday morning, SK Hynix was recently able to expose 1,670 wafers over three days, with uptime of 86.3 percent over that period.

“Progress has been significant on various aspects, which should not be overshadowed by the delay of [light] sources,” he said of ASML’s EUV systems.

The Korean chipmaker is exploring how it could work without pellicles on the EUV reticle, Lim noted. ASML has been developing a pellicle, made with polycrystalline silicon, in cooperation with Intel and others.

Nikon Precision and other Nikon subsidiaries didn’t issue any press releases at SPIE. The companies presented much information at Sunday’s LithoVision 2015 event, held at the City National Civic auditorium, across the street from the San Jose Convention Center, where SPIE Advanced Lithography is staged.

On offer at the Nikon conference was the claimed superiority of 193i immersion lithography equipment to EUV systems for the 14nm, 7nm and future process nodes. Donis Flagello, Nikon Research Corp. of America’s president, CEO, and chief operating officer, emphasized that message on Tuesday morning with an invited paper on “Evolving optical lithography without EUV.”

Nikon’s champion machine is the NSR-S630D immersion scanner, which was touted throughout the LithoVision event. The system is capable of exposing 250 wafers per hour, according to Nikon’s Yuichi Shibazaki.

Ryoichi Kawaguchi of Nikon told attendees, “EUV lithography needs more stability and improvement.” He also brought up the topic of manufacturing on 450-millimeter wafers, which has mostly gone ignored in the lithography competition. Nikon will ship a 450mm system this spring to the Global 450 Consortium in Albany, N.Y., Kawaguchi said. The bigger substrates could provide “an alternative option to reduce cost,” he added.

Erik Byers of Micron Technology observed, “EUV is not a panacea.”

Which lithography technology will prevail in high-volume manufacturing? The question may not be definitively answered for some time.

SPIE plenary takes in photonics, 3DICs, connected devices

Monday, February 23rd, 2015

By Jeff Dorsch, contributing editor

Speakers at the plenary session of the SPIE Advanced Lithography conference covered a wide variety of topics, from photonics to 3D chips to the Internet of Things, on Monday morning, February 23, in San Jose, Calif.

Alan Willner, the Sample Chaired Professor of Engineering at the University of Southern California, described activities of the National Photonics Initiative, which he serves as chair-elect.

The initiative has attracted interest and support in Washington, D.C., with $250 million budgeted to fund an Integrated Photonics Institute for Manufacturing Innovation. There are three proposals being considered for the institute’s operation, with a decision expected in the near future, Willner said.

“Photonics spans a growing range of technologies and industries,” he noted. “This breadth has impeded the formulation of coherent strategies.”

Optics and photonics could benefit from the same type of lobbying and promotion employed by the semiconductor industry, he said. To that end, the NPI has hired the Podesta Group to provide access and insight on working with the federal government.

Tsu-Jae King Liu, chair of the University of California-Berkeley’s Department of Electrical Engineering and Computer Science, spoke about “Sustaining the Silicon Revolution” through three-dimensional semiconductor technology and 3D integration. She described the potential implementation of electro-mechanical switches, scaled down to contemporary transistor size, and a polymeric relay; both subjects led to multiple questions from interested attendees.

The plenary session concluded with a talk about the Internet of Things by Xiaowei Shen, director of IBM Research in China. “This is just the beginning of Big Data,” he said. “IoT data will dominate.”

What IBM hopes to foster is combining systems of engagement (such as social networks) and systems of record into “systems of insight,” Shen said.

Complexity is the Theme at Lithography Conference

Monday, February 23rd, 2015

By Jeff Dorsch, contributing editor

Nikon and KLA-Tencor put on separate conferences in San Jose, Calif., on Sunday, February 22, tackling issues in advanced optical lithography. The overarching theme in both sessions was the increased complexity of lithography as it approaches the 10-nanometer and 7nm process nodes.

“Complexity is much higher,” said Kevin Lucas of Synopsys at the Nikon event, LithoVision 2015. He noted that at the 28nm process node, lithographers could resort to five different options. For 14nm or 16nm, that expanded to eight options. There are 21 options available at 10nm, Lucas said, and at 7nm that explodes to more than 71 options.

“The increase in complexity is pretty dramatic,” he observed.

Electronic design automation vendors have “to provide more accurate modeling,” Lucas said. “We will have to go to better methods of [optical proximity correction].”

Ralph Dammel of EMD Performance Materials reviewed the situation in semiconductor materials as IC gate lengths continue to shrink. “We’re going to move from adding new elements to different forms of elements,” he said, such as graphene, silicine, black phosphorus, and molybdenum disulfide.

At the Lithography Users Forum, the event put on by KLA-Tencor, Mark Phillips of Intel said, “Scaling can continue, but it needs improved metrology.” He added, “We need side-by-side accuracy metrics.”

Phillips reported on Intel’s work with ASML Holding on developing pellicles for the reticles of ASML’s extreme-ultraviolet lithography systems. The companies have together come up with a prototype pellicle, which needs more development as a commercial product, he said.

SPIE Photomask Technology Wrap-up

Tuesday, September 23rd, 2014

Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

Even with the wide variety of topics on offer at the Monterey Conference Center, many discussions circled back to EUV lithography. After years of its being hailed as the “magic bullet” in semiconductor manufacturing, industry executives and engineers are concerned that the technology will have a limited window of usefulness. Its continued delays have led some to write it off for the 10-nanometer and 7-nanometer process nodes.

EUV photomasks were the subject of three conference sessions and the focus of seven posters. There were four posters devoted to photomask inspection, an area of increasing concern as detecting and locating defects in a mask gets more difficult with existing technology.

The conference opened Tuesday, Sept. 16, with the keynote presentation by Martin van den Brink, the president and chief technology officer of ASML Holding. His talk, titled “Many Ways to Shrink: The Right Moves to 10 Nanometer and Beyond,” was clearly meant to provide some reassurance to the attendees that progress is being made with EUV.

He reported his company’s “30 percent improvement in overlay and focus” with its EUV systems in development. ASML has shipped six EUV systems to companies participating in the technology’s development (presumably including Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing, which have made equity investments in ASML), and it has five more being integrated at present, van den Brink said.

The light source being developed by ASML’s Cymer subsidiary has achieved an output of 77 watts, he said, and the company expects to raise that to 81 watts by the end of 2014. The key figure, however, remains 100 watts, which would enable the volume production of 1,000 wafers per day. No timeline on that goal was offered.

The ASML executive predicted that chips with 10nm features would mostly be fabricated with immersion lithography systems, with EUV handling the most critical layers. For 7nm chips, immersion lithography systems will need 34 steps to complete the patterning of the chip design, van den Brink said. At that process node, EUV will need only nine lithography steps to get the job done, he added.

Among other advances, EUV will require actinic mask inspection tools, according to van den Brink. Other speakers at the conference stressed this future requirement, while emphasizing that it is several years away in implementation.

Mask making is moving from detecting microscopic defects to an era of mesoscopic defects, according to Yalin Xiong of KLA-Tencor. Speaking during the “Mask Complexity: How to Solve the Issues?” panel discussion on Thursday, Sept. 18, Xiong said actinic mask inspection will be “available only later, and it’s going to be costly.” He predicted actinic tools will emerge by 2017 or 2018. “We think the right solution is the actinic solution,” Xiong concluded.

Peter Buck of Mentor Graphics, another panelist at the Sept. 18 session, said it was necessary to embrace mask complexity in the years to come. “Directed self-assembly has the same constraints as EUV and DUV (deep-ultraviolet),” he observed.

People in the semiconductor industry place high values on “good,” “fast,” and “cheap,” Buck noted. With the advent of EUV lithography and its accompanying challenges, one of those attributes will have to give way, he said, indicating cheapness was the likely victim.

Mask proximity correction (MPC) and Manhattanization will take on increasing importance, Buck predicted. “MPC methods can satisfy these complexities,” he said.

For all the concern about EUV and the ongoing work with that technology, the panelists looked ahead to the time when electron-beam lithography systems with multiple beams will become the litho workhorses of the future.

Mask-writing times were an issue touched upon by several panelists. Shusuke Yoshitake of NuFlare Technology reported hearing about a photomask design that took 60 hours to write. An extreme example, to be sure, but next-generation multi-beam mask writers will help on that front, he said.

Daniel Chalom of IMS Nanofabrication said that with 20nm chips, the current challenge is reduce mask-writing times to less than 15 hours.

In short, presenters at the SPIE conference were optimistic and positive about facing the many challenges in photomask design, manufacturing, inspection, metrology, and use. They are confident that the technical hurdles can be overcome in time, as they have in the past.

SPIE panel tackles mask complexity issues

Friday, September 19th, 2014

Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

These were among the issues addressed by eight panelists in a Thursday session at the SPIE Photomask Technology conference in Monterey, Calif. Participants in the “Mask Complexity: How to Solve the Issues?” panel discussion came from multiple segments of the photomask food chain, although only one, moderator Naoya Hayashi of Dai Nippon Printing, represented a company that actually makes masks.

The panelists were generally optimistic on prospects for resolving the various issues in question. Dong-Hoon Chung of Samsung Electronics said solutions to the thorny challenges in designing, preparing, and manufacturing masks were “not impossible.”

Bala Thumma of Synopsys said he was “going to take the optimistic view” regarding mask-making challenges. “Scaling is going to continue,” he added.

“We are not at the breaking point yet,” Thumma said. “Far from it!” Electronic design automation companies like Synopsys will continue to improve their software tools, he asserted. Mask manufacturers will also benefit from “strong partnerships” with vendors of semiconductor manufacturing equipment, and “strong support from semiconductor companies,” he said.

“There is a lot of complexity,” he acknowledged. Still, going by past experience, “this group of people has been able to work together and solve these issues,” Thumma concluded.

To resolve the issue of burgeoning data volumes in mask design and manufacture, Suichiro Ohara of Nippon Control System (NCS) proposed the solution of a unified data format – specifically MALY and OASIS.MASK software. Shusuke Yoshitake of NuFlare Technology later said, “OASIS is gaining, but GDSII still predominates.”

Several panelists took the long-term view and looked beyond the coming era of EUV lithography to when multiple-beam mask writers and actinic inspection of masks will be required. EUV and actinic technology, it was generally agreed, will arrive at the 7-nanometer process node, possibly in 2017 or 2018. Multi-beam mask writers are also several years away, it was said.

As the floor was opened to questions and comments, consultant Ken Rygler noted that commercial mask makers have “very low margins” and asked, “How does the mask maker pay for the inspection tools, the EDA, materials?” Yalin Xiong of KLA-Tencor said the mask business is in “a tough time economically.” He added, “We have to look at where the high-end business is going. Captive [mask shops] should step up.”

ASML on EUV: Available at 10nm

Wednesday, September 17th, 2014


By Jeff Dorsch, contributing editor

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

Giving the keynote presentation Tuesday at the SPIE Photomask Technology conference in Monterey, Calif., Martin offered a lengthy update on his company’s progress with EUV technology.

Sources for the next-generation lithography systems are now able to produce 77 watts of power, and ASML is shooting for 81W by the end of 2014, Martin said.

The power figure is significant since it indicates how many wafers the litho system can process, a key milestone in EUV’s progress toward becoming a volume manufacturing technology. With an 80W power source, ASML’s EUV systems could turn out 800 wafers a day, he noted.

The goal is to get to 1,000 wafers per day. ASML has lately taken to specifying throughput rates in daily production, not wafers per hour, since many wafer fabs are running nearly all the time at present.

ASML’s overarching goal is providing “affordable scaling,” Martin asserted, through what he called “holistic lithography.” This involves both immersion litho scanners and EUV machines, he said.

Martin offered a product roadmap over the next four years, concluding with manufacturing of semiconductors with 7nm features in 2018.

The ASML president acknowledged that the development of EUV has been halting over the years, while asserting that his company has made “major progress” with EUV. He said the EUV program represented “a grinding project, going on for 10 years.”

For all of EUV’s complications and travails, “nothing is impossible,” Martin told a packed auditorium at the Monterey Conference Center.

With many producers of photomasks in attendance at the conference, Martin promised, “We are not planning to make a significant change in mask infrastructure” for EUV. He added, “What you are investing today will be useful next year, and the year after that.”