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Blog review March 31, 2014

Monday, March 31st, 2014

Ofer Adan of Applied Materials blogs about his keynote presentation at the recent SPIE Advanced Lithography conference, which focused on how improvements in metrology, multi-patterning techniques and materials can enable 3D memory and the critical dimension (CD) scaling of device designs to sub-10nm nodes.

Soitec’s Bich-Yen Nguyen and Christophe Maleville detail why the fully-depleted SOI device/circuit is a unique option that can satisfy all the requirements of smart handheld devices and remote data storage “in the cloud.” Devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. Demonstrated benefits of FDSOI, including simpler fabrication and scalability are covered.

This year’s IMAPS Device Packaging Conference in Ft McDowell, AZ had a series of excellent keynote talks. Phil Garrou takes a look at some of those and several key presentations from the conference. Steve Bezuk, Sr. Dir. of Package Engineering for Qualcomm discussed “challenges and directions in mobile device packaging”. Qualcomm expects 7 billion smartphone units to be shipped between 2012 and 2017.

Karen Lightman of the MEMS Industry Group writes about the recent MEMS Executive Congress Europe 2014. She describes how every panelist shared not only the “everything’s-coming-up-MEMS” perspective but also some real honest discussion about the remaining challenges of getting MEMS devices to market on-time, and at (or below) cost.

Pete Singer shares some details of the upcoming R&D Panel Session at The ConFab this year. The session, to be moderated by Scott Jones of Alix Partners, will include panelists Rory McInerny of Intel, Chris Danely of JP Morgan, Mike Noonen of Silicon Catalyst and Lode Lauwers of imec.

Blog review March 10, 2014

Monday, March 10th, 2014

Pete Singer is pleased to announce that IBM’s Dr. Gary Patton will provide the keynote talk at The ConFab on Tuesday, June 24th. Gary is Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, and has responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances.

Nag Patibandla of Applied Materials describes a half-day workshop at Lawrence Berkeley Lab that assembled experts to discuss challenges and identify opportunities for collaboration in semiconductor manufacturing including EUV lithography, advanced etch techniques, compound semiconductors, energy storage and materials engineering.

Adele Hars of Advanced Substrate News reports on a presentation by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during SEMI’s recent ISS Europe Symposium. FD-SOI is significantly cheaper, outdoes planar bulk and matches bulk FinFET in the performance/power ratio, and keeps the industry on track with Moore’s Law, she writes.

Phil Garrou reports on the RTI- Architectures for Semiconductor Integration & Packaging (ASIP) conference, which is focused on commercial 3DIC technology. Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing. In addition Tezzaron’s Robert Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly.

Vivek Bakshi, EUV Litho, Inc., blogs that most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM).

On March 2, 2014 SIA announced that worldwide sales of semiconductors reached $26.3 billion for the month of January 2014, an increase of 8.8% from January 2013 when sales were $24.2 billion. After adding in semiconductor sales from excluded companies such as Apple and Sandisk, that total is even higher, marking the industry’s highest-ever January sales total and the largest year-to-year increase in nearly three years. These results are in-line with the Semico IPI index which has been projecting strong semiconductor revenue growth for the 1st and 2nd quarters of 2014.

Blog review February 24, 2014

Monday, February 24th, 2014

Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. But as Pete Singer blogs, he also said: “In the end, if this isn’t cheaper, no one is going to do it,” he said.

Adele Hars of Advanced Substrate News reports that body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages.

Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc., says the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation. This is putting more emphasis on high sigma yield.

Jamie Girard, senior director, North America Public Policy, SEMI President Obama touched on many different policy areas during his State of the Union talk, and specifically mentioned a number of issues that are of top concern in the industry and with SEMI member companies. Among these are funding for federal R&D, including public-private partnerships, trade, high-skilled immigration reform, and solar energy.

Phil Garrou finishes his look at the IEEE 3DIC meeting, with an analysis of presentations from Tohoku University, Fujitsu’s wafer-on-wafer (WOW), ASE/Chiao Tung University and RTI. In another blog, Phil continues his review of the Georgia Tech Interposer conference, highlighting presentations from Corning, Schott Glass, Asahi Glass, Shinko, Altera, Zeon and Ushio.

Pete Singer recommends taking the new survey by the National Center for Manufacturing Sciences (NCMS) but you may first want to give some thought as to what is and what isn’t “nanotechnology.”

Blog review January 21, 2014

Tuesday, January 21st, 2014

Zvi Or-Bach, President and CEO of MonolithIC 3D weighs in on the battle of Intel vs TSMC in the foundry space, after conflicting stories appeared. One said that Intel had a huge pricing advantage over TSMC, and a second story noted TSMC’s boast that it was “far superior” to Intel and Samsung as a partner fab.

Adele Hars looks back at 2013 from the SOI perspective. In this “Part 2” post, she focuses on developments that last year brought in the areas of RF-SOI and SOI-FinFETs. Part 1 focused on the general SOI picture. Stayed tuned for a look at 2014.

Phil Garrou reports on some of the key 3DIC presentations from the IEEE Internal Electron Devices Meeting (IEDM), held in December in Washington, D.C. , focusing on papers from Micron, TSMC, Tohoku Univ., NC State and ASET. He said that Micron’s Naga Chandrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking, noting that he does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.

Blog review January 13, 2014

Monday, January 13th, 2014

Why is Silicon Valley the world center for innovation? How does innovation continue to thrive there? How do you create and maintain an innovative culture? These and other thought-provoking questions were the topics of discussion on a recent episode of Inside Silicon Valley, a public affairs program. Eric Witherspoon of Applied Materials blogs about these questions and various answers.

Adele Hars blogs that 2014 is going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise. In this post she takes a look back at some of the SOI-related highlights from 2013.

Phil Garrou provides details on the most notable packaging papers presented at the 2013 IWLPC Conference held in San Jose CA this past fall, including those from Rudolph, Nanium and Deca. He also comments on the rumors that ASML has delayed its 450mm EUV efforts.

Pete Singer blogs from this week’s ISS. Keynote Rick Wallace, president and CEO of KLA-Tencor said the semiconductor industry could be approaching a “Concorde moment” where economic factors overtake technical capabiltiies. Wallace also sees a need to boost innovation, and suggests the way to best do that is encourage young people to get excited about the “magic behind the gadget.”

Why SOI is the Future Technology of Semiconductors

Monday, December 23rd, 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D, blogs that this is the “one learning” we can take away from IEDM 2013.

Let’s start with the short answer – because:

A. SOI is cheaper to fabricate than FinFet with comparable performance, and it is easier and cheaper to build FinFET on SOI which then provides better performance.

B. SOI is the natural technology for monolithic 3D IC for all overlaying transistor layers, and monolithic 3D is the most effective path to stay on Moore’s Law.

C. SOI, or better ‘XOI’, is the most efficient path for most of the new concepts such as alternate materials for transistor construction and other structures like nano-wires.

Let’s now elaborate and discuss each of these points.

Starting with A: The following chart from Globalfoundries was presented on June 2013 at the FD-SOI Workshop, Kyoto, Japan. The chart illustrates that the best cost per transistor is the classic polysilcon gate at the 28nm node, that FD-SOI is cheaper than bulk with comparable performance at 28nm HKMG, and that FD-SOI at 20nm is cheaper than 14nm FinFet at the same performance level.

Similar information was presented by IBS (International Business Strategies), in Oct 2013 at the SOI Summit Shanghai, China.

And before that D. Handel Jones of IBS in a 2012 White Paper presented the following table.

Clearly the SOI substrate costs much more than the bulk substrate ($500 vs. $120), but the improvement in performance and the reduction of cost associated with FD processing neutralizes the substrate costs and makes the SOI route far more attractive. The following charts were included in a Comparison Study of FinFET on SOI vs. Bulk done by IBM, IMEC, SOITEC and Freescale:

For the second point “B, SOI is the natural technology for monolithic 3D”, in monolithic 3D the upper semiconductor layer is very thin (<100nm) and is placed over oxide to isolate it from the interconnection structure underneath – hence SOI.

In this month’s IEDM 2013 two papers (9.3, 29.6) presented exciting demonstrations of monolithic 3D IC. It is interesting to note that Prof. Emeritus Chenming Hu of Berkeley (past TSMC CTO) who is now very famous due to his pioneering work on FinFETs, is a co-author of these two pioneering works on monolithic 3D IC. The following figures illustrate the natural SOI structure of the upper transistor layers:

In his invited paper at IEDM 2013 Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is most effective path for the semiconductor future: ” Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” As illustrated by his Fig. 17 below.

Clearly dimensional scaling is not providing transistor cost reduction beyond the 28 nm node, and the large fabless companies—Qualcomm, Broadcom, Nvidia, and AMD—recently reported this fact once again. The industry is trying to accommodate this new reality, while still rushing to develop and adopt more advanced nodes at escalating costs and complexity. And it is encouraging to see that Qualcomm are actually ‘putting their money where their mouth is” as CEA Leti just recently announced an agreement with Qualcomm to Evaluate Leti’s Non-TSV 3D Process.

Thus it was natural for Leti to include in their presentation at their promotional event in conjunction with this year’s IEDM 2013, slides advocating monolithic 3D as an alternative to dimensional scaling.

Leti’s presentation goes even further. One can see that in the following Leti slide, monolithic 3D is positioned as a far better path to keep the industry momentum and provides the cost reduction that dimensional scaling does not provide any more. Monolithic 3D also does this with far less costly fab infrastructure and process R&D. As the slide sums up: “1 node gain without scaling,” or, as others may say, the new form of scaling is ‘scaling up’.

In respect to point C regarding integration of other materials, we must admit that this is still area of advanced research and contains many unknowns. What we do know is that the silicon related worldwide infrastructure is unparalleled and will not be easily replaced. Accordingly, future technologies would have the best chance by first integrating with the existing silicon infrastructure, which in many cases is easier to do with SOI. To illustrate this we can refer to some other work presented in the IEDM 2013. Such as Stanford work (19.7) titled: “Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits” illustrated in the following chart:

Other work is about integrating photonics with CMOS which was covered in a recent article titled Is There Light At The End Of Moore’s Tunnel? and includes the following illustrations:

Clearly SOI and monolithic 3D integration have a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS Scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains. These technologies were not part of the main stream semiconductor past; accordingly it is a golden opportunity to catch-up with these technologies now. Please mark your calendar for this opportunity to contribute and learn about SOI and monolithic 3D technology, as these technologies are well positioned to keep the semiconductor industry’s future momentum.

The Week in Review: Dec. 20, 2013

Friday, December 20th, 2013

3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame, CA. Bryan Black, Sr Fellow and 3D program manager at AMD noted that while die stacking has caught on in FPGAs and image sensors “..there is nothing yet in mainstream computing CPUs, GPUs or APUs” but that “HBM (high bandwidth memory) will change this.”  Black continued,  “Getting 3D going will take a BOLD move and AMD is ready to make that move.” Black announced that AMD is co-developing HBM with SK Hynix which is currently sampling the HBM memory stacks and that AMD “…is ready to work with customers.”

ABI Research verified that Intel has a leading position in the mobile processor technology race; launching the first 22nm mobile application processor. The 22nm quad-core application processor (Intel Z3740D) was found in a Dell tablet that was recently launched for the Christmas season. “2013 saw a number of new processor launches with 32nm and 28nm technology (most from fabless companies) but Intel has used one of its core advantages [process technology] to pass them all,” Jim Mielke, VP of engineering at ABI Research, commented. “The 22nm process node used for the Z3740D is not just the smallest geometry in a mobile device today; it also introduces a new transistor. The core transistor structure used in the 22nm Z3740D is quite different than structures used in previous generations. The core transistor found in the device ABI Research analyzed has a gate that surrounds source/drain diffusion fins on three sides giving it the name tri-gate or 3D transistor.

North America-based manufacturers of semiconductor equipment posted $1.24 billion in orders worldwide in November 2013 (three-month average basis) and a book-to-bill ratio of 1.11, according to the November EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.11 means that $111 worth of orders were received for every $100 of product billed for the month. “The continuing rise in equipment bookings clearly points to year-end order activity that is substantially stronger compared to one year ago,” said Denny McGuirk, president and CEO of SEMI.  ”This trend supports the current outlook showing a rebound in equipment spending for 2014.”

Soitec and CEA have renewed their partnership for the next five years. This new contract aims to support Soitec’s strategy for the electronics, solar energy and lighting markets. It will focus on engineered substrates and materials offering higher performances and energy savings at a competitive cost. As the new partnership is putting in place a powerful R&D ecosystem, time from research to product will be considerably reduced. Thanks to the strengths of CEA-Leti in electronic materials, multi-domain research and its pre-industrialization infrastructure, competitive R&D sample prototyping will be enabled thru a common platform, reducing time to market and R&D costs for Soitec and its customers.

Micron Technology, Inc. announced its collaboration with Broadcom Corporation to develop the industry’s first solution designed for customers challenged by an intrinsic DDR3 timing parameter called tFAW, or four activate window.

Solid State Watch: Dec. 13-19, 2013

Friday, December 20th, 2013
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Solid State Watch: Dec. 6-12, 2013

Friday, December 13th, 2013
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The Week in Review: Dec. 13, 2013

Friday, December 13th, 2013

A new type of transistor that could make possible fast and low-power computing devices for energy-constrained applications such as smart sensor networks, implantable medical electronics and ultra-mobile computing is feasible, according to Penn State researchers. Called a near broken-gap tunnel field effect transistor (TFET), the new device uses the quantum mechanical tunneling of electrons through an ultrathin energy barrier to provide high current at low voltage. Penn State, the National Institute of Standards and Technology and IQE, a specialty wafer manufacturer, jointly presented their findings at the International Electron Devices Meeting in Washington, D.C. The IEDM meeting includes representatives from all of the major chip companies and is the recognized forum for reporting breakthroughs in semiconductor and electronic technologies.

Based on a honeycomb network of carbon atoms, graphene could generate a type of electronic surface wave that would allow antennas just one micron long and 10 to 100nm wide to do the work of much larger antennas. While operating graphene nano-antennas have yet to be demonstrated, the researchers say their modeling and simulations show that nano-networks using the new approach are feasible with the alternative material.“We are exploiting the peculiar propagation of electrons in graphene to make a very small antenna that can radiate at much lower frequencies than classical metallic antennas of the same size,” said Ian Akyildiz, a Ken Byers Chair professor in Telecommunications in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. “We believe that this is just the beginning of a new networking and communications paradigm based on the use of graphene.”

This week, industry leaders and experts have gathered in Washington D.C. at the 59th annual IEEE International Electron Device Meeting (IEDM) conference. The IEDM presents more leading work in more areas of the field than any other technical conference, encompassing silicon and non-silicon device technology, molecular electronics, nanotechnology, optoelectronics, MEM/NEMS, energy-related devices and bioelectronics. The 59th annual IEDM conference includes a strong overall emphasis on circuit-device interaction, advanced semiconductor manufacturing, and biomedical devices. Solid State Technology‘s Pete Singer is on site all week, and we will be getting insight from bloggers and industry partners. Browse our slideshow of highlights from abstracts being presented this week.

The penetration of gallium nitride-on-silicon (GaN-on-Si) wafers into the light-emitting diode (LED) market is forecast to increase at a compound annual growth rate (CAGR) of 69 percent from 2013 to 2020, by which time they will account for 40 percent of all GaN LEDs manufactured, according to a new report from IHS Inc. In 2013, 95 percent of GaN LEDs will be manufactured on sapphire wafers, while only 1 percent will be manufactured on silicon wafers. The growth in the manufacturing of GaN-on-Si LEDs between 2013 and 2020 will take market share from both sapphire and silicon carbide wafers.

Soitec announced this week that the European Commission has approved the financing for the Guépard program, coordinated by Soitec. This program was launched to develop a new generation of highly efficient photovoltaic cells. It was selected in April 2012 by the “Invest for the Future” (Investissements d’Avenir) program, which is managed by the French environment and energy management agency (ADEME – Agence de l’Environnement et de la Maîtrise de l’Energie). As well as Soitec, Guépard brings together the French Alternative Energies and Atomic Energy Commission (CEA), and an SME, InPACT. For all these partners together it represents total investment of €68.9 million over five years. The European Commission’s notification to the French government of its funding approval will give Soitec access to €21.3 million in government support.

Invensas Corporation announced that it is partnering with Tezzaron Semiconductor Corp. a pioneer and producer of 3D Integrated Circuit (3D-IC) semiconductor devices, in order to build a wide range of 3D-IC customer products. Robert Patti, CTO of Tezzaron said: “We can produce complete high-quality 2.5D and 3D silicon devices, but the final packaging flows are lacking. Invensas’ 3D-IC packaging expertise and existing pilot assembly line capability will enable us to ramp our unique products into full production. The Invensas combination of technology development and low volume manufacturing capabilities are unlike anything else available.”

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