Part of the  

Solid State Technology

  Network

About  |  Contact

Posts Tagged ‘SOI’

Blog review April 14, 2014

Monday, April 14th, 2014

The increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. Dr. Roawen Chen of Qualcomm says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In a keynote talk at The ConFab, titled “what’s on our mind?” Dr. Chen will deliberate on a number of headwinds and opportunities.

Jean-Eric Michallet, Hughes Metras and Perrine Batude of CEA-Leti describe how the research group has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.

Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a review of the keynote by AMD’s Bryan Black, titled“Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” Garrou also reviews the newly announced STATSChipPAC FlexLine, which uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.

Karen Savala, president, SEMI Americas, blogs about the sustainable manufacturing imperative, noting that sustainability is increasingly considered a differentiating factor in global competitiveness relative to the technologies and products being provided. In conjunction with SEMICON West and INTERSOLAR North America, SEMI is organizing a four-day Sustainable Manufacturing Forum to share information about the latest technologies, products, and management approaches that promote sustainable manufacturing.

Blog review March 10, 2014

Monday, March 10th, 2014

Pete Singer is pleased to announce that IBM’s Dr. Gary Patton will provide the keynote talk at The ConFab on Tuesday, June 24th. Gary is Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, and has responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances.

Nag Patibandla of Applied Materials describes a half-day workshop at Lawrence Berkeley Lab that assembled experts to discuss challenges and identify opportunities for collaboration in semiconductor manufacturing including EUV lithography, advanced etch techniques, compound semiconductors, energy storage and materials engineering.

Adele Hars of Advanced Substrate News reports on a presentation by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during SEMI’s recent ISS Europe Symposium. FD-SOI is significantly cheaper, outdoes planar bulk and matches bulk FinFET in the performance/power ratio, and keeps the industry on track with Moore’s Law, she writes.

Phil Garrou reports on the RTI- Architectures for Semiconductor Integration & Packaging (ASIP) conference, which is focused on commercial 3DIC technology. Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing. In addition Tezzaron’s Robert Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly.

Vivek Bakshi, EUV Litho, Inc., blogs that most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM).

On March 2, 2014 SIA announced that worldwide sales of semiconductors reached $26.3 billion for the month of January 2014, an increase of 8.8% from January 2013 when sales were $24.2 billion. After adding in semiconductor sales from excluded companies such as Apple and Sandisk, that total is even higher, marking the industry’s highest-ever January sales total and the largest year-to-year increase in nearly three years. These results are in-line with the Semico IPI index which has been projecting strong semiconductor revenue growth for the 1st and 2nd quarters of 2014.

Blog review February 24, 2014

Monday, February 24th, 2014

Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. But as Pete Singer blogs, he also said: “In the end, if this isn’t cheaper, no one is going to do it,” he said.

Adele Hars of Advanced Substrate News reports that body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages.

Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc., says the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation. This is putting more emphasis on high sigma yield.

Jamie Girard, senior director, North America Public Policy, SEMI President Obama touched on many different policy areas during his State of the Union talk, and specifically mentioned a number of issues that are of top concern in the industry and with SEMI member companies. Among these are funding for federal R&D, including public-private partnerships, trade, high-skilled immigration reform, and solar energy.

Phil Garrou finishes his look at the IEEE 3DIC meeting, with an analysis of presentations from Tohoku University, Fujitsu’s wafer-on-wafer (WOW), ASE/Chiao Tung University and RTI. In another blog, Phil continues his review of the Georgia Tech Interposer conference, highlighting presentations from Corning, Schott Glass, Asahi Glass, Shinko, Altera, Zeon and Ushio.

Pete Singer recommends taking the new survey by the National Center for Manufacturing Sciences (NCMS) but you may first want to give some thought as to what is and what isn’t “nanotechnology.”

Blog review January 21, 2014

Tuesday, January 21st, 2014

Zvi Or-Bach, President and CEO of MonolithIC 3D weighs in on the battle of Intel vs TSMC in the foundry space, after conflicting stories appeared. One said that Intel had a huge pricing advantage over TSMC, and a second story noted TSMC’s boast that it was “far superior” to Intel and Samsung as a partner fab.

Adele Hars looks back at 2013 from the SOI perspective. In this “Part 2” post, she focuses on developments that last year brought in the areas of RF-SOI and SOI-FinFETs. Part 1 focused on the general SOI picture. Stayed tuned for a look at 2014.

Phil Garrou reports on some of the key 3DIC presentations from the IEEE Internal Electron Devices Meeting (IEDM), held in December in Washington, D.C. , focusing on papers from Micron, TSMC, Tohoku Univ., NC State and ASET. He said that Micron’s Naga Chandrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking, noting that he does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.

Blog review January 13, 2014

Monday, January 13th, 2014

Why is Silicon Valley the world center for innovation? How does innovation continue to thrive there? How do you create and maintain an innovative culture? These and other thought-provoking questions were the topics of discussion on a recent episode of Inside Silicon Valley, a public affairs program. Eric Witherspoon of Applied Materials blogs about these questions and various answers.

Adele Hars blogs that 2014 is going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise. In this post she takes a look back at some of the SOI-related highlights from 2013.

Phil Garrou provides details on the most notable packaging papers presented at the 2013 IWLPC Conference held in San Jose CA this past fall, including those from Rudolph, Nanium and Deca. He also comments on the rumors that ASML has delayed its 450mm EUV efforts.

Pete Singer blogs from this week’s ISS. Keynote Rick Wallace, president and CEO of KLA-Tencor said the semiconductor industry could be approaching a “Concorde moment” where economic factors overtake technical capabiltiies. Wallace also sees a need to boost innovation, and suggests the way to best do that is encourage young people to get excited about the “magic behind the gadget.”

Why SOI is the Future Technology of Semiconductors

Monday, December 23rd, 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D, blogs that this is the “one learning” we can take away from IEDM 2013.

Let’s start with the short answer – because:

A. SOI is cheaper to fabricate than FinFet with comparable performance, and it is easier and cheaper to build FinFET on SOI which then provides better performance.

B. SOI is the natural technology for monolithic 3D IC for all overlaying transistor layers, and monolithic 3D is the most effective path to stay on Moore’s Law.

C. SOI, or better ‘XOI’, is the most efficient path for most of the new concepts such as alternate materials for transistor construction and other structures like nano-wires.

Let’s now elaborate and discuss each of these points.

Starting with A: The following chart from Globalfoundries was presented on June 2013 at the FD-SOI Workshop, Kyoto, Japan. The chart illustrates that the best cost per transistor is the classic polysilcon gate at the 28nm node, that FD-SOI is cheaper than bulk with comparable performance at 28nm HKMG, and that FD-SOI at 20nm is cheaper than 14nm FinFet at the same performance level.

Similar information was presented by IBS (International Business Strategies), in Oct 2013 at the SOI Summit Shanghai, China.

And before that D. Handel Jones of IBS in a 2012 White Paper presented the following table.

Clearly the SOI substrate costs much more than the bulk substrate ($500 vs. $120), but the improvement in performance and the reduction of cost associated with FD processing neutralizes the substrate costs and makes the SOI route far more attractive. The following charts were included in a Comparison Study of FinFET on SOI vs. Bulk done by IBM, IMEC, SOITEC and Freescale:

For the second point “B, SOI is the natural technology for monolithic 3D”, in monolithic 3D the upper semiconductor layer is very thin (<100nm) and is placed over oxide to isolate it from the interconnection structure underneath – hence SOI.

In this month’s IEDM 2013 two papers (9.3, 29.6) presented exciting demonstrations of monolithic 3D IC. It is interesting to note that Prof. Emeritus Chenming Hu of Berkeley (past TSMC CTO) who is now very famous due to his pioneering work on FinFETs, is a co-author of these two pioneering works on monolithic 3D IC. The following figures illustrate the natural SOI structure of the upper transistor layers:

In his invited paper at IEDM 2013 Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is most effective path for the semiconductor future: ” Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” As illustrated by his Fig. 17 below.

Clearly dimensional scaling is not providing transistor cost reduction beyond the 28 nm node, and the large fabless companies—Qualcomm, Broadcom, Nvidia, and AMD—recently reported this fact once again. The industry is trying to accommodate this new reality, while still rushing to develop and adopt more advanced nodes at escalating costs and complexity. And it is encouraging to see that Qualcomm are actually ‘putting their money where their mouth is” as CEA Leti just recently announced an agreement with Qualcomm to Evaluate Leti’s Non-TSV 3D Process.

Thus it was natural for Leti to include in their presentation at their promotional event in conjunction with this year’s IEDM 2013, slides advocating monolithic 3D as an alternative to dimensional scaling.

Leti’s presentation goes even further. One can see that in the following Leti slide, monolithic 3D is positioned as a far better path to keep the industry momentum and provides the cost reduction that dimensional scaling does not provide any more. Monolithic 3D also does this with far less costly fab infrastructure and process R&D. As the slide sums up: “1 node gain without scaling,” or, as others may say, the new form of scaling is ‘scaling up’.

In respect to point C regarding integration of other materials, we must admit that this is still area of advanced research and contains many unknowns. What we do know is that the silicon related worldwide infrastructure is unparalleled and will not be easily replaced. Accordingly, future technologies would have the best chance by first integrating with the existing silicon infrastructure, which in many cases is easier to do with SOI. To illustrate this we can refer to some other work presented in the IEDM 2013. Such as Stanford work (19.7) titled: “Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits” illustrated in the following chart:

Other work is about integrating photonics with CMOS which was covered in a recent article titled Is There Light At The End Of Moore’s Tunnel? and includes the following illustrations:

Clearly SOI and monolithic 3D integration have a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS Scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains. These technologies were not part of the main stream semiconductor past; accordingly it is a golden opportunity to catch-up with these technologies now. Please mark your calendar for this opportunity to contribute and learn about SOI and monolithic 3D technology, as these technologies are well positioned to keep the semiconductor industry’s future momentum.

FinFET on SOI: Potential Becomes Reality

Thursday, December 5th, 2013

Authors: T. B. Hook, I. Ahsan, A. Kumar, K. McStay, E. Nowak, S. Saroop, C. Schiller, G. Starkey, IBM Semiconductor Research and Development Center

We report here empirical results demonstrating the electrical benefits of SOI-based FinFETs. There are benefits inherent in the elimination of dopant as the means to establish the effective device dimensions.  However, significant compromise is unavoidable when using doping as a means of isolation, as in bulk-based FinFETs.  Accordingly, we use SOI as the base on which to build the FinFET, which not only simplifies the process but enables full realization of the potential of the device.
Fully depleted transistor technologies – both planar and SOI-based FinFET – offer excellent circuit operation for SRAM and DRAM due to the unsurpassed threshold voltage matching associated with the near-absence of doping.   Additionally, good low voltage and stacked-fet circuit operation is realized due to the superior electrostatics associated with thin-body devices.  Hardware data specifically illustrating these features is described below.

Threshold voltage matching and distribution

A significant improvement in threshold voltage mismatch has been well documented, as well as the degradation associated with adding doping to a FinFET.  Less well publicized, however, is the even larger relative benefit to be found in thick-dielectric transistors, such as are used for analog and IO devices, and also in DRAM.

Random dopant fluctuation is not the only mechanism contributing to local threshold voltage mismatch, but it has historically been the largest contributor.  It has been an even larger contributor for thicker dielectrics, as its baleful influence scales directly with dielectric thickness, unlike work function variations for example.   Therefore an even more dramatic improvement in matching is found in thick-dielectric devices, as shown in Figure 1.

Figure 1. Mismatch data as a function of tinv for conventional doped (dotted line) and SOI FinFET (solid line). While the improvement in matching for ‘thin-oxide’ (1.2-1.5nm) is well known, less widely recognized is the even larger advantage obtained with ‘thick-oxide’ (>3nm) devices commonly used in IO and analog applications.

This improvement is important to IO and analog circuit operation and is vital to scaling the DRAM transfer device into the next generations.
In Figure 2 are shown probability plots of the threshold voltage for two DRAM transfer gate transistors and the profound improvement is obvious.   The FinFET version actually has a considerably thicker gate dielectric than the conventional doped device and a shorter gate yet much better matching.  The absence of thickness-driven matching opens up the device design space and enables optimization of the overall design, as well as allowing for the fundamental area scaling needed to move to the next generation.

Figure 2: Threshold voltage matching for DRAM transfer devices. Blue: 32nm generation thick oxide doping-controlled device. Red: 14nm generation thick oxide FinFET device. The FinFET device is shorter and has a thicker dielectric, yet the threshold voltage matching standard deviation is 0.7X that of the conventional planar doped version. This improvement is applicable also to other thick oxide devices, such as are used in IO and analog applications.

SRAM Vmin
One of the most important benefits of improved matching is the much-desired reduction in the minimum operating voltage of the classic 6T SRAM.  While the transistor matching data clearly show an advantage, putting it all together into a quantized FinFET SRAM cell with correct beta and gamma ratios and device centering to actually achieve low Vmin is a larger challenge.
Additionally, there may be other factors present in the scaled-up SRAM array that may not be so evident in the classic Pelgrom analysis from which most matching data are derived, such as some perturbation to line-edge-roughness, or nfet/pfet interactions, or any number of other possibilities.

Our data demonstrate that these concerns are surmountable and that real SOI FinFET SRAMs can operate at very low voltages. Figure 3 shows remarkable results on an SRAM array, with full read and write operation down to 400mV, without any assist circuitry.  This is among the best results ever reported, even among those that utilize boost techniques and in-situ tuning of the devices.

Figure 3: Shmoo plot of 14nm SOI FinFET SRAM array showing a minimum operating voltage of 400mV, with full read and write capability. This result, as good or better than any yet reported, was obtained without benefit of the chip-specific tuning techniques associated with planar fully depleted devices or specialized independent double-gate FinFETs.

Low Voltage Circuit Operation
A considerable improvement in electrostatics associated with the FinFET over conventional doped devices not only enables the necessary gate-length scaling, but simultaneously improves the relative performance at reduced voltage and therefore reduces the power density at a given performance.  While fully-depleted devices should in principle enjoy this advantage, the introduction of non-uniformity such as is involved with the tapered fin profile associated with bulk-based FinFET seriously compromises the output conductance and may obviate these expectations, as shown in Figure 4.

Figure 4: Representative bulk-based and SOI-based fin profiles, and corresponding empirical degradation in electrostatics. The tapered shape of the bulk fin shown results in nonuniform current flow and poorer low-voltage operation and self-gain than the more ideally shaped SOI FinFET.

The fin profile obtainable in SOI-based FinFETs is very nearly ideal and our data show that the low voltage benefits are fully realized in hardware.  The frequencies of a suite of ring oscillator circuits (inverter, NANDs, and NORs) were measured on 14nm SOI-based FinFET hardware as a function of voltage and compared to the modeled expectations.
Figure 5 shows excellent correspondence with expectation, and also shows how the data are far superior to the voltage dependence of conventional planar technology.

Figure 5: Normalized frequency reduction as a function of Vdd for a suite of circuits (NANDs, NORs, and inverters). Near-perfect correspondence of the SOI FinFET data with the compact model is shown. This flatter voltage dependence is highly superior to that typical of doping-controlled planar technology.

Conclusion
Several key elements of the putative advantages of FinFETs over conventional devices have been demonstrated in hardware.  By using SOI-based FinFET technology, the need for doping in the body has been effectively minimized, resulting in excellent matching characteristics in the undoped DRAM transfer device, and truly remarkable minimum operating voltage in the SRAM.  Additionally, the superior voltage dependence and stacked-fet circuit behavior relative to conventional devices has also been demonstrated through measurements of ring oscillators of various sorts.

From SEMICON West 2013: Paul Boudre of Soitec

Thursday, October 24th, 2013
YouTube Preview Image

Soitec’s COO Paul Boudre talks about the competitiveness of full-depleted planar with full-depleted finfet; capacity issues for SOI in light of ST’s open foundry model; and growth of High Resistivity SOI in the RF implementation on smart phones.

Innovative Wafers For Energy-Efficient CMOS Technology

Thursday, October 18th, 2012

For continued attractiveness and competitiveness of advanced electronic appliances such as smartphones, TVs, notebooks or tablets, the semiconductor industry is moving to “fully depleted” transistor technology to build integrated circuits. This technology comes in two flavors: planar and tri-dimensional (FinFET), each with its own advantages and challenges. This White Paper explains how innovative wafers, which are the foundations of silicon chips, will play a role to enable or facilitate the introduction of the planar and non-planar approaches to fully depleted technology, starting at the 28nm node. It also outlines the benefits that users can expect.

To view this white paper, click here.