Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘SOI’

Next Page »

Germanium Junctions for CMOS

Tuesday, November 25th, 2014

thumbnail

By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

It is nearly certain that alternate channel materials with higher mobilities will be needed to replace silicon (Si) in future CMOS ICs. The best PMOS channels are made with germanium (Ge), while there are many possible elements and compounds in R&D competition to form the NMOS channel, in part because of difficulties in forming stable n-junctions in Ge. If the industry can do NMOS with Ge then the integration with Ge PMOS would be much simpler than having to try to integrate a compound semiconductor such as gallium-arsenide or indium-phosphide.

In considering Ge channels in future devices, we must anticipate that they will be part of finFET structures. Both bulk-silicon and silicon-on-insulator (SOI) wafers will be used to build 3D finFET device structures for future CMOS ICs. Ultra-Shallow Junctions (USJ) will be needed to make contacts to channels that are nanoscale.

John Borland is a renowned expert in junction-formation technology, and now a principle with Advanced Integrated Photonics. In a Junction Formation side-conference at SEMICON West 2014, Borland presented a summary of data that had first been shown by co-author Paul Konkola at the 2014 International Conference on Ion Implant Technology. Their work on “Implant Dopant Activation Comparison Between Silicon and Germanium” provides valuable insights into the intrinsic differences between the two semiconducting materials.

P-type implants into Ge showed an interesting self-activation (seen as a decrease in of p-type dopant after implant, especially for monomer B as the dose increases.  Using 4-Point-Probe (4PP) to measure sheet-resistance (Rs), the 5E14/cm2 B-implant Rs was 190Ω/□ and at higher implant dose of 5E15/cm2 Rs was 120Ω/□. B requires temperatures >600°C for full activation in PMOS Ge channels, and generally results in minimal dopant diffusion for USJ.

Figure 1 shows a comparison between P, As, and Sb implanted dopants at 1E16/cm2 into both a Si wafer and 1µm Ge-epilayer on Si after various anneals. The sheet-resistance values for all three n-type dopants were always lower in Ge than in Si over the 625-900°C RTA range by about 5x for P and 10x for As and Sb. Another experiment to study the results for co-implants of P+Sb, P+C, and P+F using a Si-cap layer did not show any enhanced n-type dopant activation.

Fig.1: Sheet-resistance (Rs) versus RTA temperatures for P, As, and Sb implanted dopants into Ge and Si. (Source: Borland)

Prof. Saraswat of Stanford University showed in 2005—at the spring Materials Research Society meeting— that n-type activation in Ge is inherently difficult. In that same year, Borland was the lead author of an article in Solid State Technology (July 2005, p.45) entited, “Meeting challenges for engineering the gate stack”, in which the authors advocated for using a Si-cap for P implant to enable high temperature n-type dopant activation with minimal diffusion for shallow n+ Ge junctions that can be used for Ge nMOS. Now, almost 10 year later, Borland is able to show that it can be done.

Ge Channel Integration and Metrology

Nano-scale Ge channels wrapped around 3D fin structures will be difficult to form before they can be implanted. However, whether formed in a Replacement Metal Gate (RMG) or epitaxial-etchback process, one commonality is that Ge channels will need abrupt junctions to fit into shrunk device structures. Also, as device structures have continued to shrink, the junction formation challenges between “planar” devices and 3D finFET have converged since the “2D” structures now have nano-scale 3D topography.

Adam Brand, senior director of transistor technology in the Advanced Product Technology Development group of Applied Materials, explained that, “Heated beamline implants are best when the priority is precise dose and energy control without lattice damage. Plasma doping (PLAD) is best when the priority is to deliver a high dose and conformal implant.”

Ehud Tzuri, director strategic marketing in the Process Diagnostic and Metrology group at Applied Materials reminds us that control of the Ge material quality, as specified by data on the count and lengths of stacking-faults and other crystalline dislocations, could be done by X-Ray Diffraction (XRD) or by some new disruptive technology. Cross-section Transmission Electron Microscopy (X-TEM) is the definitive technology for looking at nanoscale material quality, but since it is expensive and the sample must be destroyed it cannot be used for process control.

Figure 2 shows X-TEM results for 1 µm thick Ge epi-layers after 625°C and 900°C RTA. Due to the intrinsic lattice mis-match between Ge and Si there will always be some defects at the surface, as indicated by arrows in the figure. However, stacking faults are clearly seen in the lower RTA sample, while the 900°C anneal shows no stacking-faults and so should result in superior integrated device performance.

Fig. 2: Cross-section TEM of 1µm Ge-epi after 625°C and 900°C RTA, showing great reduction in stacking-faults with the higher annealing temperature. (Source: Borland)

Borland explains that the stacking-faults in Ge channels on finFETs would protrude to the surface, and so could not be mitigated by the use of the “Aspect-Ratio Trapping” (ART) integration trick that has been investigated by imec. However, the use of a silicon-oxide cap allows for the use of 900°C RTA which is hot enough to anneal out the defects in the crystal.

Brand provides an example of why integration challenges of Ge channels include subtle considerations, “The most important consideration for USJ in the FinFET era is to scale down the channel body width to improve electrostatics. Germanium has a higher semiconductor dielectric constant than silicon so a slightly lower body width will be needed to reach the same gate length due to the capacitive coupling.”

Junction formation in Ge channels will be one of the nanoscale materials engineering challenges for future CMOS finFETs. Either XRD or some other metrology technology will be needed for control. Integration will include the need to control the materials on the top and the bottom surfaces of channels to ensure that dopant atoms activate without diffusing away. The remaining challenge is to develop the shortest RTA process possible to minimize all diffusions.

— E. K.

RF and MEMS Technologies to Enable the IoT

Friday, October 24th, 2014

thumbnail

By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

The “Internet of Things” (IoT) has been seen as the next major market that will demand high volumes of integrated circuits (IC). The IoT can be loosely defined as a network of small, low-cost, ubiquitous electronic devices where sensing data and communicating information occurs without direct human intervention. Each device would function as a “smart node” in the network by doing some low-level signal processing to filter signals from noise, and to reduce the bandwidth needed for node-to-node communications. The nodes will need to communicate up to some manner of a “cloud” for secure memory storage and to bounce actionable information down to humans.

Figure 1 shows a conservative forecast of the global IoT market that was recently published by IDC. IDC expects the worldwide IoT installed base to experience a compound annual growth rate (CAGR) of 17.5% from 2013 to 2020, starting from 9.1 billion smart nodes installed at the end of 2013 and growing to 28.1 billion units by 2020.

FIGURE 1: Forecast for global IoT applications revenue 2013-2020. Note that smart node “intelligent systems/devices” provide the foundation for this huge growing market. (Source: IDC)

Due to the anticipated elastic-demand for IoT devices that would come from cost reductions, the forecasts for the number of IoT nodes ranges to 50 billion or even 80 billion by the year 2020, as documented in the recent online Pete’s Post “Don’t Hack My Light Bulb, Bro”. The post also provides an excellent overview of recent discussions regarding the host of additional technology and business challenges associated with the enterprise infrastructure and security issues surrounding the integration of vast streams of new information.

As shown in Figure 1, the smart nodes form the foundation for the whole IoT. Consequently, the world will need low-cost high-volume manufacturing (HVM) technologies to create the different functionalites needed for smart nodes. Sensor- and logic-technologies to enable IoT smart nodes will generally evolve from existing IC applications, while R&D continues in Radio Frequency (RF) communications and in Micro Electro-Mechanical Systems (MEMS) energy harvesting.

RF Technology

IoT smart-nodes will use wireless RF technologies to communicate between themselves and with the “cloud.” In support of rapid growth in the 71-86 GHz RF “E-band” telecom backhaul segment—which transports data from cell sites in the peripheral radio access network (RAN) to the wireless packet core—Presto Engineering recently announced a non-captive production-scale testing service for 50µm-thin gallium arsenide wafers.

Silicon-On-Insulator (SOI) substrate supplier Soitec has excellent perspective on the global market for RF chips, since it’s High-Resistivity SOI (HR-SOI) wafers are widely used in commercial fabs. Bernard Aspar, senior vice president and general manager of the Communications and Power business unit of Soitec, explained to SemiMD in an exclusive interview why the market for RF chips is growing rapdily. RF front-end module unit sales are forecasted to increase at a CAGR of ~16% over the period of 2013-2017, while the area of silicon needing to be delivered could actually increase at ~30% CAGR. RF chips are increasing in average size due to the need to integrate multiple standards for wireless communications and multiple antenna switches. “The first components to be integrated in silicon were the antenna switches, moving from 70% on GaAs in 2010 to more than 80% on SOI in 2014,“ said Aspar.

Soitec claims that >80% of smart-phones today use an RF chip built on a wafer from the company, based on sales last year of >300k 200mm HR-SOI wafers. Due to anticipated future growth in RF demand, the company has plans to eventually move HR-SOI production to 300mm diameter wafers. Most of the anticipated demand will be for the company’s new variant of HR-SOI called eSI (“enhanced Signal Integrity”previously called “Trap Rich”) with a measured effective resistivity as high as 10 kOhm-cm for improved device performance.

This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) and purely capacitive crosstalk similar to quartz substrates. HR-SOI substrates in general demonstrate reduced harmonics compared with standard SOI substrates, and the eSI wafers reduce harmonics to the point that they can be considered as lossless. Soitec was recently given a Best Partnership Award by Sony Semiconductor for supplying RF substrates.

“We’re also adding value to the substrate because it allows for simplification of the fab processing,” said Aspar. The eSI wafers enable much higher linearity and isolation, helping designers to address some of the most advanced LTE requirements at competitive costs. These substrates also provides benefits for the integration of passives, such as the quality factor of spiral inductors or tunable MEMS capacitors.

Vibrational Energy Harvesting

IoT smart nodes will need electrical power to function, and batteries that must be replaced or charged by an external source create issues for ubiquitous always-on small devices. In principle the ambient energies of the environment can be harvested to power smart nodes, and to do so we may consider using thermoelectric, photovoltaic, and piezoelectric properties of thin-films. Thermoelectric and photovoltaic devices both require somewhat specialized ambients for efficient energy harvesting, while piezoelectric devices can extract energy from subtle vibrations almost anywhere in the world (Fig. 2).

FIGURE 2: Schematic cross-section of piezoelectric cantilever with end mass, depicted in connection to an energy-harvesting circuit. (Source: Science)

Researchers in the Energy Harvesting and Mechatronics Research Lab at Stony Brook University, New York, recently published an excellent overview of the potential for 1 W to 100 kW piezoelectronic energy harvesting in building, automobiles, and wearables electronics in the Journal of Intelligent Material Systems and Structures 24(11) 1405-1430. However, the largest forecasted growth in the IoT is for small devices that would consume µW to mW of active power.

For low-cost and low-power consumption, the logic chips for IoT smart nodes are expected to be made using a 65nm “trailing edge” fab process. For example, CAST Inc. has developed a 32-bit BA20 embedded processor core that can deliver 3.41 CoreMarks/MHz at a maximum frequency of 75 MHz. Using TSMC’s 65nm Low Power fab process, it occupies only 0.01 mm2 of silicon area while consuming 2 µW/MHz. Thus, at maximum speed the chip core would consume just 150µW.

MicroGen Systems, Inc. (MicroGen) is a privately held company developing thin piezoelectric energy harvesters, based on technology from Cornell University’s NanoScale Science and Technology Facility. Founded in 2007, MicroGen has headquarters and R&D in the Ithaca and Rochester, NY areas, and volume manufacturing with X-FAB in Itzehoe, Germany. Figure 3 shows one of the company’s ~100 mm2 area chips featuring an aluminum nitride (AlN) peizoelectric thin-film on a cantilever that produces alternating current (AC) electricity in response to external vibrations. Different cantilever designs allow for harvesting energy from either single-frequency or broadband vibrations. At resonance the AC power output is maximized, so it can be ~100 µW at 120Hz and 0.1g, or ~900 µW at 600Hz and 0.5g.

FIGURE 3: BOLT™-R0600 energy-harvesting chip without packaging. The green-silver trapezoidal area is a 25-100µm thick cantilever (with several thin-film layers including an AlN piezoelectric) attached to grey rectangular end mass (silicon). A fixed-frequency device, at resonance of ~600Hz it can produce ~900 µWatts of AC power. (Source: MicroGen Systems)

For any piezoelectric energy harvester there are basic materials properties that must be optimized, including the piezoelectric strain constant as well as the electromechanical coupling factor of the thin-film to the moving mass. Lead-zirconium-titanate (PZT) has been the most studied piezoelectric thin-film due to high strain constant and ability to couple to a substrate though the use of buffer layers.

S. H. Baek, et al. showed “Piezoelectric MEMS with Giant Piezo Actuation” in Science 18 November 2011, Vol 344 using lead-manganese-niobate with lead-titanate (PMN-PT) layers epitaxially grown on a strontium-titanate (STO) buffer layer over 4°-off-axis(001)Si. Figure 4 shows both the transverse piezoelectric coefficient (C/m2) and the energy-harvesting figure of merit (GPa) for this and other thin-films. Note that to acheive stable “giant” piezoelectric effects the PMN-PT layer had to be grown epitaxially with precise control over the STO grain orientation.

FIGURE 4: Transverse piezoelectric coefficient (C/m2) and the energy-harvesting figure of merit (GPa) for PMN-PT (“this work”) and other piezoelectric thin-films. (Source: Science)

—E.K.

Blog review August 4, 2014

Monday, August 4th, 2014

Innovation is alive and well in the semiconductor industry. That was a key takeaway from the strategic investor panel at the second annual Silicon Innovation Forum at SEMICON West, and one I can’t reinforce enough within the venture capital (VC) community. Eileen Tanghal of Applied Materials reports.

At SEMICON West this year in Thursday morning’s Yield Breakfast sponsored by Entegris, top executives from Qualcomm, GlobalFoundries, and Applied Materials discussed the challenges to achieving profitable fab yield for atomic-scale devices. In his blog, Ed Korzynski reports on what was discussed.

Phil Garrou blogs that Apple has acquired 24 tech companies in the last 18 months. Recently, Apple acquired LuxVue, a start-up focused on low power micro-LED displays. Although Apple has not disclosed any details of the acquisition, not even the purchase price, one can easily envision where micro LED displays could play a big part in Apples thrust into wearable electronics such as the i-watch, Phil says.

Adele Hars continued a report on the SOI papers at the VLSI Symposia in this Part 2 installment. The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry.

Vivek Bakshi created a EUV stir, blogging about IBM’s NXE3300B scanner, at the EUV Center of Excellence in Albany, which recently completed a “40W” EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.

Scouting report for materials at end of the road: 2013 ITRS

Monday, May 12th, 2014

Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The IC fabrication industry is approaching the end of the road for device miniaturization, with both atomic and economic limits looming on the horizon. New materials are widely considered as key to the future of profitable innovation in ICs, so everyone from process engineers to business pundits needs to examine the Emerging Research Materials (ERM) chapter of the just published 2013 edition of the International Technology Roadmap for Semiconductors (ITRS).

The 2013 ITRS covers both near-term (2014-2020) and long-term (2020 onward) perspectives on what materials and processes would be desired to build ideal ICs (Fig. 1, Table ERM15). However, to properly understand the information in the current edition we need to consider the changes in the IC fab industry since 1992 when the first edition of the ITRS’s predecessor was published as the U.S. National Technology Roadmap for Semiconductors (NTRS).

Fig. 1

Twenty-two years ago, the industry had dozens of fabs working on next-generation technology, and with lithographic scaling dominating innovation there was broad consensus on gradual materials evolutions. Today, the industry has 3 logic fabs and about as many memory lines pushing processes to smaller geometries, and each fab may use significantly different revolutionary materials. The result today is that there is little consensus on direction for new materials, and at best we can quantify the relative benefits of choosing one or another of the many options available.

In fact, with just a few players left in the game, there is much to lose for any one player to disclose strategic plans such as the use of revolutionary materials. Mark Thirsk, managing partner with specialty materials analysts Linx Consulting, commented, “We built our business based on anonymizing and generalizing the world, and then predicting the future based on big categorical buckets. But now there are a very few number of people pushing the boundaries and we’re being asked to model specific fab processes such as those for Intel or TSMC.”

For all of the above reasons, the current ITRS might be better understood as a scouting report that quantifies the roughness of the terrain when our current roads end. Exotic materials such as graphene and indium-gallium-phosphide may be used as alternate materials for the Si channels in transistors, novel stacks of atomic-layers may be used as electrical contacts, and spintronics and single-electron devices may one day replace DRAM and Flash chips for solid-state memory chips. However,  “significant challenges” exist in integrating any of these new technologies into high-volume manufacturing.

In the near-term, Cu wires clad with various metal barriers are projected to provide the best overall performance for on-chip interconnects.  As stated in the 2013 Executive Summary, “Unfortunately no new breakthroughs are reported for interconnections since no viable materials with resistivity below copper exist. However, progress in manipulation of edgeless wrapped materials (e.g., carbon nanotubes, graphene combinations etc.) offer the promise of ‘ballistic conductors,’ which may emerge in the next decade.”

Specialty Materials Suppliers

Fig. 2

Figure 2 (Figure ERM5) shows the inherent complexity involved in the stages of developing a new chemical precursor for use in commercial IC production. The chapter summarizes the intrinsic difficulty of atomic-scale R&D for future chips as follows:

A critical ERM factor for improving emerging devices, interconnects, and package technologies is the ability to characterize and control embedded interface properties. As features approach the nanometer scale, fundamental thermodynamic stability considerations and fluctuations may limit the ability to fabricate materials with tight dimensional distributions and controlled useful material properties.

In addition to daunting technical issues with pre-cursor R&D, the business model for chemical suppliers is being strained by industry consolidation and by dimensional shrinks. Consolidation means that each fab has unique pre-cursor requirements, so there may be just one customer for a requested chemistry and no ability to get a return on the investment if the customer decides to use a different approach.

Shrinks down to atomic dimensions means that just milliliters instead of liters of chemistry may be needed. For example, atomic-layer deposition (ALD) precursor R&D requires expertise and investment in molecular- and chemical-engineering, and so significant sunk costs to create any specialty molecule in research quantities. “We’ll have an explosion of precursors required based on proprietary IP held by different companies,” reminds Thirsk. “The people who are being asked to develop the supply-chain of ever increasing specifications are simultaneously being squeezed on margin and volumes.”

For materials such as Co, Ru, La, and Ti-alloys to be used in fabs we need to develop more than just deposition and metrology steps. We will also likely require atomic-level processes for cleaning and etch/CMP, which can trigger a need for yet another custom material solution.

Established chemical suppliers—such as Air Liquide, Dow, DuPont, Linde, Praxair, and SAFC—run international businesses serving many industries. IC manufacturing is just a small portion of their businesses, and they can afford to simply walk-away from the industry if the ROI seems unattractive. “We’re finding more and more that, for example in wet cleaning chemistry, the top line of the market is flat,” cautioned Thirsk. “You can find some specialty chemistries that provide better profits, but the dynamics of the market are such that there’s reduced volume and reduced profitability. So where will the innovation come from?”

Alternate Channel Materials

With finFETs and SOI now both capable of running in fully-depleted mode, alternative materials to strained silicon are being extensively explored to provide higher MOSFET performance at reduced power. Examples include III-V semiconductors, Ge, graphene, carbon nanotubes, and other semiconductor nanowires (NW). To achieve complimentary MOS high performance, co-integration of different materials (i.e. III-V and Ge) on Si may be necessary. Significant materials issues such as defect reduction, interface chemistry, metal contact resistivity, and process integration must be addressed before such improvements can be achieved.

Nano-wire transistors

Top down fabricated nanowires (NW) are one-dimensional structures that can be derived from two-dimensional finFETs. Patterned and etched <5nm Si NW have been reported to have room temperature quantum oscillatory behavior with back-gate voltage with a peak mobility approaching ∼900 cm2/Vs. Despite extensive R&D, grown Si NW demonstrate no performance improvements over patterned-and-etched NW, and controlled growth in desired locations remains extraordinarily challenging. Overall, significant challenges must be overcome for NW to be integrated in high density, particularly when targeting laterally placed NW with surround gates and low resistance contacts.

—E.K.

Blog review May 5, 2014

Monday, May 5th, 2014

Jeremy Read of Applied Materials writes that while some consumer IoT applications will require semiconductors manufactured using cutting-edge technologies the vast majority of chips will be used in client-side applications. These chips, such as a sensor monitoring room temperature in a connected HVAC system, require processing capabilities that can be met using legacy process (90 and 45nm) technologies manufactured on 200mm wafers.

Ali Khakifirooz of Spansion notes that body biasing has been long considered as an effective and relatively easy way to compensate for some of the process variations. Not only does it lead to a tighter performance distribution and better yield, but also by mitigating the guardband requirements for process corners and temperature variation, it leads to better performance and faster design cycle.

Frank Feng of Mentor Graphics blogs that transistor and gate levels of library design are normally delivered fully vetted for reliability issues such as electrostatic discharge (ESD), latch-up, electrical overstress (EOS), and dielectric breakdown. However, when designers assemble transistors and gates into intellectual property (IP), blocks, or whole chip designs, they encounter a variety of reliability problems generated across interconnect layers or across device regions of PSUB and NWELL bodies.

Phil Garrou has not been predicting the end of the world, but rather the end of electronics as we know it, i.e.,relying on CMOS scaling. He blogs that it was with great anticipation that he perused the 2013 ITRS roadmap that was released a few weeks ago. He is happy to tell you they are facing the challenges head on although the ultimate solutions are, as we might expect, not yet crystal clear.

Pete Singer writes that the newly revamped International Technology Roadmap for Semiconductors was released in early April. It’s actually called the 2013 ITRS, which makes it seem already out of date, but that’s the way the numbering has always been. The latest ITRS highlights 3D power scaling, system level integration and a new chapter on big data.

Blog review April 14, 2014

Monday, April 14th, 2014

The increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. Dr. Roawen Chen of Qualcomm says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In a keynote talk at The ConFab, titled “what’s on our mind?” Dr. Chen will deliberate on a number of headwinds and opportunities.

Jean-Eric Michallet, Hughes Metras and Perrine Batude of CEA-Leti describe how the research group has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.

Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a review of the keynote by AMD’s Bryan Black, titled“Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” Garrou also reviews the newly announced STATSChipPAC FlexLine, which uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.

Karen Savala, president, SEMI Americas, blogs about the sustainable manufacturing imperative, noting that sustainability is increasingly considered a differentiating factor in global competitiveness relative to the technologies and products being provided. In conjunction with SEMICON West and INTERSOLAR North America, SEMI is organizing a four-day Sustainable Manufacturing Forum to share information about the latest technologies, products, and management approaches that promote sustainable manufacturing.

Blog review March 10, 2014

Monday, March 10th, 2014

Pete Singer is pleased to announce that IBM’s Dr. Gary Patton will provide the keynote talk at The ConFab on Tuesday, June 24th. Gary is Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, and has responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances.

Nag Patibandla of Applied Materials describes a half-day workshop at Lawrence Berkeley Lab that assembled experts to discuss challenges and identify opportunities for collaboration in semiconductor manufacturing including EUV lithography, advanced etch techniques, compound semiconductors, energy storage and materials engineering.

Adele Hars of Advanced Substrate News reports on a presentation by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during SEMI’s recent ISS Europe Symposium. FD-SOI is significantly cheaper, outdoes planar bulk and matches bulk FinFET in the performance/power ratio, and keeps the industry on track with Moore’s Law, she writes.

Phil Garrou reports on the RTI- Architectures for Semiconductor Integration & Packaging (ASIP) conference, which is focused on commercial 3DIC technology. Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing. In addition Tezzaron’s Robert Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly.

Vivek Bakshi, EUV Litho, Inc., blogs that most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM).

On March 2, 2014 SIA announced that worldwide sales of semiconductors reached $26.3 billion for the month of January 2014, an increase of 8.8% from January 2013 when sales were $24.2 billion. After adding in semiconductor sales from excluded companies such as Apple and Sandisk, that total is even higher, marking the industry’s highest-ever January sales total and the largest year-to-year increase in nearly three years. These results are in-line with the Semico IPI index which has been projecting strong semiconductor revenue growth for the 1st and 2nd quarters of 2014.

Blog review February 24, 2014

Monday, February 24th, 2014

Paul Farrar, general manager of the G450C consortium, said early work has demonstrated good results and that he sees no real barriers to implementing 450mm wafers from a technical standpoint. But as Pete Singer blogs, he also said: “In the end, if this isn’t cheaper, no one is going to do it,” he said.

Adele Hars of Advanced Substrate News reports that body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages.

Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc., says the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation. This is putting more emphasis on high sigma yield.

Jamie Girard, senior director, North America Public Policy, SEMI President Obama touched on many different policy areas during his State of the Union talk, and specifically mentioned a number of issues that are of top concern in the industry and with SEMI member companies. Among these are funding for federal R&D, including public-private partnerships, trade, high-skilled immigration reform, and solar energy.

Phil Garrou finishes his look at the IEEE 3DIC meeting, with an analysis of presentations from Tohoku University, Fujitsu’s wafer-on-wafer (WOW), ASE/Chiao Tung University and RTI. In another blog, Phil continues his review of the Georgia Tech Interposer conference, highlighting presentations from Corning, Schott Glass, Asahi Glass, Shinko, Altera, Zeon and Ushio.

Pete Singer recommends taking the new survey by the National Center for Manufacturing Sciences (NCMS) but you may first want to give some thought as to what is and what isn’t “nanotechnology.”

Blog review January 21, 2014

Tuesday, January 21st, 2014

Zvi Or-Bach, President and CEO of MonolithIC 3D weighs in on the battle of Intel vs TSMC in the foundry space, after conflicting stories appeared. One said that Intel had a huge pricing advantage over TSMC, and a second story noted TSMC’s boast that it was “far superior” to Intel and Samsung as a partner fab.

Adele Hars looks back at 2013 from the SOI perspective. In this “Part 2” post, she focuses on developments that last year brought in the areas of RF-SOI and SOI-FinFETs. Part 1 focused on the general SOI picture. Stayed tuned for a look at 2014.

Phil Garrou reports on some of the key 3DIC presentations from the IEEE Internal Electron Devices Meeting (IEDM), held in December in Washington, D.C. , focusing on papers from Micron, TSMC, Tohoku Univ., NC State and ASET. He said that Micron’s Naga Chandrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking, noting that he does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.

Blog review January 13, 2014

Monday, January 13th, 2014

Why is Silicon Valley the world center for innovation? How does innovation continue to thrive there? How do you create and maintain an innovative culture? These and other thought-provoking questions were the topics of discussion on a recent episode of Inside Silicon Valley, a public affairs program. Eric Witherspoon of Applied Materials blogs about these questions and various answers.

Adele Hars blogs that 2014 is going to be a terrific year for the greater SOI community, with 28nm FD-SOI ramping in volume and 14nm debuting, plus RF-SOI continuing its stellar rise. In this post she takes a look back at some of the SOI-related highlights from 2013.

Phil Garrou provides details on the most notable packaging papers presented at the 2013 IWLPC Conference held in San Jose CA this past fall, including those from Rudolph, Nanium and Deca. He also comments on the rumors that ASML has delayed its 450mm EUV efforts.

Pete Singer blogs from this week’s ISS. Keynote Rick Wallace, president and CEO of KLA-Tencor said the semiconductor industry could be approaching a “Concorde moment” where economic factors overtake technical capabiltiies. Wallace also sees a need to boost innovation, and suggests the way to best do that is encourage young people to get excited about the “magic behind the gadget.”

Next Page »