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SOI: Revolutionizing RF and expanding in to new frontiers

Friday, April 17th, 2015

By Peter A. Rabbeni, Director, RF Segment Marketing and Business Development, GLOBALFOUNDRIES

Faster connections and greater network capacity for wireless technologies such as LTE, WiFi, and the Internet of Things is driving the demand for more complex radio circuit designs and multi-band operation.  In addition the emergence of wirelessly connected smart wearables is not only driving localized high performance processing power but also extended battery life, two goals which are often in conflict. The predicted explosion in the IoT is shown in Figure 1.

Figure 1. More than 30 billion devices are forecast to be connected to the internet by 2018 (Source: BI Intelligence).

The rapid growth in smartphones and tablet PCs and other mobile consumer applications has created an opportunity and demand for chips based on RF-SOI technology, particularly for antenna interface and RF front end components such as RF switches and antenna tuners.  As a low cost and more flexible alternative to expensive gallium arsenide (GaAs) technologies, the vast majority of RF switches today are built on RF-SOI.

To address the highly complex, multi-band and multi-standard designs, RF front-end modules (RF FEM) require integration of multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management. Today these functions are addressed by different technologies. The RF SOI process technology enables design flexibility by integrating multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management to be integrated—all on the same die. The benefit of integrated radios is they consume   less power and smaller area than traditional radios. Therefore, mobile devices that exploit radio integration using RFSOI can offer more functions with better RF performance at competitive cost.

Mobile devices that implement RF SOI for RF Front End module functions benefit from higher levels of integration that combine with improved linearity and insertion loss, which translates to better transmitter efficiency and thus longer battery life enabling longer talk times (lower power) and faster downloads (higher signal-to-noise ratio).

Emerging technologies like RF-SOI and even FD-SOI have unique properties and capabilities beneficial in enabling RF circuit innovation and integration levels never before seen in silicon-based technologies.  Device ft, gm/I, well bias control and inherent isolation of the substrate all contribute to improved system level performance over competing technology resulting in the ability to achieve higher linearity, lower power, low loss, and low cost/small size.

Innovative solutions

An innovative technology that is currently addressing the ever-increasing challenges of RF front-end design is UltraCMOS 10 (Figure 2). This customer specific process, co-developed by GLOBALFOUNDRIES and Peregrine Semiconductor, demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions. For designers, it dramatically reduces the required engineering and validation time. And, for the end-user, they benefit from longer battery life, better reception, faster data rates and wider roaming range. With the qualification process complete, UltraCMOS 10 technology is now a fully qualified technology platform.

Figure 2. UltraCMOS 10 technology demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions (Source: Peregrine Semiconductor).

High speed digital-to-analog converters (DAC) are an essential component for direct-to-RF conversion architectures. Faster converter sampling speeds and greater peak-to-peak signal fidelity hold high promise in moving mobile digital signal processing closer to the antenna. It has been demonstrated that DACs on fully depleted SOI, achieve high linearity and very low power for nyquist bandwidths as wide as 5.5GHz. The RF architecture with a high-performance DAC results in lower power dissipation while synthesizing very wideband signals (Figure 3). This further demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna.

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Figure 3. Low power RF DAC demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna [1

Agile radio architectures are another key area that can address mobile architecture challenges and cost. Today, the analog RF frontend duplicates much of the circuitry for each band. To simplify, new advancements (Figure 4) in tunable structures and filters are being made to provide a single radio for multi-band/multi-mode frequency. SOI technology offers the possibility to develop tunable/reconfigurable RF FEMs to improve RF performance at competitive cost.

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Figure 4. Cutting-edge developments in tunable filters [2

Creating an Ecosystem to Extend SOI to RF

As RF FEM architectures and design challenges become more and more complex, it becomes necessary to relieve some of the increased burden at all levels of the value chain. In order to provide better RF products—from system design and RF integrated circuits down to engineered substrate design—development teams can no longer expect to design in silos and be successful. Collaboration and co-optimization are becoming much more important as a result of the changing dynamics of the design-technology landscape.

Investing in the future is critical to address certain RF challenges such as radio architecture design in multiband, multimode mobile radios and ultra-low power (ULP) wireless devices. Successful collaboration will require adherence to standards to enable interoperability, otherwise, in this fragmented market, the industry won’t see the full benefit of all of the technology innovation. To succeed, we need collaboration at different levels, from R&D to ensure we have the world’s best talent trying to solve all of these problems, all the way through to business models.

There is no doubt that demand on our networks will continue grow and there are advanced chip technology challenges the industry needs to address to enable a higher level of integration and lower power consumption for future wireless communication. GLOBALFOUNDRIES is committed to enabling an SOI portfolio and ecosystem—from process, device, and circuit through system level IP— to lower customer design barriers and complexity and introduce new RF architectures that leverage SOI-based technologies.

References

1. E. Olieman, A.-J. Annema and B. Nauta, “A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist,,” in VLSI Circuits Digest of Technical Papers, 2014 Symposium on , Honolulu, 2014.

2. Joeri Lechevallier, Remko Struiksma, Hani Sherry, Andreia Cathelin, Eric Klumpernik, Bram Nauta, “A Forward-Body-Bias Tuned 450MHz Gm-C 3rd-Order Low Pass Filter in 28nm UTBB FD-SOI with >1VdBVp IIP3 over a 0.7 to 1V Supply”, ISSCC, San Francisco, 2015.

Monolithic 3D processing using non-equilibrium RTP

Friday, April 17th, 2015

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By Ed Korczynski, Senior Technical Editor, Solid State Technology

Slightly more than one year after Qualcomm Technologies announced that it was assessing CEA-Leti’s monolithic 3D (M3D) transistor stacking technology, Qualcomm has now announced that M3D will be used instead of through-silicon vias (TSV) in the company’s next generation of cellphone handset chips. Since Qualcomm had also been a leading industrial proponent of TSV over the last few years while participating in the imec R&D consortium, this endorsement of M3D is particularly relevant.

Leti’s approach to 3D stacking of transistors starts with a conventionally built and locally-interconnected bottom layer of transistors, which are then covered with a top layer of transistors built using relatively low-temperature processes branded as “CoolCube.” Figure 1 shows a simplified cross-sectional schematic of a CoolCube stack of transistors and interconnects. CoolCube M3D does not transfer a layer of built devices as in the approach using TSV, but instead transfers just a nm-thin layer of homogenous semiconducting material for subsequent device processing.

Fig. 1: Simplified cross-sectional rendering of Monolithic 3D (M3D) transistor stacks, with critical process integration challenges indicated. (Source: CEA-Leti)

The reason that completed transistors are not transferred in the first place is because of intrinsic alignment issues, which are eliminated when transistors are instead fabricated on the same wafer. “We have lots of data to prove that alignment precision is as good as can be seen in 2D lithography, typically 3nm,” explained Maud Vinet, Leti’s advanced CMOS laboratory manager in an exclusive interview with SST.

As discussed in a blog post online at Semiconductor Manufacturing and Design (http://semimd.com/hars/2014/04/09/going-up-monolithic-3d-as-an-alternative-to-cmos-scaling/) last year by Leti researchers, the M3D approach consists of sequentially processing:

  • processing a bottom MOS transistor layer with local interconnects,
  • bonding a wafer substrate to the bottom transistor layer,
  • chemical-mechanical planarization (CMP) and SPE of the top layer,
  • processing the top device layer,
  • forming metal vias between the two device layers as interconnects, and
  • standard copper/low-k multi-level interconnect formation.

To transfer a layer of silicon for the top layer of transistors, a cleave-layer is needed within the bulk silicon or else time and money would be wasted in grinding away >95% of the silicon bulk from the backside. For CMOS:CMOS M3D thin silicon-on-insulator (SOI) is the transferred top layer, a logical extension of work done by Leti for decades. The heavy dose ion-implantation that creates the cleave-layer leaves defects in crystalline silicon which require excessively high temperatures to anneal away. Leti’s trick to overcome this thermal-budget issue is to use pre-amorphizing implants (PAI) to completely dis-order the silicon before transfer and then solid-phase epitaxy (SPE) post-transfer to grow device-grade single-crystal silicon at ~500°C.

Since neither aluminum nor copper interconnects can withstand this temperature range, the interconnects for the bottom layer of transistors need to be tungsten wires with the highest melting point of any metal but somewhat worse electrical resistance (R). Protection for the lower wires cannot use low-k dielectrics, but must use relatively higher capacitance (C) oxides. However, the increased RC delay in the lower interconnects is more than offset by the orders-of-magnitude reduction in interconnect lengths due to vertical stacking.

M3D Roadmaps

Leti shows data that M3D transistor stacking can provide immediate benefit to industry by combining two 28nm-node CMOS layers instead of trying to design and manufacture a single 14nm-node CMOS layer:  area gain 55%, performance gain 23%, and power gain 12%. With cost/transistor now expected to increase with sequential nodes, M3D thus provides a way to reduce cost and risk when developing new ICs.

For the industry to use M3D, there are some unique new unit-processes that will need to ramp into high-volume manufacturing (HVM) to ensure profitable line yield. As presented by C. Fenouillet-Beranger et al. from Leti and ST (paper 27.5) at IEDM2014 in San Francisco, “New Insights on Bottom Layer Thermal Stability and Laser Annealing Promises for High Performance 3D Monolithic Integration,” due to stability improvement in bottom transistors found through the use of doping nickel-silicide with a noble metal such as platinum, the top MOSFET processing temperature could be relaxed up to 500°C. Laser RTP annealing then allows for the activation of top MOSFETs junctions, which have been characterized morphologically and electrically as promising for high performance ICs.

Figure 2 shows the new unit-processes at <=500°C that need to be developed for top transistor formation:

*   Gate-oxide formation,

*   Dopant activation,

*   Epitaxy, and

*   Spacer deposition.

Fig. 2: Thermal processing ranges for process modules need to be below ~500°C for the top devices in M3D stacks to prevent degradation of the bottom layer. (Source: CEA-Leti)

After the above unit-processes have been integrated into high-yielding process modules for CMOS:CMOS stacking, heterogeneous integration of different types of devices are on the roadmap for M3D. Leti has already shown proof-of-concept for processes that integrate new IC functionalities into future M3D stacks:

1)       CMOS:CMOS,

2)       PMOS:NMOS,

3)       III-V:Ge, and

4)       MEMS/NEMS:CMOS.

Thomas Ernst, senior scientist, Electron Nanodevice Architectures, Leti, commented to SST, “Any application that will need a ‘pixelated’ device architecture would likely use M3D. In addition, this approach will work well for integrating new channel materials such as III-V’s and germanium, and any materials that can be deposited at relatively low temperatures such as the active layers in gas-sensors or resistive-memory cells.”

Non-Equilibrium Thermal Processing

Though the use of an oxide barrier between the active device layers provides significant thermal protection to the bottom layer of devices during top-layer fabrication, the thermal processes of the latter  cannot be run at equilibrium. “One way of controlling the thermal budget is to use what we sometimes call the crème brûlée approach to only heat the very top surface while keeping the inside cool,” explained Vinet. “Everyone knows that you want a nice crispy top surface with cool custard beneath.” Using a laser with a short wavelength prevents penetration into lower layers such that essentially all of the energy is absorbed in the surface layer in a manner that can be considered as adiabatic.

Applied Materials has been a supplier-partner with Leti in developing M3D, and the company provided responses from executive technologists to queries from SST about the general industry trend to controlling short pulses of light for thermal processing. “Laser non-equilibrium heating is enabling technology for 3D devices,” affirmed Steve Moffatt, chief technology officer, Front End Products, Applied Materials. “The idea is to heat the top layer and not the layers below. To achieve very shallow adiabatic heating the toolset needs to ramp up in less than 100 nsec. In order to get strong absorption in the top surface, shorter wavelengths are useful, less than 800 nm. Laser non-equilibrium heating in this regime can be a critical process for building monolithic 3D structures for SOC and logic devices.”

Of course, with ultra-shallow junctions (USJ) and atomic-scale gate-stacks already in use for CMOS transistors at the 22nm-node, non-equilibrium thermal processing has already been used in leading fabs. “Gate dielectric, gate metal, and contact treatments are areas where we have seen non-equilibrium anneals slowly taking the place of conventional RTP,” clarified Abhilash Mayur, senior director, Front End Products, Applied Materials. “For approximate percentages, I would say about 25 percent of thermal processing for logic at the 22nm-node is non-equilibrium, and seen to be heading toward 50 percent at the 10nm-node or lower.”

Mayur further explained some of the trade-offs in working on the leading-edge of thermal processing for demanding HVM customers. Pulse-times are in the tens of nsec, with longer pulses tending to allow the heat to diffuse deeper and adversely alter the lower layers, and with shorter pulses tending to induce surface damage or ablation. “Our roadmap is to ensure flexibility in the pulse shape to tailor the heat flow to the specific application,” said Mayur.

Now that Qualcomm has endorsed CoolCube M3D as a preferred approach to CMOS:CMOS transistor stacking in the near-term, we may assume that R&D in novel unit-processes has mostly concluded. Presumably there are pilot lots of wafers now being run through commercial foundries to fine-tune M3D integration. With a roadmap for long-term heterogeneous integration that seems both low-cost and low-risk, M3D using non-equilibrium RTP will likely be an important way to integrate new functionalities into future ICs.

Synopsys founder has plenty of work to do, isn’t interested in politics

Thursday, March 26th, 2015

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By Jeff Dorsch, Contributing Editor

Aart de Geus is not running for governor of California.

The Synopsys chairman and co-CEO denied that speculation in meeting with journalists Monday morning at the 25th annual Synopsys Users Group Conference in Santa Clara, Calif. In any case, Governor Jerry Brown just began his last four-year term, and there’s not another gubernatorial election in the Golden State until 2018.

“I have a life so interesting,” de Geus said during an hour-long, freewheeling discussion of mostly technical topics. In addition to leading the electronic design automation, intellectual property, and software firm he founded in 1986, which had fiscal 2014 revenue of $2.057 billion, de Geus serves as the guitarist of Legally Blue, a blues band that regularly performs in Silicon Valley.

The political process in Sacramento and Washington, D.C., is plagued by “diffraction,” de Geus observed, leaving little or no public consensus on important issues, such as climate change and water supplies. Synopsys has provided corporate philanthropy for public education in the valley and the Second Harvest Food Bank, among other causes and charities. De Geus said he personally supports the Environmental Defense Fund and Human Rights Watch.

As he noted earlier in the morning during his SNUG keynote address, de Geus spoke about the hardiness of Moore’s Law, which is often proclaimed to be dead.

“For 15 years, analysts have predicted the next chip is impossible,” he said. He recalled that while he was a student 37 years ago, semiconductor experts generally agreed that the industry would never produce chips with dimensions smaller than 1 micron.

“Everything is a constraint problem,” he commented. “It’s always been like that.”

De Geus added, “I have been surprised by how quickly FinFET has caught on.” Later on Monday, Synopsys customers testified about how they have designed chips with FinFETs using Synopsys tools.

Asked about the implementation of fully-depleted silicon-on-insulator technology, de Geus said, “The jury is still out.” He added, “We are seeing design starts.”

The complexity of semiconductor design and manufacturing is increasing, de Geus acknowledged. “Of course it’s getting hard,” he said. The industry will go through the usual period of hand-wringing about technical challenges, according to de Geus. “Then, we nail it!”

Germanium Junctions for CMOS

Tuesday, November 25th, 2014

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By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

It is nearly certain that alternate channel materials with higher mobilities will be needed to replace silicon (Si) in future CMOS ICs. The best PMOS channels are made with germanium (Ge), while there are many possible elements and compounds in R&D competition to form the NMOS channel, in part because of difficulties in forming stable n-junctions in Ge. If the industry can do NMOS with Ge then the integration with Ge PMOS would be much simpler than having to try to integrate a compound semiconductor such as gallium-arsenide or indium-phosphide.

In considering Ge channels in future devices, we must anticipate that they will be part of finFET structures. Both bulk-silicon and silicon-on-insulator (SOI) wafers will be used to build 3D finFET device structures for future CMOS ICs. Ultra-Shallow Junctions (USJ) will be needed to make contacts to channels that are nanoscale.

John Borland is a renowned expert in junction-formation technology, and now a principle with Advanced Integrated Photonics. In a Junction Formation side-conference at SEMICON West 2014, Borland presented a summary of data that had first been shown by co-author Paul Konkola at the 2014 International Conference on Ion Implant Technology. Their work on “Implant Dopant Activation Comparison Between Silicon and Germanium” provides valuable insights into the intrinsic differences between the two semiconducting materials.

P-type implants into Ge showed an interesting self-activation (seen as a decrease in of p-type dopant after implant, especially for monomer B as the dose increases.  Using 4-Point-Probe (4PP) to measure sheet-resistance (Rs), the 5E14/cm2 B-implant Rs was 190Ω/□ and at higher implant dose of 5E15/cm2 Rs was 120Ω/□. B requires temperatures >600°C for full activation in PMOS Ge channels, and generally results in minimal dopant diffusion for USJ.

Figure 1 shows a comparison between P, As, and Sb implanted dopants at 1E16/cm2 into both a Si wafer and 1µm Ge-epilayer on Si after various anneals. The sheet-resistance values for all three n-type dopants were always lower in Ge than in Si over the 625-900°C RTA range by about 5x for P and 10x for As and Sb. Another experiment to study the results for co-implants of P+Sb, P+C, and P+F using a Si-cap layer did not show any enhanced n-type dopant activation.

Fig.1: Sheet-resistance (Rs) versus RTA temperatures for P, As, and Sb implanted dopants into Ge and Si. (Source: Borland)

Prof. Saraswat of Stanford University showed in 2005—at the spring Materials Research Society meeting— that n-type activation in Ge is inherently difficult. In that same year, Borland was the lead author of an article in Solid State Technology (July 2005, p.45) entited, “Meeting challenges for engineering the gate stack”, in which the authors advocated for using a Si-cap for P implant to enable high temperature n-type dopant activation with minimal diffusion for shallow n+ Ge junctions that can be used for Ge nMOS. Now, almost 10 year later, Borland is able to show that it can be done.

Ge Channel Integration and Metrology

Nano-scale Ge channels wrapped around 3D fin structures will be difficult to form before they can be implanted. However, whether formed in a Replacement Metal Gate (RMG) or epitaxial-etchback process, one commonality is that Ge channels will need abrupt junctions to fit into shrunk device structures. Also, as device structures have continued to shrink, the junction formation challenges between “planar” devices and 3D finFET have converged since the “2D” structures now have nano-scale 3D topography.

Adam Brand, senior director of transistor technology in the Advanced Product Technology Development group of Applied Materials, explained that, “Heated beamline implants are best when the priority is precise dose and energy control without lattice damage. Plasma doping (PLAD) is best when the priority is to deliver a high dose and conformal implant.”

Ehud Tzuri, director strategic marketing in the Process Diagnostic and Metrology group at Applied Materials reminds us that control of the Ge material quality, as specified by data on the count and lengths of stacking-faults and other crystalline dislocations, could be done by X-Ray Diffraction (XRD) or by some new disruptive technology. Cross-section Transmission Electron Microscopy (X-TEM) is the definitive technology for looking at nanoscale material quality, but since it is expensive and the sample must be destroyed it cannot be used for process control.

Figure 2 shows X-TEM results for 1 µm thick Ge epi-layers after 625°C and 900°C RTA. Due to the intrinsic lattice mis-match between Ge and Si there will always be some defects at the surface, as indicated by arrows in the figure. However, stacking faults are clearly seen in the lower RTA sample, while the 900°C anneal shows no stacking-faults and so should result in superior integrated device performance.

Fig. 2: Cross-section TEM of 1µm Ge-epi after 625°C and 900°C RTA, showing great reduction in stacking-faults with the higher annealing temperature. (Source: Borland)

Borland explains that the stacking-faults in Ge channels on finFETs would protrude to the surface, and so could not be mitigated by the use of the “Aspect-Ratio Trapping” (ART) integration trick that has been investigated by imec. However, the use of a silicon-oxide cap allows for the use of 900°C RTA which is hot enough to anneal out the defects in the crystal.

Brand provides an example of why integration challenges of Ge channels include subtle considerations, “The most important consideration for USJ in the FinFET era is to scale down the channel body width to improve electrostatics. Germanium has a higher semiconductor dielectric constant than silicon so a slightly lower body width will be needed to reach the same gate length due to the capacitive coupling.”

Junction formation in Ge channels will be one of the nanoscale materials engineering challenges for future CMOS finFETs. Either XRD or some other metrology technology will be needed for control. Integration will include the need to control the materials on the top and the bottom surfaces of channels to ensure that dopant atoms activate without diffusing away. The remaining challenge is to develop the shortest RTA process possible to minimize all diffusions.

— E. K.

RF and MEMS Technologies to Enable the IoT

Friday, October 24th, 2014

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By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

The “Internet of Things” (IoT) has been seen as the next major market that will demand high volumes of integrated circuits (IC). The IoT can be loosely defined as a network of small, low-cost, ubiquitous electronic devices where sensing data and communicating information occurs without direct human intervention. Each device would function as a “smart node” in the network by doing some low-level signal processing to filter signals from noise, and to reduce the bandwidth needed for node-to-node communications. The nodes will need to communicate up to some manner of a “cloud” for secure memory storage and to bounce actionable information down to humans.

Figure 1 shows a conservative forecast of the global IoT market that was recently published by IDC. IDC expects the worldwide IoT installed base to experience a compound annual growth rate (CAGR) of 17.5% from 2013 to 2020, starting from 9.1 billion smart nodes installed at the end of 2013 and growing to 28.1 billion units by 2020.

FIGURE 1: Forecast for global IoT applications revenue 2013-2020. Note that smart node “intelligent systems/devices” provide the foundation for this huge growing market. (Source: IDC)

Due to the anticipated elastic-demand for IoT devices that would come from cost reductions, the forecasts for the number of IoT nodes ranges to 50 billion or even 80 billion by the year 2020, as documented in the recent online Pete’s Post “Don’t Hack My Light Bulb, Bro”. The post also provides an excellent overview of recent discussions regarding the host of additional technology and business challenges associated with the enterprise infrastructure and security issues surrounding the integration of vast streams of new information.

As shown in Figure 1, the smart nodes form the foundation for the whole IoT. Consequently, the world will need low-cost high-volume manufacturing (HVM) technologies to create the different functionalites needed for smart nodes. Sensor- and logic-technologies to enable IoT smart nodes will generally evolve from existing IC applications, while R&D continues in Radio Frequency (RF) communications and in Micro Electro-Mechanical Systems (MEMS) energy harvesting.

RF Technology

IoT smart-nodes will use wireless RF technologies to communicate between themselves and with the “cloud.” In support of rapid growth in the 71-86 GHz RF “E-band” telecom backhaul segment—which transports data from cell sites in the peripheral radio access network (RAN) to the wireless packet core—Presto Engineering recently announced a non-captive production-scale testing service for 50µm-thin gallium arsenide wafers.

Silicon-On-Insulator (SOI) substrate supplier Soitec has excellent perspective on the global market for RF chips, since it’s High-Resistivity SOI (HR-SOI) wafers are widely used in commercial fabs. Bernard Aspar, senior vice president and general manager of the Communications and Power business unit of Soitec, explained to SemiMD in an exclusive interview why the market for RF chips is growing rapdily. RF front-end module unit sales are forecasted to increase at a CAGR of ~16% over the period of 2013-2017, while the area of silicon needing to be delivered could actually increase at ~30% CAGR. RF chips are increasing in average size due to the need to integrate multiple standards for wireless communications and multiple antenna switches. “The first components to be integrated in silicon were the antenna switches, moving from 70% on GaAs in 2010 to more than 80% on SOI in 2014,“ said Aspar.

Soitec claims that >80% of smart-phones today use an RF chip built on a wafer from the company, based on sales last year of >300k 200mm HR-SOI wafers. Due to anticipated future growth in RF demand, the company has plans to eventually move HR-SOI production to 300mm diameter wafers. Most of the anticipated demand will be for the company’s new variant of HR-SOI called eSI (“enhanced Signal Integrity”previously called “Trap Rich”) with a measured effective resistivity as high as 10 kOhm-cm for improved device performance.

This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) and purely capacitive crosstalk similar to quartz substrates. HR-SOI substrates in general demonstrate reduced harmonics compared with standard SOI substrates, and the eSI wafers reduce harmonics to the point that they can be considered as lossless. Soitec was recently given a Best Partnership Award by Sony Semiconductor for supplying RF substrates.

“We’re also adding value to the substrate because it allows for simplification of the fab processing,” said Aspar. The eSI wafers enable much higher linearity and isolation, helping designers to address some of the most advanced LTE requirements at competitive costs. These substrates also provides benefits for the integration of passives, such as the quality factor of spiral inductors or tunable MEMS capacitors.

Vibrational Energy Harvesting

IoT smart nodes will need electrical power to function, and batteries that must be replaced or charged by an external source create issues for ubiquitous always-on small devices. In principle the ambient energies of the environment can be harvested to power smart nodes, and to do so we may consider using thermoelectric, photovoltaic, and piezoelectric properties of thin-films. Thermoelectric and photovoltaic devices both require somewhat specialized ambients for efficient energy harvesting, while piezoelectric devices can extract energy from subtle vibrations almost anywhere in the world (Fig. 2).

FIGURE 2: Schematic cross-section of piezoelectric cantilever with end mass, depicted in connection to an energy-harvesting circuit. (Source: Science)

Researchers in the Energy Harvesting and Mechatronics Research Lab at Stony Brook University, New York, recently published an excellent overview of the potential for 1 W to 100 kW piezoelectronic energy harvesting in building, automobiles, and wearables electronics in the Journal of Intelligent Material Systems and Structures 24(11) 1405-1430. However, the largest forecasted growth in the IoT is for small devices that would consume µW to mW of active power.

For low-cost and low-power consumption, the logic chips for IoT smart nodes are expected to be made using a 65nm “trailing edge” fab process. For example, CAST Inc. has developed a 32-bit BA20 embedded processor core that can deliver 3.41 CoreMarks/MHz at a maximum frequency of 75 MHz. Using TSMC’s 65nm Low Power fab process, it occupies only 0.01 mm2 of silicon area while consuming 2 µW/MHz. Thus, at maximum speed the chip core would consume just 150µW.

MicroGen Systems, Inc. (MicroGen) is a privately held company developing thin piezoelectric energy harvesters, based on technology from Cornell University’s NanoScale Science and Technology Facility. Founded in 2007, MicroGen has headquarters and R&D in the Ithaca and Rochester, NY areas, and volume manufacturing with X-FAB in Itzehoe, Germany. Figure 3 shows one of the company’s ~100 mm2 area chips featuring an aluminum nitride (AlN) peizoelectric thin-film on a cantilever that produces alternating current (AC) electricity in response to external vibrations. Different cantilever designs allow for harvesting energy from either single-frequency or broadband vibrations. At resonance the AC power output is maximized, so it can be ~100 µW at 120Hz and 0.1g, or ~900 µW at 600Hz and 0.5g.

FIGURE 3: BOLT™-R0600 energy-harvesting chip without packaging. The green-silver trapezoidal area is a 25-100µm thick cantilever (with several thin-film layers including an AlN piezoelectric) attached to grey rectangular end mass (silicon). A fixed-frequency device, at resonance of ~600Hz it can produce ~900 µWatts of AC power. (Source: MicroGen Systems)

For any piezoelectric energy harvester there are basic materials properties that must be optimized, including the piezoelectric strain constant as well as the electromechanical coupling factor of the thin-film to the moving mass. Lead-zirconium-titanate (PZT) has been the most studied piezoelectric thin-film due to high strain constant and ability to couple to a substrate though the use of buffer layers.

S. H. Baek, et al. showed “Piezoelectric MEMS with Giant Piezo Actuation” in Science 18 November 2011, Vol 344 using lead-manganese-niobate with lead-titanate (PMN-PT) layers epitaxially grown on a strontium-titanate (STO) buffer layer over 4°-off-axis(001)Si. Figure 4 shows both the transverse piezoelectric coefficient (C/m2) and the energy-harvesting figure of merit (GPa) for this and other thin-films. Note that to acheive stable “giant” piezoelectric effects the PMN-PT layer had to be grown epitaxially with precise control over the STO grain orientation.

FIGURE 4: Transverse piezoelectric coefficient (C/m2) and the energy-harvesting figure of merit (GPa) for PMN-PT (“this work”) and other piezoelectric thin-films. (Source: Science)

—E.K.

Blog review August 4, 2014

Monday, August 4th, 2014

Innovation is alive and well in the semiconductor industry. That was a key takeaway from the strategic investor panel at the second annual Silicon Innovation Forum at SEMICON West, and one I can’t reinforce enough within the venture capital (VC) community. Eileen Tanghal of Applied Materials reports.

At SEMICON West this year in Thursday morning’s Yield Breakfast sponsored by Entegris, top executives from Qualcomm, GlobalFoundries, and Applied Materials discussed the challenges to achieving profitable fab yield for atomic-scale devices. In his blog, Ed Korzynski reports on what was discussed.

Phil Garrou blogs that Apple has acquired 24 tech companies in the last 18 months. Recently, Apple acquired LuxVue, a start-up focused on low power micro-LED displays. Although Apple has not disclosed any details of the acquisition, not even the purchase price, one can easily envision where micro LED displays could play a big part in Apples thrust into wearable electronics such as the i-watch, Phil says.

Adele Hars continued a report on the SOI papers at the VLSI Symposia in this Part 2 installment. The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry.

Vivek Bakshi created a EUV stir, blogging about IBM’s NXE3300B scanner, at the EUV Center of Excellence in Albany, which recently completed a “40W” EUV light source upgrade.  The upgrade resulted in better than projected performance with 44W of EUV light being measured at intermediate focus and confirmed in resist at the wafer level.

Scouting report for materials at end of the road: 2013 ITRS

Monday, May 12th, 2014

Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The IC fabrication industry is approaching the end of the road for device miniaturization, with both atomic and economic limits looming on the horizon. New materials are widely considered as key to the future of profitable innovation in ICs, so everyone from process engineers to business pundits needs to examine the Emerging Research Materials (ERM) chapter of the just published 2013 edition of the International Technology Roadmap for Semiconductors (ITRS).

The 2013 ITRS covers both near-term (2014-2020) and long-term (2020 onward) perspectives on what materials and processes would be desired to build ideal ICs (Fig. 1, Table ERM15). However, to properly understand the information in the current edition we need to consider the changes in the IC fab industry since 1992 when the first edition of the ITRS’s predecessor was published as the U.S. National Technology Roadmap for Semiconductors (NTRS).

Fig. 1

Twenty-two years ago, the industry had dozens of fabs working on next-generation technology, and with lithographic scaling dominating innovation there was broad consensus on gradual materials evolutions. Today, the industry has 3 logic fabs and about as many memory lines pushing processes to smaller geometries, and each fab may use significantly different revolutionary materials. The result today is that there is little consensus on direction for new materials, and at best we can quantify the relative benefits of choosing one or another of the many options available.

In fact, with just a few players left in the game, there is much to lose for any one player to disclose strategic plans such as the use of revolutionary materials. Mark Thirsk, managing partner with specialty materials analysts Linx Consulting, commented, “We built our business based on anonymizing and generalizing the world, and then predicting the future based on big categorical buckets. But now there are a very few number of people pushing the boundaries and we’re being asked to model specific fab processes such as those for Intel or TSMC.”

For all of the above reasons, the current ITRS might be better understood as a scouting report that quantifies the roughness of the terrain when our current roads end. Exotic materials such as graphene and indium-gallium-phosphide may be used as alternate materials for the Si channels in transistors, novel stacks of atomic-layers may be used as electrical contacts, and spintronics and single-electron devices may one day replace DRAM and Flash chips for solid-state memory chips. However,  “significant challenges” exist in integrating any of these new technologies into high-volume manufacturing.

In the near-term, Cu wires clad with various metal barriers are projected to provide the best overall performance for on-chip interconnects.  As stated in the 2013 Executive Summary, “Unfortunately no new breakthroughs are reported for interconnections since no viable materials with resistivity below copper exist. However, progress in manipulation of edgeless wrapped materials (e.g., carbon nanotubes, graphene combinations etc.) offer the promise of ‘ballistic conductors,’ which may emerge in the next decade.”

Specialty Materials Suppliers

Fig. 2

Figure 2 (Figure ERM5) shows the inherent complexity involved in the stages of developing a new chemical precursor for use in commercial IC production. The chapter summarizes the intrinsic difficulty of atomic-scale R&D for future chips as follows:

A critical ERM factor for improving emerging devices, interconnects, and package technologies is the ability to characterize and control embedded interface properties. As features approach the nanometer scale, fundamental thermodynamic stability considerations and fluctuations may limit the ability to fabricate materials with tight dimensional distributions and controlled useful material properties.

In addition to daunting technical issues with pre-cursor R&D, the business model for chemical suppliers is being strained by industry consolidation and by dimensional shrinks. Consolidation means that each fab has unique pre-cursor requirements, so there may be just one customer for a requested chemistry and no ability to get a return on the investment if the customer decides to use a different approach.

Shrinks down to atomic dimensions means that just milliliters instead of liters of chemistry may be needed. For example, atomic-layer deposition (ALD) precursor R&D requires expertise and investment in molecular- and chemical-engineering, and so significant sunk costs to create any specialty molecule in research quantities. “We’ll have an explosion of precursors required based on proprietary IP held by different companies,” reminds Thirsk. “The people who are being asked to develop the supply-chain of ever increasing specifications are simultaneously being squeezed on margin and volumes.”

For materials such as Co, Ru, La, and Ti-alloys to be used in fabs we need to develop more than just deposition and metrology steps. We will also likely require atomic-level processes for cleaning and etch/CMP, which can trigger a need for yet another custom material solution.

Established chemical suppliers—such as Air Liquide, Dow, DuPont, Linde, Praxair, and SAFC—run international businesses serving many industries. IC manufacturing is just a small portion of their businesses, and they can afford to simply walk-away from the industry if the ROI seems unattractive. “We’re finding more and more that, for example in wet cleaning chemistry, the top line of the market is flat,” cautioned Thirsk. “You can find some specialty chemistries that provide better profits, but the dynamics of the market are such that there’s reduced volume and reduced profitability. So where will the innovation come from?”

Alternate Channel Materials

With finFETs and SOI now both capable of running in fully-depleted mode, alternative materials to strained silicon are being extensively explored to provide higher MOSFET performance at reduced power. Examples include III-V semiconductors, Ge, graphene, carbon nanotubes, and other semiconductor nanowires (NW). To achieve complimentary MOS high performance, co-integration of different materials (i.e. III-V and Ge) on Si may be necessary. Significant materials issues such as defect reduction, interface chemistry, metal contact resistivity, and process integration must be addressed before such improvements can be achieved.

Nano-wire transistors

Top down fabricated nanowires (NW) are one-dimensional structures that can be derived from two-dimensional finFETs. Patterned and etched <5nm Si NW have been reported to have room temperature quantum oscillatory behavior with back-gate voltage with a peak mobility approaching ∼900 cm2/Vs. Despite extensive R&D, grown Si NW demonstrate no performance improvements over patterned-and-etched NW, and controlled growth in desired locations remains extraordinarily challenging. Overall, significant challenges must be overcome for NW to be integrated in high density, particularly when targeting laterally placed NW with surround gates and low resistance contacts.

—E.K.

Blog review May 5, 2014

Monday, May 5th, 2014

Jeremy Read of Applied Materials writes that while some consumer IoT applications will require semiconductors manufactured using cutting-edge technologies the vast majority of chips will be used in client-side applications. These chips, such as a sensor monitoring room temperature in a connected HVAC system, require processing capabilities that can be met using legacy process (90 and 45nm) technologies manufactured on 200mm wafers.

Ali Khakifirooz of Spansion notes that body biasing has been long considered as an effective and relatively easy way to compensate for some of the process variations. Not only does it lead to a tighter performance distribution and better yield, but also by mitigating the guardband requirements for process corners and temperature variation, it leads to better performance and faster design cycle.

Frank Feng of Mentor Graphics blogs that transistor and gate levels of library design are normally delivered fully vetted for reliability issues such as electrostatic discharge (ESD), latch-up, electrical overstress (EOS), and dielectric breakdown. However, when designers assemble transistors and gates into intellectual property (IP), blocks, or whole chip designs, they encounter a variety of reliability problems generated across interconnect layers or across device regions of PSUB and NWELL bodies.

Phil Garrou has not been predicting the end of the world, but rather the end of electronics as we know it, i.e.,relying on CMOS scaling. He blogs that it was with great anticipation that he perused the 2013 ITRS roadmap that was released a few weeks ago. He is happy to tell you they are facing the challenges head on although the ultimate solutions are, as we might expect, not yet crystal clear.

Pete Singer writes that the newly revamped International Technology Roadmap for Semiconductors was released in early April. It’s actually called the 2013 ITRS, which makes it seem already out of date, but that’s the way the numbering has always been. The latest ITRS highlights 3D power scaling, system level integration and a new chapter on big data.

Blog review April 14, 2014

Monday, April 14th, 2014

The increased performance and the rapid shift from traditional handsets to consumer computing device post a number of manufacturing and supply chain challenges for fabless chip makers. Dr. Roawen Chen of Qualcomm says the scale of the challenges also creates an “extreme stress” for the existing foundry/fabless model to defend its excellence in this dynamic landscape. In a keynote talk at The ConFab, titled “what’s on our mind?” Dr. Chen will deliberate on a number of headwinds and opportunities.

Jean-Eric Michallet, Hughes Metras and Perrine Batude of CEA-Leti describe how the research group has already demonstrated the successful stacking of Si CMOS on Si CMOS, achieving benchmark performance for both layers of transistors. The main process challenge is to develop a sufficiently low-temperature process for the top transistor layer to limit the impact on the lower transistor layers.

Phil Garrou continues his analysis of the IMAPS Device Packaging Conference with a review of the keynote by AMD’s Bryan Black, titled“Die Stacking and High Bandwidth Memory.” Black stated that “…while die stacking is catching on in FPGAs, Power Devices, and MEMs, there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” Garrou also reviews the newly announced STATSChipPAC FlexLine, which uses eWLB technology to dice and reconstitute incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size.

Karen Savala, president, SEMI Americas, blogs about the sustainable manufacturing imperative, noting that sustainability is increasingly considered a differentiating factor in global competitiveness relative to the technologies and products being provided. In conjunction with SEMICON West and INTERSOLAR North America, SEMI is organizing a four-day Sustainable Manufacturing Forum to share information about the latest technologies, products, and management approaches that promote sustainable manufacturing.

Blog review March 10, 2014

Monday, March 10th, 2014

Pete Singer is pleased to announce that IBM’s Dr. Gary Patton will provide the keynote talk at The ConFab on Tuesday, June 24th. Gary is Vice President of IBM’s Semiconductor Research and Development Center in East Fishkill, New York, and has responsibility for IBM’s semiconductor R&D roadmap, operations, and technology development alliances.

Nag Patibandla of Applied Materials describes a half-day workshop at Lawrence Berkeley Lab that assembled experts to discuss challenges and identify opportunities for collaboration in semiconductor manufacturing including EUV lithography, advanced etch techniques, compound semiconductors, energy storage and materials engineering.

Adele Hars of Advanced Substrate News reports on a presentation by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during SEMI’s recent ISS Europe Symposium. FD-SOI is significantly cheaper, outdoes planar bulk and matches bulk FinFET in the performance/power ratio, and keeps the industry on track with Moore’s Law, she writes.

Phil Garrou reports on the RTI- Architectures for Semiconductor Integration & Packaging (ASIP) conference, which is focused on commercial 3DIC technology. Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC. Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing. In addition Tezzaron’s Robert Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly.

Vivek Bakshi, EUV Litho, Inc., blogs that most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM).

On March 2, 2014 SIA announced that worldwide sales of semiconductors reached $26.3 billion for the month of January 2014, an increase of 8.8% from January 2013 when sales were $24.2 billion. After adding in semiconductor sales from excluded companies such as Apple and Sandisk, that total is even higher, marking the industry’s highest-ever January sales total and the largest year-to-year increase in nearly three years. These results are in-line with the Semico IPI index which has been projecting strong semiconductor revenue growth for the 1st and 2nd quarters of 2014.

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