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Why SOI is the Future Technology of Semiconductors

Monday, December 23rd, 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D, blogs that this is the “one learning” we can take away from IEDM 2013.

Let’s start with the short answer – because:

A. SOI is cheaper to fabricate than FinFet with comparable performance, and it is easier and cheaper to build FinFET on SOI which then provides better performance.

B. SOI is the natural technology for monolithic 3D IC for all overlaying transistor layers, and monolithic 3D is the most effective path to stay on Moore’s Law.

C. SOI, or better ‘XOI’, is the most efficient path for most of the new concepts such as alternate materials for transistor construction and other structures like nano-wires.

Let’s now elaborate and discuss each of these points.

Starting with A: The following chart from Globalfoundries was presented on June 2013 at the FD-SOI Workshop, Kyoto, Japan. The chart illustrates that the best cost per transistor is the classic polysilcon gate at the 28nm node, that FD-SOI is cheaper than bulk with comparable performance at 28nm HKMG, and that FD-SOI at 20nm is cheaper than 14nm FinFet at the same performance level.

Similar information was presented by IBS (International Business Strategies), in Oct 2013 at the SOI Summit Shanghai, China.

And before that D. Handel Jones of IBS in a 2012 White Paper presented the following table.

Clearly the SOI substrate costs much more than the bulk substrate ($500 vs. $120), but the improvement in performance and the reduction of cost associated with FD processing neutralizes the substrate costs and makes the SOI route far more attractive. The following charts were included in a Comparison Study of FinFET on SOI vs. Bulk done by IBM, IMEC, SOITEC and Freescale:

For the second point “B, SOI is the natural technology for monolithic 3D”, in monolithic 3D the upper semiconductor layer is very thin (<100nm) and is placed over oxide to isolate it from the interconnection structure underneath – hence SOI.

In this month’s IEDM 2013 two papers (9.3, 29.6) presented exciting demonstrations of monolithic 3D IC. It is interesting to note that Prof. Emeritus Chenming Hu of Berkeley (past TSMC CTO) who is now very famous due to his pioneering work on FinFETs, is a co-author of these two pioneering works on monolithic 3D IC. The following figures illustrate the natural SOI structure of the upper transistor layers:

In his invited paper at IEDM 2013 Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is most effective path for the semiconductor future: ” Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” As illustrated by his Fig. 17 below.

Clearly dimensional scaling is not providing transistor cost reduction beyond the 28 nm node, and the large fabless companies—Qualcomm, Broadcom, Nvidia, and AMD—recently reported this fact once again. The industry is trying to accommodate this new reality, while still rushing to develop and adopt more advanced nodes at escalating costs and complexity. And it is encouraging to see that Qualcomm are actually ‘putting their money where their mouth is” as CEA Leti just recently announced an agreement with Qualcomm to Evaluate Leti’s Non-TSV 3D Process.

Thus it was natural for Leti to include in their presentation at their promotional event in conjunction with this year’s IEDM 2013, slides advocating monolithic 3D as an alternative to dimensional scaling.

Leti’s presentation goes even further. One can see that in the following Leti slide, monolithic 3D is positioned as a far better path to keep the industry momentum and provides the cost reduction that dimensional scaling does not provide any more. Monolithic 3D also does this with far less costly fab infrastructure and process R&D. As the slide sums up: “1 node gain without scaling,” or, as others may say, the new form of scaling is ‘scaling up’.

In respect to point C regarding integration of other materials, we must admit that this is still area of advanced research and contains many unknowns. What we do know is that the silicon related worldwide infrastructure is unparalleled and will not be easily replaced. Accordingly, future technologies would have the best chance by first integrating with the existing silicon infrastructure, which in many cases is easier to do with SOI. To illustrate this we can refer to some other work presented in the IEDM 2013. Such as Stanford work (19.7) titled: “Monolithic Three-Dimensional Integration of Carbon Nanotube FET Complementary Logic Circuits” illustrated in the following chart:

Other work is about integrating photonics with CMOS which was covered in a recent article titled Is There Light At The End Of Moore’s Tunnel? and includes the following illustrations:

Clearly SOI and monolithic 3D integration have a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS Scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains. These technologies were not part of the main stream semiconductor past; accordingly it is a golden opportunity to catch-up with these technologies now. Please mark your calendar for this opportunity to contribute and learn about SOI and monolithic 3D technology, as these technologies are well positioned to keep the semiconductor industry’s future momentum.

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