Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘Silicon’

Next Page »

Mechanistic Modeling of Silicon ALE for FinFETs

Tuesday, April 25th, 2017

thumbnail

With billions of device features on the most advanced silicon CMOS ICs, the industry needs to be able to precisely etch atomic-scale features without over-etching. Atomic layer etching (ALE), can ideally remove uniform layers of material with consistent thickness in each cycle, and can improve uniformity, reduce damage, increase selectivity, and minimize aspect ratio dependent etching (ARDE) rates. Researchers Chad Huard et al. from the University of Michigan and Lam Research recently published “Atomic layer etching of 3D structures in silicon: Self-limiting and nonideal reactions” in the latest issue of the Journal of Vacuum Science & Technology A (http://dx.doi.org/10.1116/1.4979661). Proper control of sub-cycle pulse times is the key to preventing gas mixing that can degrade the fidelity of ALE.

The authors modeled non-idealities in the ALE of silicon using Ar/Cl2 plasmas:  passivation using Ar/Cl2 plasma resulting in a single layer of SiClx, followed by Ar-ion bombardment to remove the single passivated layer. Un-surprisingly, they found that ideal ALE requires self-limited processes during both steps. Decoupling passivation and etching allows for several advantages over continuous etching, including more ideal etch profiles, high selectivity, and low plasma-induced damage. Any continuous etching —when either or both process steps are not fully self-limited— can cause ARDE and surface roughness.

The gate etch in a finFET process requires that 3D corners be accurately resolved to maintain a uniform gate length along the height of the fin. In so doing, the roughness of the etch surface and the exact etch depth per cycle (EPC) are not as critical as the ability of ALE to be resistant to ARDE. The Figure shows that the geometry modeled was a periodic array of vertical crystalline silicon fins, each 10nm wide and 42nm high, set at a pitch of 42 nm. For continuous etching (a-c), simulations used a 70/30 mix of Ar/Cl gas and RF bias of 30V. Just before the etch-front touches the underlying SiO2 (a), the profile has tapered away from the trench sidewalls and the etch-front shows some micro-trenching produced by ions (or hot neutrals) specularly reflected from the tapered sidewalls. After a 25% over-etch (b), a significant amount of Si remains in the corners and on the sides of the fins. Even after an over-etch of 100% (c), Si still remains in the corners.

FIGURE CAPTION: Simulated profiles resulting from etching finFET gates with (a)–(c) a continuous etching process, or (d)–(f) an optimized ALE process. Time increases from left to right, and images represent equal over-etch (as a percentage of the time required to expose the bottom SiO2) not equal etch times. Times listed for the ALE process in (d)–(f) represent plasma-on, ignoring any purge or dwell times. (Source: J. Vac. Sci. Technol. A, Vol. 35, No. 3, May/Jun 2017)

In comparison, the ALE process (d-f) shows that after 25% over-etch (e) the bottom SiO2 surface would be almost completely cleared with minimal corner residues, and continuing to 100% over-etch results in little change to the profile. The ALE process times shown here do not include the gas purge and fill times between plasma pulses; to clear the feature using ALE required 200 pulses and assuming 5 seconds of purge time between each pulse results in a total process time of 15–20 min to clear the feature. This is a significant increase in total process time over the continuous etch (2 min).

One conclusion of this ALE modeling is that even small deviations from perfectly self-limited reactions significantly compromise the ideality of the ALE process. For example, having as little as 10 ppm Cl2 residual gas in the chamber during the ion bombardment phase produced non-idealities in the ALE. Introducing any source of continuous chemical etching into the ALE process leads to the onset of ARDE and roughening of the etch front. These trends have significant implications for both the design of specialized ALE chambers, and also for the use of ALE to control uniformity.

—E.K.

Silicon Photonics Technology Developments

Thursday, April 6th, 2017

thumbnail

By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.

—E.K.

Picosun and Hitachi MECRALD Process

Friday, February 24th, 2017

thumbnail

By Ed Korczynski, Sr. Technical Editor

A new microwave electron cyclotron resonance (MECR) atomic layer deposition (ALD) process technology has been co-developed by Hitachi High-Technologies Corporation and Picosun Oy to provide commercial semiconductor IC fabs with the ability to form dielectric films at lower temperatures. Silicon oxide and silicon nitride, aluminum oxide and aluminum nitride films have been deposited in the temperature range of 150-200 degrees C in the new 300-mm single-wafer plasma-enhanced ALD (PEALD) processing chamber.

With the device features within both logic and memory chips having been scaled to atomic dimensions, ALD technology has been increasingly enabling cost-effective high volume manufacturing (HVM) of the most advanced ICs. While the deposition rate will always be an important process parameter for HVM, the quality of the material deposited is far more important in ALD. The MECR plasma source provides a means of tunable energy to alter the reactivity of ALD precursors, thereby allowing for new degrees of freedom in controlling final film properties.

The Figure shows the MECRALD chamber— Hitachi High-Tech’s ECR plasma generator is integrated with Picosun’s digitally controlled ALD system—from an online video (https://youtu.be/SBmZxph-EE0) describing the process sequence:

1.  first precursor gas/vapor flows from a circumferential ring near the wafer chuck,

2.  first vacuum purge,

3.  second precursor gas/vapor is ionized as it flows down through the ECR zone above the circumferential ring, and

4.  second vacuum purge to complete one ALD cycle (which may be repeated).

Cross-sectional schematic of a new Microwave Electron Cyclotron Resonance (MECR) plasma source from Hitachi High-Technologies connected to a single-wafer Atomic Layer Deposition (ALD) processing chamber from Picosun. (Source: Picosun)

The development team claims that MECRALD films are superior to other PEALD films in terms of higher density, lower contamination of carbon and oxygen (in non-oxides), and also show excellent step-coverage as would be expected from a surface-driven ALD process. The relatively density of these films has been confirmed by lower wet etch rates. The single-wafer process non-uniformity on 300mm wafers is claimed at ~1% (1 sigma). The team is now exploring processes and precursors to be able to deposit additional films such as titanium nitride (TiN), tantalum nitride (TaN), and hafnium oxide (HfO). In an interview with Solid State Technology, a spokesperson from Hitachi High-Technologies explained that, “We are now at the development stage, and the final specifications mainly depend on future achievements.”

The MECR source has been used in Hitachi High-Tech’s plasma chamber for IC conductor etch for many years, and is able to generate a stable high-density plasma at very low pressure (< 0.1 Pa). MECR plasmas provide wide process windows through accurate plasma parameter management, such as plasma distribution or plasma position control. The same plasma technology is also used to control ions and radicals in the company’s dry cleaning chambers.

“I’m really impressed by the continuous development of ALD technology, after more than 40 years since the invention,” commented Dr. Tuomo Suntola, and the famous inventor and patentor of the Atomic Layer Deposition method in Finland in 1974, and member of the Picosun board of directors. “Now combining Hitachi and Picosun technologies means (there is) again a major breakthrough in advanced semiconductor manufacturing.”

MECRALD chambers can be clustered on a Picosun platform that features a Brooks robot handler. This technology is still under development, so it’s too soon to discuss manufacturing parameters such as tool cost and wafer throughput.

—E.K.

Photonics in Silicon R&D Toward Tb/s

Tuesday, January 3rd, 2017

thumbnail

By Ed Korczynski, Sr. Technical Editor

The client:server computing paradigm colloquially referred to as the “Cloud” results in a need for extremely efficient Cloud server hardware, and from first principles the world can save a lot of energy resources if servers run on photonics instead of electronics. Though the potential for cost-savings is well known, the challenge of developing cost-effective integrated photonics solutions remains. Today, discrete compound-semiconductor chips function as transmitters, multiplexers (MUX), and receivers of photons, while many global organizations pursue the vision of lower-cost integrated silicon (Si) photonics circuits.

Work on photonics chips—using light as logic elements in an integrated circuit—built in silicon (Si) has accelerated recently with announcements of new collaborative research and development (R&D) projects. Leti, an institute of CEA Tech, announced the launch of a European Commission Horizon 2020 “COSMICC” project to enable mass commercialization of Si-photonics-based transceivers to meet future data-transmission requirements in data centers and super computing systems.

The Leti-coordinated COSMICC project will combine CMOS electronics and Si-photonics with innovative fiber-attachment techniques to achieve 1 Tb/s data rates. These scalable solutions will provide performance improvement an order of magnitude better than current VCSELs transceivers, and the COSMICC-developed technology will address future data-transmission needs with a target cost per bit that traditional wavelength-division multiplexing (WDM) transceivers cannot meet. The project’s 11 partners from five countries are focusing on developing mid-board optical transceivers with data rates up to 2.4 Tb/s with 200 Gb/s per fiber using 12 fibers. The devices will consume less than 2 pJ/bit. and cost approximately 0.2 Euros/Gb/s.

Figure 1: Schematic of COSMICC on-board optical transceiver at 2.4 Tb/s using 50 Gbps/wavelength, 4 CWDM wavelengths per fiber, 12 fibers for transmission and 12 fibers for reception. (Source: Leti)

A first improvement will be the introduction of a silicon-nitride (SiN) layer that will allow development of temperature-insensitive MUX/DEMUX devices for coarse WDM operation, and will serve as an intermediate wave-guiding layer for optical input/output. The partners will also evaluate capacitive modulators, slow-wave depletion modulators with 1D periodicity, and more advanced approaches. These include GeSi electro-absorption modulators with tunable Si composition and photonic crystal electro-refraction modulators to make micrometer-scale devices. In addition, a hybrid III-V on Si laser will be integrated in the SOI/SiN platform in the more advanced transmitter circuits.

Meanwhile in the United States, Coventor, Inc. is collaborating with the Massachusetts Institute of Technology (MIT) on photonics modeling. MIT is a key player in the AIM Photonics program, a federally funded, public-private partnership established to advance domestic capabilities in integrated photonic technology and strengthen high-tech U.S.-based manufacturing. Coventor will provide its SEMulator3D process modeling platform to model the effect of process variation in the development of photonic integrated components.

“Coventor’s technical expertise in predicting the manufacturability of advanced technologies is outstanding. Our joint collaboration with Coventor will help us develop new design methods for achieving high yield and high performance in integrated photonic applications,” said Professor Duane Boning of MIT. Boning is an expert at modeling non-linear effects in processing, many years after working on the semiconductor industry’s reference model for the control of chemical-mechanical planarization (CMP) processing.

—E.K.

Silicon as Disruptive Platform for IoT Applications

Monday, August 29th, 2016

thumbnail

By Ed Korczynski, Sr. Technical Editor

Marie Semeria, chief executive officer of CEA-Leti (http://www.leti.fr/en), sat down with SemiMD during SEMICON West to discuss how the French R&D and pilot manufacturing campus—located at the foot of the beautiful French alps near Grenoble—is expanding the scope of it’s activities to develop systems solutions for the Internet-of-Things (IoT). Part-1 on hardware/software co-development was published last month.

Korczynski: Regarding ‘IoT’ applications, we expect that chips must be very low cost to be successful, and at the same time the ultimately winning solutions will be those that combine the best functionalities from different technology spaces each in a ‘sweet spot’ of cost to performance. It seems that being able to do it on SOI wafers could produce the right volumes.

Semeria: Yes. It could be enough.

Korczynski: Do you have any feel in advance for how much area of silicon is needed? Some small ADC, an 8-bit micro-controller, and RF components may be done in different processes and then integrated. Is it possible that the total area of silicon needed could be less than a square millimeter?

Semeria: Yes.

Korczynski: Well, if they are that small then we have to remember how many units we’d get from just a single wafer, and there are 24 wafers in a batch…

Semeria: One batch can be enough for one market, depending upon the application.

Korczynski: If this is the case, then even though the concept of purely-additive roll-to-roll processes are attractive, oddly they may be too efficient and produce more units than the world can absorb. If we can do all that we need to do with established silicon wafer fab technology creating ICs smaller than a square millimeter then it will be very cost-effective.

Semeria: Leti’s strategy is to keep the performance of solid-state devices, so not to go to organic electronics. Use silicon as the differentiator to lower the cost, add more functions, and then miniaturize all that can be miniaturized. In this way we are achieving integration of MEMS with small electronics in arrays as small as one millimeter square. When you deal with such small die you can put them inside of flexible materials, inside of a t-shirt and it’s no problem. So that’s our strategy to keep small silicon and put it in clothes, in shoes, in windows, in glasses, and all sorts of flexible materials. When you are thinning substrates for bonding, then the thinned silicon is very flexible.

Korczynski: In 1999 I worked for one of the first companies selling through-silicon via technology, and it was all about backside thinning so I’ve played with flexible wafers.

Semeria: So you know what I mean.

Korczynski: Around 50 microns and below as long as you etch away any grinding defects from the backside it is very strong and very flexible (Fig. 1). At 50 microns the chip is still thick enough to be easily picked-and-placed, but it’s flexible. Below 10 microns the wafer is difficult to handle.

FIGURE 1: 50 micron thin silicon wafers can be strong and very flexible. (Source: Virginia Semiconductor)

Semeria: To maintain the advantage of cost for different applications spaces, we are developing the ‘chiplet’ approach which means a network of chips. It starts with a digital platform, then you add an active interposer to connect different dice. For example you could have 28nm-node on the bottom and a 14nm-node chip on top for some specific function. Then you can put embedded memory and RF connected through the interposer, and it’s the approach that we promote for the first generation of multi-functional integration on digital. Very flexible, cost-effective.

Korczynski: This is using some sort of bus to move information?

Semeria: Yes, this will be an electronic bus for the first generation, as we recently announced. Then a photonics interposer could be used for higher-speed data rate in a future generation. We have a full roadmap with different types of integration schemes. So it’s a way to combine all with silicon. Everything is intended to be integrated into existing 300mm silicon facilities. Some weeks ago we presented the first results showing silicon quantum bits built on 300mm substrates, and fully compatible with CMOS processing. So it’s the way we are going, taking a very disruptive approach using the foundation of proven 300mm silicon processing.

Korczynski: Interesting.

Semeria: For example, regarding driving assistance applications we have to consider fusion integration of different sensors, and complete coverage of the environment with low power-consumption. For computing capacity we developed a completely disruptive approach, very different from Intel and very different from nVidia which use consumer products as the basis for automotive application products. Specifically for automotive we developed a new probabilistic methodology to avoid all of the calculations based on floating-point. In this way we can divide the computing needs of the device by 100, so it’s another example of developing just the right device for the right application adapted for the right environment. So the approach is very different in development for IoT instead of mainstream CMOS.

Korczynski: For automotive there’s such a requirement for reliability, with billions of dollars at stake in product recalls and potential lawsuits, the auto industry is very risk-averse for very good reasons. So historically they’ve always used trailing-edge nodes, and if you want to supply to them you have to commit to 10 or maybe 20 years of manufacturing, and yet we still want to add in advance functionalities. The impression I’ve gotten is that the 28nm FD-SOI platform is fairly ideal here.

Semeria: FD-SOI is very reliable and very efficient. That’s why when we showed our demonstrator at the recent DAC it’s based on the STMicroelectronics micro-controller. It’s very reliable and adaptable for automotive applications.

Korczynski: Is it at 28nm?

Semeria: No, about 40nm now. The latest generation is not needed, because we changed the algorithms so we didn’t need so much capacity in computing. In IoT there is space to use 40nm or 32nm down to 28nm. It’s a great space to use ‘old technologies’ and optimize them with the right algorithms, the right signal-processing, and the right security. So it’s very exciting for Leti because we have all of the key competencies to be able to handle the IoT challenge, and there is a great ability to make various integration schemes depending upon the application. There is a very large space to demonstrate, and to develop new materials.

Korczynski: Does this relate to some recent work I’ve seen from Leti with micro-cantilevers?

Semeria: Yes, this is the work we are doing with CalTech on micro-resonators (Fig. 2).

FIGURE 2: MEMS/NEMS silicon cantilever resonator capable of detecting individual adhered molecules, for integration with digital CMOS in a complete IoT sensing system. (Source: Leti)

Korczynski: Thank you very much for taking the time to discuss these important trends.

Semeria: It is a pleasure.

—E.K.

79 GHz CMOS RADAR Chips for Cars from Imec and Infineon

Tuesday, May 24th, 2016

thumbnail

By Ed Korczynski, Sr. Technical Editor

As unveiled at the annual Imec Technology Forum in Brussels (itf2016.be), Infineon Technologies AG (infineon.com) and imec (imec.be) are working on highly integrated CMOS-based 79 GHz sensor chips for automotive radar applications. Imec provides expertise in high-frequency system, circuit, and antenna design for radar applications, complementing Infineon’s knowledge from the many learnings that go along with holding the world’s top market share in commercial radar sensor chips. Infineon and imec expect functional CMOS sensor chip samples in the third quarter of 2016. A complete radar system demonstrator is scheduled for the beginning of 2017.

Whether or not fully automated cars and trucks will be traveling on roads soon, today’s drivers want more sensors to be able to safely avoid accidents in conditions of limited visibility. Typically, there are up to three radar systems in today’s vehicle equipped with driver assistance functions. In a future with fully automated cars, up to ten radar systems and ten more sensor systems using cameras or lidar (https://en.wikipedia.org/wiki/Lidar) could be needed. Short-range radar (SRR) would look for side objects, medium-range radar (MRR) would scan widely for objects up to 50m in front and in back, and long-range radar (LRR) would focus up to 250m in front and in back for high-speed collision avoidance.

“Infineon enables the radar-based safety cocoon of the partly and fully automated car,” said Ralf Bornefeld, Vice President & General Manager, Sense & Control, Infineon Technologies AG. “In the future, we will manufacture radar sensor chips as a single-chip solution in a classic CMOS process for applications like automated parking. Infineon will continue to set industry standards in radar technology and quality.”

The Figure shows the evolution of radar technology over the last decades, leading to the current miniaturization using solid-state silicon CMOS. Key to the successful development of this 79 GHz demonstrator was choosing to use 28 nm CMOS technology. Imec has been refining this technology as shown at ISSCC (isscc.org) for many years, first showing a 28nm transmitter chip in 2013, then showing a 28nm transmit and receive (a.k.a. “transceiver”) chip in 2014, and finally showing a single-chip with a transceiver and analog-digital converters (ADC) and phase-lock loops (PLL) and digital components in 2015. Long-term supply of eventual commercial chips should be ensured by using 28nm technology, which is known as a “long lived” node.

“We are excited to work with Infineon as a valuable partner in our R&D program on advanced CMOS-based 77 GHz and 79 GHz radar technology,” stated Wim Van Thillo, program director perceptive systems at imec. “Compared to the mainstream 24 GHz band, the 77 GHz and 79 GHz bands enable a finer range, Doppler and angular resolution. With these advantages, we aim to realize radar prototypes with integrated multiple-input, multiple-output (MIMO) antennas that not only detect large objects, but also pedestrians and bikers and thus contribute to a safer environment for all.”

Since the aesthetics are always important for buyers, automobile companies have been challenged to integrate all of the desired sensors into vehicles in an invisible manner. “The designers hate what they call the ‘warts’ on car bumpers that are the small holes needed for the ultrasonic sensors currently used,” explained Van Thillo in a press conference during ITF2016.

In an ITF2016 presentation, CEO Reinhard Ploss, discussed how Infineon works with industrial partners to create competitive commercial products. “When we first developed RADAR, there was a collaboration between the Tier-1 car companies and ourselves,” explained Ploss. “The key lies in the algorithms needed to process the data, since the raw data stream is essentially useless. The next generation of differentiation for semiconductors will be how to integrate algorithms. In effect, how do you translate ‘pixels’ into ‘optics’ without an expensive microprocessor?”

Evolution of radar technology over time has reached the miniaturization of 79 GHz using 28nm silicon CMOS technology. Imec is now also working on 140 GHz radar chips. (Source: imec)

—E.K.

New Materials: A Paradox of the Unknown

Thursday, March 17th, 2016

thumbnail

By Pete Singer, Editor-in-Chief

The semiconductor industry has slowly been implementing a growing array of new materials in an effort to boost speed and performance, reduce power consumption and reduce leakage. From the 1960s through the 1990s, only a handful of materials were used, most notably silicon, silicon oxide, silicon nitride and aluminum. Soon, by 2020, more than 40 different materials will be in high-volume production, including more exotic materials such as hafnium, ruthenium, zirconium, strontium, complex III-Vs (such as InGaAs), cobalt and SiC (Figure 1).

Figure 1

At the same time, semiconductor manufacturing processes are executed at the atomic level. Atomic layer deposition, atomic layer etching and atomic layer epitaxy are now common.

One of the challenges with new materials and atomic-level processing is that new and unexpected reactions can occur due to the trace impurities in the gases used during production. These impurities may be organic materials or trace levels of oxygen, nitrogen or other elements.

Jean-Charles Cigal

Jean-Charles Cigal, market development manager at Linde in Pullach, Germany, said a growing concern is that gases that have the same specification as before suddenly are not working the same way. “There are a lot of impurities that weren’t a problem before. They are now reacting because you have new materials on the wafer,” he said. “Process engineers don’t know what to look at in terms of impurities. That’s the paradox of the unknown.”

To help customers avoid such problems, gas supplier Linde has implemented tools commonly used in the semiconductor industry, including statistical process control (SPC), statistical quality control (SQC) and a lab information management system (LIMS). “The advantage of having this statistical process strategy is the ability to more rapidly correct any quality issue,” Cigal said.

A “fingerprinting” strategy also comes into play. “We’re using broad spectrum analyzers to get a lot of data and check everything possible. We want to do detection and correction of any quality issue before it reaches the fab,” Cigal said. If an unexpected quality issue is later identified at the fab, Linde can step in with forensic analysis using a database of information.

It is not cost-effective to simply specify higher and higher levels of purity. Instead, Cigal says targeted specifications are now the norm. “In the past, people were asking for the highest purity. Give me a 7.0 silane. Now they are saying OK, give me a silane with 5.0 but I don’t want this organic material,” he said. Linde’s HiQ portfolio offers more than 100 different pure gases such as HiQ Nitrogen 5.0 and HiQ Argon 6.0. Purity is commonly expressed as a two digit number. For example, Helium with a purity of 99.9996% would be described as HiQ Helium 5.6 with the 5 representing the number of nines, while the 6 represents the first digit following the nines.

“What we want ultimately is to get a full picture of what is inside (the gas) and to make the customer aware,” Cigal said. “We don’t know everything about the customers’ processes, but Linde is building large database that will help electronics manufacturers identify what impurities might react in certain processes.”

Customers are now asking for specifications just under the detection limits. We are continuously acquiring analytical tools that will help them to better understand the composition of their materials, which ultimately helps to improve their manufacturing yield.

The semiconductor industry demands very high-purity materials and yet electronics materials suppliers often receive raw materials of very low quality. To ensure that customers get the high-quality materials they require, Linde takes on the responsibility of being the quality gate keeper and controls the whole supply chain – from the source, through purification, and transportation.

Editor’s Note: Jean-Charles Cigal is currently Market Development Manager at Linde Electronics. In his role, Jean-Charles supports electronics customers and equipment manufacturers to achieve their roadmap with the introduction of new processes and materials. He joined Linde as principal technologist in 2009, where he was technology consultant for the semiconductor and the photovoltaic industry.  Prior to joining the Linde Group, Jean-Charles worked several years as senior process engineer in the semiconductor industry. He owns a M.Sc. in Applied Physics from Pierre et Marie Curie University, Paris, France, and a PhD in Applied Physics from Eindhoven University of Technology, the Netherlands.

TSMC Readies 7nm Chip Ecosystem, Infrastructure for 2017

Wednesday, March 16th, 2016

thumbnail

By Jeff Dorsch, Contributing Editor

Taiwan Semiconductor Manufacturing Company came to Silicon Valley on Tuesday for a day of presentations on its latest chip technology. The TSMC Technology Symposium for North America drew more than 1,000 attendees at the San Jose Convention Center.

The world’s largest silicon foundry led off the day with a pair of announcements: ARM Holdings and TSMC said they would collaborate on 7-nanometer FinFET process technology for ultra-low-power high-performance computing (HPC) system-on-a-chip devices, building on their previous experience with 16nm and 10nm FinFET process technology, while MediaTek and TSMC extended their partnership to develop Internet of Things and wearable electronics products, using the IC design house’s MT2523 chipset for fitness smartwatches, introduced in January and fabricated with TSMC’s 55nm ULP process.

TSMC’s work with ARM on the 16nm and 10nm nodes employed ARM’s Artisan foundation physical intellectual property, as will their 7nm efforts.

On Tuesday afternoon, the hundreds of attendees heard first from BJ Woo, TSMC’s vice president of business development, on the company’s advanced technology, including its moves toward supporting radio-frequency IC (RFIC) designs for smartphone chips and other areas of wireless communications.

“Cellular RF and WLAN are RF technology drivers,” she said. Looking toward 4G LTE Carrier Aggregation, TSMC began offering its 28HPC RF process to customers in late 2015 and will roll out the 28HPC+ RF process in the second quarter of this year, Woo added.

TSMC has won 75 percent of the business for RFIC applications, she asserted.

The foundry will start making 10nm FinFET chips for flagship smartphones and “phablets” this year, with 7nm FinFET devices for those products in 2017, according to Woo.

The business development executive also touted the company’s “mature 28-nanometer processes,” the 28HPC and 28HPC+, saying they are “rising in both volume and customer tape-outs.”

TSMC has been shipping automotive chips meeting industry standards since 2014, Woo noted, primarily for advanced driver assistance systems (ADAS) and infotainment electronics. The foundry is now working on vehicle control technology, employing microcontrollers.

The company’s 16FF+ process has been used in 50 customer tape-outs, Woo said. “Many have achieved first-silicon success,” she added. TSMC is putting its 16FFC process into volume production during this quarter.

“Automotive will be the [semiconductor] industry focus,” Woo predicted.

She also spoke about the company’s MD2 local interconnect technology, its 1D back-end-of-line process, and its spacer BEOL process.

Regarding 7nm chips, Woo said the company will offer two “tracks” of such chips, for high-performance computing and mobile applications. “Both will be available at the same time,” she said.

Most of the semiconductor production equipment being used for fabrication of 10nm chip will also be used for 7nm manufacturing, according to Woo. Those 7nm chips will be 10 to 15 percent faster than 10nm chips, while reducing power consumption by 35 to 40 percent, she said.

Risk production of 7nm chips will begin one year from now, in March of 2017, she said.

Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division, reported on development of electronic design automation (EDA) products for the 16nm node and beyond.

“Low-power solutions are ready,” he said of the foundry’s 16FFC process. IP is available to use with 16FFC for automotive, IoT, HPC, and mobile computing applications, he noted.

Lee reviewed what the company’s EDA partners – Mentor Graphics, Synopsys, Cadence Design Systems, ANSYS, and ATopTech – have available for 10nm chip design and verification.

Design and manufacturing of 7nm chips will involve cut-metal handling and multiple patterning, according to Lee. “We’ve used this technology on 16 nanometer and previous generations,” he said of cut-metal handling.

TSMC will support multiple SPICE simulators, having developed hybrid-format netlist support, Lee said. Pre-silicon design kits for 7nm chips will be available in the third quarter of 2016, he added.

The TSMC9000 Program for automotive/IoT products will be “up and running” in Q3 of this year, providing “automotive-grade qualification requirements in planning,” he said.

Lee also spoke about the foundry’s offerings in 3D chips, featuring “full integration of packaging and IC design” with TSMC’s InFO technology. The HBM2 CoWoS design kit will be out in the second quarter of 2016, he said. “We’re very excited about that,” Lee added.

George Liu, senior director of TSMC’s Sensor & Display Business Development, said, “The Internet of Things will drive the next semiconductor growth.” When it comes to the IoT and the Internet of Everything, “forecasts are all over the map,” he noted.

Taking diversification as his theme, Liu said TSMC’s specialty technology will help bridge the connection between the natural world and the computing cloud. First there is the “signal chain” of analog chips and sensors, leading to the “data chain” of connectivity, he said.

Liu reviewed a wide variety of relevant technologies, such as CMOS image sensors, microelectromechanical system (MEMS devices, embedded flash memories, biometrics, touch and display technology, and power management ICs.

At the all-day conference, which included an ecosystem exhibition by partner companies, TSMC emphasized its readiness to take on 28nm, 16nm, 10nm, and 7nm chip designs, along with the more mature process technologies. It’s game on for the foundry business.

Tallness Makes Reliable Spindt Tip Cold Cathodes

Monday, November 30th, 2015

thumbnail

By Ed Korczynski, Sr. Technical Editor

MIT researchers have seemingly found a solution to a half-century-old engineering challenge:  how to make a reliable cold cathode array for vacuum electronic devices. While solid-state technology continues to replace vacuum tubes for most electronic applications—the most recent being light emitting diode (LED) luminaires replacing both incandescent and fluorescent light bulbs—there are still applications where vacuum-based devices provide unmatched performance. At the IEEE’s upcoming annual International Electron Devices Meeting (IEDM www.ieee-iedm.org), Stephen Guerrera will present paper number 33.1 entitled “High Performance and Reliable Silicon Field Emission Arrays Enabled by Silicon Nanowire Current Limiters” on behalf of his team. Since these field emission arrays (FEA) are built in silicon, they can be integrated as cold cathodes with silicon ICs to function as compact RF amplifiers and as sources of terahertz, infrared, and X-ray energy.

Figure 1 shows a 3D illustration of the FEA structure, along with scanning electron microscope (SEM) close-up images of one tip cross-section and the tip array. The array of cold cathodes can be considered as a group of nanoscale electron guns. Each 10µm tall and 100-200nm diameter vertical silicon nanowire is topped by a 6-8nm diameter conical emitter tip.

FIGURE 1: (top) 3D schematic of the FEA device structure showing 50:1 aspect-ratio silicon nanowires, and (bottom) left-side SEM image of one tip cross-section, and right-side plan-view SEM of gate holes showing 1µm spacing and a gate aperture of 350nm.

As can be seen in the bottom left of Figure 1, the researchers used a variation on the now-standard “Bosch” deep reactive ion etch (DRIE, http://www.samcointl.com/tech/03_bosch.php) process to form the nanowires. The Bosch process uses vertical etching with side-wall dielectric deposition in alternating sequences such that cross-sections appear with characteristic scalloped profiles. It appears that the other unit-processes used by the MIT team to create this new device are likewise similar to industry standards.

However, while based on standard processes, the cost of using a Bosch etch and the other steps needed to fabricate the 50:1 aspect-ratio (AR) of these 200nm diameter wires is inherently high. In constrast, 5:1 AR structures can be formed using much less expensive processes, while 1:1 AR cones as used in original Spindt tips can be very inexpensive to make. Why do these nanowires need to be so tall?

SPINDT-TIP TRAUMAS

Decades before organic light emitting diode (OLED) technology was to be the future of flat panel display (FPD) manufacturing, Field Effect Display (https://en.wikipedia.org/wiki/Field_emitter_array FED) technology was explored as a more efficient replacement for liquid crystal displays (LCD). FED have typically been built using “Spindt Tip” Arrays, named after Charles A. Spindt who developed the technology for SRI International as originally published as “A thin-film field-emission cathode,” Journal of Applied Physics, vol. 39, no. 7, pages 3504-3505, 1968. Figure 2 shows how FED use multiple redundant Spindt Tips to light up the phosphor in each color sub-pixel. With ten or more connected in parallel, if one tip fails then the remaining tips in the sub-pixel cluster only have to handle a 10% increase in current…under another tip fails…and another tip will fail over time without a way to limit current.

FIGURE 2: Cross-sectional schematic of a pixel in a field effect display (FED), showing multiple redundant Spindt Tips driving a single phosphor dot.

Though inherently prone to reliability issues, the original Spindt Tip design is extraordinarily manufacturable. After layers of blanked film depositions, the top gate is patterned with uniform holes which serve as masks for both the etching of cavities and the deposition of tips. Each resulting cone-shaped tip concentrates the current to the point, allowing for efficient low voltage operation. The problem with concentrating current is that over time it tends to find a weak spot in grain boundaries resulting in decreased electrical resistance on one side of a tip, such that current flow over-concentrates and run-away heating causes the tip to fail.

In 2002 and still with SRI International, Spindt was co-author on “Spindt cathode tip processing to enhance emission stability and high-current performance” published by the American Vacuum Society [DOI: 10.1116/1.1527954]. The paper describes using the extracted field emission current to controllably heat and recrystallize the surface of Spindt tips to drive off impurities and smooth the tip surface, thereby producing more uniform physical arrays for more reliable functionality.

While alloys and anneals can improve the reliability, the run-away over-heating effect remains an inherent issue with conical tips. Dean et al. from Motorola worked on FEDs for many years, and found that individual tips emit from multiple nano-scale features with fluctuating current levels [DOI: 10.1109/IVMC.2001.939681]. It only takes one of these nano-scale features to preferentially line-up with a grain-boundary for it to draw relatively more current, and with electro-migration the feature can grow from the surface to be relatively closer to the gate compared to the rest of the tip. A protruding nano-spike create an extremely concentrated electrical field, which further concentrates the current flowing to the protrusion until it tends to physically explode.

TALL NANOWIRES LIMIT CURRENT

Having exhausted all easier solutions, it now appears that using DRIE to create 50:1 AR vertical nanowires is the way to make reliable FEA. The nanowires act as current limiters to protect each emitter tip from run-away heating and arcing, and thereby design-in reliability unlike simple Spindt Tip cones. Since high-quality silicon epitaxial layers with controlled dopant levels to ensure uniform electrical resistivity can be commercially sourced, the resistance of nanowire arrays etched from such an epi-layer can be easily controlled. These device reportedly exhibit long lifetimes and low-voltage operation.

The team built emitter arrays as large as 1,000 x 1,000, and have shown ability to handle current density of >100 A/cm2, more than a hundredfold greater than any other field-emission cathode operated in continuous wave mode. These new devices combine the positive aspects of solid state semiconductors (high gain and low noise) with those of vacuum electronics (high power and efficiency). While not likely to appear in commercial FPDs, there seems to be demand for this technology in diverse communications, defense, and healthcare applications.

—E.K.

Managing Dis-Aggregated Data for SiP Yield Ramp

Monday, August 24th, 2015

thumbnail

By Ed Korczynski, Sr. Technical Editor

In general, there is an accelerating trend toward System-in-Package (SiP) chip designs including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces—primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within and between chips and packages—influence the electrical properties of ICs. In this era, the industry needs to be able to model and control the mechanical and thermal properties of the combined chip-package, and so we need ways to feed data back and forth between designers, chip fabs, and Out-Sourced Assembly and Test (OSAT) companies. With accelerated yield ramps needed for High Volume Manufacturing (HVM) of consumer mobile products, to minimize risk of expensive Work In Progress (WIP) moving through the supply chain a lot of data needs to feed-forward and feedback.

Calvin Cheung, ASE Group Vice President of Business Development & Engineering, discussed these trends in the “Scaling the Walls of Sub-14nm Manufacturing” keynote panel discussion during the recent SEMICON West 2015. “In the old days it used to take 12-18 months to ramp yield, but the product lifetime for mobile chips today can be only 9 months,” reminded Cheung. “In the old days we used to talk about ramping a few thousand chips, while today working with Qualcomm they want to ramp millions of chips quickly. From an OSAT point of view, we pride ourselves on being a virtual arm of the manufacturers and designers,” said Cheung, “but as technology gets more complex and ‘knowledge-base-centric” we see less release of information from foundries. We used to have larger teams in foundries.” Dick James of ChipWorks details the complexity of the SiP used in the Apple Watch in his recent blog post at SemiMD, and documents the details behind the assumption that ASE is the OSAT.

With single-chip System-on-Chip (SoC) designs the ‘final test’ can be at the wafer-level, but with SiP based on chips from multiple vendors the ‘final test’ now must happen at the package-level, and this changes the Design For Test (DFT) work flows. DRAM in a 3D stack (Figure 1) will have an interconnect test and memory Built-In Self-Test (BIST) applied from BIST resident on the logic die connected to the memory stack using Through-Silicon Vias (TSV).

Fig.1: Schematic cross-sections of different 3D System-in-Package (SiP) design types. (Source: Mentor Graphics)

“The test of dice in a package can mostly be just re-used die-level tests based on hierarchical pattern re-targeting which is used in many very large designs today,” said Ron Press, technical marketing director of Silicon Test Solutions, Mentor Graphics, in discussion with SemiMD. “Additional interconnect tests between die would be added using boundary scans at die inputs and outputs, or an equivalent method. We put together 2.5D and 3D methodologies that are in some of the foundry reference flows. It still isn’t certain if specialized tests will be required to monitor for TSV partial failures.”

“Many fabless semiconductor companies today use solutions like scan test diagnosis to identify product-specific yield problems, and these solutions require a combination of test fail data and design data,” explained Geir Edie, Mentor Graphics’ product marketing manager of Silicon Test Solutions. “Getting data from one part of the fabless organization to another can often be more challenging than what one should expect. So, what’s often needed is a set of ‘best practices’ that covers the entire yield learning flow across organizations.”

“We do need a standard for structuring and transmitting test and operations meta-data in a timely fashion between companies in this relatively new dis-aggregated semiconductor world across Fabless, Foundry, OSAT, and OEM,” asserted John Carulli, GLOBALFOUNDRIES’ deputy director of Test Development & Diagnosis, in an exclusive discussion with SemiMD. “Presently the databases are still proprietary – either internal to the company or as part of third-party vendors’ applications.” Most of the test-related vendors and users are supporting development of the new Rich Interactive Test Database (RITdb) data format to replace the Standard Test Data Format (STDF) originally developed by Teradyne.

“The collaboration across the semiconductor ecosystem placed features in RITdb that understand the end-to-end data needs including security/provenance,” explained Carulli. Figure 2 shows that since RITdb is a structured data construct, any data from anywhere in the supply chain could be easily communicated, supported, and scaled regardless of OSAT or Fabless customer test program infrastructure. “If RITdb is truly adopted and some certification system can be placed around it to keep it from diverging, then it provides a standard core to transmit data with known meaning across our dis-aggregated semiconductor world. Another key part is the Test Cell Communication Standard Working Group; when integrated with RITdb, the improved automation and control path would greatly reduce manually communicated understanding of operational practices/issues across companies that impact yield and quality.”

Fig.2: Structure of the Rich Interactive Test Database (RITdb) industry standard, showing how data can move through the supply chain. (Source: Texas Instruments)

Phil Nigh, GLOBALFOUNDRIES Senior Technical Staff, explained to SemiMD that for heterogeneous integration of different chip types the industry has on-chip temperature measurement circuits which can monitor temperature at a given time, but not necessarily identify issues cause by thermal/mechanical stresses. “During production testing, we should detect mechanical/thermal stress ‘failures’ using product testing methods such as IO leakage, chip leakage, and other chip performance measurements such as FMAX,” reminded Nigh.

Model but verify

Metrology tool supplier Nanometrics has unique perspective on the data needs of 3D packages since the company has delivered dozens of tools for TSV metrology to the world. The company’s UniFire 7900 Wafer-Scale Packaging (WSP) Metrology System uses white-light interferometry to measure critical dimensions (CD), overlay, and film thicknesses of TSV, micro-bumps, Re-Distribution Layer (RDL) structures, as well as the co-planarity of Cu bumps/pillars. Robert Fiordalice, Nanometrics’ Vice President of UniFire business group, mentioned to SemiMD in an exclusive interview that new TSV structures certainly bring about new yield loss mechanisms, even if electrical tests show standard results such as ‘partial open.’ Fiordalice said that, “we’ve had a lot of pull to take our TSV metrology tool, and develop a TSV inspection tool to check every via on every wafer.” TSV inspection tools are now in beta-tests at customers.

As reported at 3Dincites, Mentor Graphics showed results at DAC2015 of the use of Calibre 3DSTACK by an OSAT to create a rule file for their Fan-Out Wafer-Level Package (FOWLP) process. This rule file can be used by any designer targeting this package technology at this assembly house, and checks the manufacturing constraints of the package RDL and the connectivity through the package from die-to-die and die-to-BGA. Based on package information including die order, x/y position, rotation and orientation, Calibre 3DSTACK performs checks on the interface geometries between chips connected using bumps, pillars, and TSVs. An assembly design kit provides a standardized process both chip design companies and assembly houses can use to ensure the manufacturability and performance of 3D SiP.

—E.K.

Next Page »