By Mark LaPedus

There are mixed signals in the semiconductor industry right now and it’s difficult to get a pulse on the market.

Chip demand is hot and then cold. Inventories seem to rise and fall. “We’re seeing positive signs and we’re seeing negative signs,” said Len Jelinek, an analyst for IHS. “In the U.S., one week is good. One week is bad.”

Following a disappointing period in the first quarter of this year, IHS plans to lower its chip forecast to 4.8% for 2013, down from 5.6% in the previous forecast, Jelinek said.  In 2012, the IC market fell 2.2%, according to the research firm.

“It’s a different story in the foundry market,” he said. The overall foundry market is expected to grow 20% in 2013, compared to 16.9% in 2012, according to the firm.

Another firm, VLSI Research, has recently lowered its chip forecast from 10.2% to 9.9% in 2013 over 2012. VLSI also lowered its semiconductor equipment forecast from -4.6% to -5.4% in 2013.

Earlier this year, Mike Splinter, chairman and CEO of Applied Materials, said the 2013 wafer fab equipment market would be flat to down 10% relative to 2012, reaching around $30 billion in terms of spending.

This week, Splinter maintained his forecast. “While there have been some shifts in customers’ investment plans towards mobility, we maintain our view that 2013 wafer fab equipment will be in the range of $27 billion to $30 billion,” he said on the Seeking Alpha Web site. Splinter’s comments were transcribed as Applied this week reported its results for the quarter.

Meanwhile, IHS originally thought that the first quarter would hit a seasonal lull and fall 2.4% in the period, compared to the fourth quarter of 2012. Instead, the first quarter of 2013 fell 4.4%. “It was a weaker quarter than anticipated,” Jelinek said during a keynote at the 2013 MagnaChip Semiconductor Foundry Technology Symposium in Santa Clara, Calif.

IHS also sees the chip market growing 2.3% in the second quarter and 8.3% in the third quarter, with flat growth in the fourth quarter. “2013 is driven by wireless products,” he said. “Consumer spending is second half loaded. PC and tablet sales, along with holiday spending, will drive industry revenue growth in Q3 and Q4.”

However, there are some concerns, especially with the overall economy. Europe and Japan remain in a slump. “Sequestering in the U.S. will slow economic growth in the second quarter before a modest improvement in the second half of this year,” he said. “Chinese economic growth in Q1 decelerated, but economic injections will drive overall growth to greater than 8%.”

On the semiconductor side of the equation, fab utilization will remain below optimal levels well into the second quarter. “Modest revenue growth projections with cautious increases in manufacturing should keep supply and demand in balance throughout 2013,” he said.

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics. What follows are excerpts of that conversation.

SMD: We’ve been hearing for a long time about EUV, but at this point it may not even be commercially viable at 14nm. So what do we do about that?
Liebmann: We have to keep the roadmap going, but we have to focus on performance scaling and cost per function scaling—and perhaps more so than pitch scaling. This whole idea that we’ll do double patterning and triple patterning and quadruple patterning, at some point the cost-per-function equation starts to degrade. I predict we’ll get away from these very rigorous node definitions and introduce new elements such as FinFETs to get a power/performance boost rather than focusing on 70% pitch scaling every two years because Moore’s Law says so. We have more options.

SMD: So how do we get out of this?
Aitken: That’s an excellent question, but I’m not sure there’s an equally excellent answer. The first challenge is that we have to be clear what we’re talking about. With 28nm, 22nm and 20nm, in some ways we’ve already lost touch with what those numbers actually mean. It’s similar to a size-12 shoe. It’s not 20% bigger than a size-10 shoe. It’s just somewhat bigger. In the same way, 22nm is somewhat smaller than 28nm but we’ve already lost some of the 70% pitch scaling Lars mentioned. So then we’re left with, ‘What’s actually scaling and what are the limiters?’ We’re trying to push those limiters. We need to apply more double patterning to more layers, and eventually that stops making cost-effective sense. It’s not obvious EUV will be ready even in time for 14nm, and at 10nm we’re into a lot of complexity even with EUV. There is a general issue with patterning, too. There are so many complexities associated with double patterning and so many flavors—stitching or not stitching, self-aligned or not self-aligned.
Capodieci: On double patterning, we will use it in technology development and production. It is complex and costly, but it is the only technology we have available. What’s really interesting is going beyond double patterning to triple patterning and quadruple patterning. Everybody has said at some point it will have to stop. The discussion beyond double patterning is that it makes us realize the insanity, for lack of a better word, of trying to do patterning at all. The reality is we have to stop doing patterning. That’s the wrong way to go beyond 14nm. We need to assemble and build. Patterning from the top down and creating an entire design methodology basically creates very complex systems. Then we try to create a physical design by superimposing our will onto hard matter. The hard matter pushes back. Photons don’t scale. Atoms don’t scale. And thermally, the voltage doesn’t scale. We need to discuss triple patterning, but only with the notion of destroying it.
Lin: It’s something we have to cope with at 20nm and 14nm.
White: From a tools perspective, double patterning will be necessary at 20nm. We absolutely see it, given all partners we have worked with, at 14nm. But at 14nm it will expand beyond double patterning. Whether it’s triple patterning is still a question for our customers. From an EDA perspective we perceive part of our normal business going forward. It’s an adjunct of on top of physical verification.
Capodieci: There are good solutions in place for double patterning. But in terms of design solutions as a whole, we are not there. Just because we have a signoff tool does not mean the entire ecosystem is ready. There are point solutions.
Geronimi: What is surprising is that double patterning is working quite well. This is coming from processes at other nodes where we have used design co-optimization, but this is the first time for design enablement.

SMD: Where are we with double patterning and directed self-assembly?
Liebmann: As Jean-Pierre said, we have solved the problem of double patterning for 20nm. There are no alternatives. We have rules, tools and methodologies. I would declare this problem solved.
Lin: I agree. We’re still smoothing out the kinks, but there are no major showstoppers.
Liebmann: So from here on, we can focus on the future, which involves directed self-assembly.
Aitken: There is an existence of tools at 20nm and there are various companies that have done it. But I think we’re a long way from saying these solutions have all of the kinks worked out.
Liebmann: And I would agree with that. As each new company creates a new test chip, we are having to work with them on this process, doing verification and taping out.
Aitken: One classic one we’ve been looking at recently is that when you have double-patterned metal layers you no longer have the concept of a best-case, worst-case that you had previously. You have fairly correlated situations where pattern one and pattern two get close to each other, creating a best case in one situation and a worst case in the other that migrates across the die. You have to have a method of dealing with that for timing closure. It’s not obvious how to do that with a lot of the tools today.
Capodieci: This is what I have been saying, as well. We have the solution, yes. It works, yes. But the deployment of this solution to a larger community without additional work isn’t possible, and it’s not a trivial amount of work. As engineers, we don’t just want a solution. What we want is a high-volume design to be in production. That isn’t an insurmountable problem, but it hasn’t been demonstrated yet.

Worldwide semiconductor manufacturing equipment spending is projected to total $38.9 billion in 2012, an 11.6 percent decline from 2011 spending of $44 billion, according to Gartner Inc., a research firm.

Gartner said worldwide semiconductor manufacturing equipment spending will return to double-digit growth in 2013 when spending is projected to total $43 billion, a 10.5 percent increase from 2012. Worldwide semiconductor capital spending is forecast to total $60.9 billion in 2012, down 7.3 percent from 2011 spending of $65.8 billion in 2011. Capital spending is expected to grow 3.5 percent in 2013.

“Weak market conditions in the second half of 2011 caused pullbacks in expansion plans throughout the semiconductor manufacturing industry,” said Klaus Rinnen, managing vice president at Gartner. “This investment weakness will continue through the first half of 2012 and will surge in the second half of the year. We’re basing these assumptions on the aggressive spending plans announced by the major semiconductor manufacturers. There is a risk that some capacity expansion plans will slip from the second half of 2012 into 2013.”

Source: Gartner

Worldwide semiconductor revenue is projected to total $316 billion in 2012, a 4 percent increase from 2011, according to Gartner Inc., a market research firm. This outlook is up from Gartner’s previous forecast in the fourth quarter of 2011 for 2.2 percent growth.

“The semiconductor industry is poised for a rebound starting in the second quarter of 2012,” said Bryan Lewis, research vice president at Gartner. “The inventory correction is expected to conclude this quarter, foundry utilization rates are bottoming, and the economic outlook is stabilizing.”

There are some issues in 2012. “2012 should be a reasonably strong year for the semiconductor industry if the macroeconomic outlook stays in check. Gartner’s 2012 semiconductor forecast of 4 percent growth assumes the European debt issues stay contained, Iran/Israel tensions stay in check, and solid growth from China,” he added.

In the memory sector, DRAM pricing is expected to improve beginning in the second quarter of 2012. The DRAM market will show a slight revenue increase in 2012 after being the worst-performing market in 2011, declining 25 percent. In 2012, the DRAM market is expected to grow a mere 0.9 percent, according to the firm.

DRAM prices were down about 50 percent in 2011. Gartner expects pricing to rebound in part due to the recent Elpida filing bankruptcy protection. In contrast, NAND flash memory remains one of the fastest-growing device types in 2012, with revenue forecast to grow 18 percent, according to the firm.

Media tablet unit production is forecast to increase 78 percent over 2011, and semiconductor revenue from media tablets will reach $9.5 billion in 2012. Quad-core processors and higher-resolution displays will be mainstream for tablets in 2012, they said.

PC unit production in 2012 is projected to increase 4.7 percent, and semiconductor revenue from PCs will reach $57.8 billion. Mobile phone unit production is expected to grow 6.7 percent, with semiconductor revenue for mobile phones totaling $57.2 billion in 2012.

By Mark LaPedus, SemiMD senior editor

2011 started off as a promising year for the semiconductor industry, but it ended on a sour note amid lackluster demand, bloating inventories and shaky worldwide economic factors. So what about 2012?

The semiconductor market looks mixed for 2012, as analysts predict single-digit growth for ICs and a down year for the fab tool sector.

“SIA data along with 4Q outlook by chipmakers continue to suggest semi revenues are on track to grow 1-2 percent in 2011,” said C.J. Muse, an analyst with Barclays Capital. “While we expect the inventory correction to bleed into 2012 with 1Q ‘12 likely the trough, we expect demand trends to begin to outpace end market growth beginning in 2Q ‘12, enabling overall semi revenue growth of flat to 4 percent in 2012 verses our prior estimate of 2 to 5 percent.”

Muse was referring to the data from the U.S. Semiconductor Industry Association (SIA). This week, the SIA announced worldwide sales of semiconductors were $25.1 billion for the month of November 2011, a decrease of 2.4 percent from the prior month when sales were $25.7 billion. On a year to date basis, worldwide semiconductor sales are 0.8 percent higher compared to the same period last year.

Others see a different picture. As reported, Semico Research Corp. sees 8 percent growth in the IC sector for 2012. Another firm, VLSI Research Inc., predicts 4.5 percent growth for the IC business and minus 20.1 percent for the semiconductor equipment sector in 2012.

“Sales of smartphones and tablets have been particularly strong,” according to VLSI Research. “Q1 is seasonally a soft quarter for chipmakers and this year is not going to be any different. However, we expect to see a steady improvement in IC demand as chipmakers restock due to falling inventories across the channel. An improving macro picture in the U.S. should also boost end-demand.”

Here’s what Muse says will drive the IC market:

•“Heading into 2012, we see above-average unit/silicon growth in tablets. Servers are also poised to gain in 2012, supported by both the strength of the white box market along with the refresh in the server cycle, led by Intel’s Romley platform.”

•“Led by a continued replacement cycle of basic and enhanced phones by smartphones across the globe, we model wireless semiconductor growing 10 percent in ‘12 and 19 percent in ‘13.”

•“Our guess is that the inventory correction is likely to spill into 2012 and see 1Q12 as the likely trough.”

On the other hand, the fab tool sector is soft. “For semi equipment, we maintain our year-over-year outlook for wafer fab equipment (WFE) of down 5 percent,” Barclays’ Muse said. “With spending from certain players adjusted higher for 2011, and given our expectations for foundry spending to surprise to the upside in 2012, we estimate 2012 capex down ~7 percent in 2012.”

It’s a mixed picture in the WFE sector. “With 2011 now behind us and with final numbers coming in, we believe the WFE market ended the year at ~$30 billion verses our prior estimate of $29 billion,” he said. “And given our expectations for DRAM and NAND spending to remain roughly flattish, MPU spending to decline from ~$6 billion to ~$5 billion, and foundry/logic spending to be flat to down 10 percent, we now see 2012 WFE spending of ~$28.5 billion or down ~5 percent year-over-year,” he said.

Source: Barclays Capital

Muse provides the following predictions in the arena:

•After a spending spree in 2011, Intel’s 2012 capex will decline 20 percent to about $8 billion.

•TSMC’s capex will decline from about $7.3 billion in 2011 to about $6.3 billion in 2012, a 14 percent drop.

•Samsung will need to add some 43,000 wafers a month of 32nm capacity in 2012 to support Apple’s A6 production and internal Samsung application processor demand. As a result, Samsung LSI’s budget will ramp from KRW ~4.2 trillion in 2011 to KRW ~8 trillion in 2012. Samsung’s memory capex remaining flat at KRW ~7 trillion, with a 50/50 split between DRAM and NAND in both 2011 and 2012.

•GlobalFoundries will continue to spend on tools for the Malta fab, but the company’s capex will fall from about $4.3 billion in 2011 to $3.4 billion in 2012. UMC’s spending will decline from about $1.8 billion in 2011 to about $1.0 billion in 2012.

Top capex players in 2012 (Source: Barclays Capital)

Meanwhile, it’s a mixed bag in various fab tool sectors. In lithography, it’s a down year. “Overall, we maintain our outlook for industry litho shipments in 2012. We see overall litho shipments declining from ~344 in 2011 to ~239 in 2012, driven by ~66 i-line (from 99 in 2011), ~75 KrF (from 111 in 2011), ~11 ArF dry (from 14 in 2011), and ~87 immersion (from 120 in 2011),” he said.

Muse provides one surprise in the arena: Extreme Ultraviolet (EUV) lithography will finally see its initial adoption. “Although 2011 was characterized by more muted optimism about EUV adoption, as a result of progress delays at the light source manufacturers, we believe 2012 will in fact be the ‘Year of EUV,’ where preliminary milestones are reached and EUV penetration becomes more certain,” he said.

Like lithography, ATE looks soft. “With 2011 now behind us, we believe the final 2011 SOC test spend ended at ~$2.4 billion, with the upside driven by Intel. Looking to 2012, we tweak down our market size estimate to ~$2.2 billion from our previous estimate of ~$2.3 billion, given our more muted expectations for semiconductor industry revenues,” he added.

By Mark LaPedus, SemiMD senior editor

Taking another step in the IC-packaging market, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) this week outlined its 2.5D chip interposer strategy, saying it would provide a turnkey solution for customers.

TSMC’s interposer strategy, dubbed Chip-on-Wafer-on-Substrate (CoWoS), is surprising to some observers: It is providing an end-to-end solution, including all of the traditional assembly and test steps handled by the IC packaging houses. Over the years, in fact, TSMC has moved into other IC-packaging fronts, such as wafer bumping, copper pillar bumping, and, most recently, chip-scale packaging (CSP).

Officials from TSMC have said the company is only offering these technologies as a service to some customers. But TSMC’s CoWoS program was given a lukewarm reception by some IC packaging houses, which believe that TSMC is stepping on their toes.

But in the 2.5D and 3D eras, the lines are blurring between front-end production and IC assembly. And the other leading-edge foundries are also moving into the fine-pitch 2.5D interposer fray, including IBM, GlobalFoundries, Samsung and UMC.

It’s unclear if those companies will provide a turnkey solution or not. In a recent interview, Sunil Patel, interim director for the Customer Package Technology Group at GlobalFoundries, said: “We will partner with the industry to do the silicon interposer. We are working on putting in the infrastructure.”

Within TSMC’s “interposer and assembly integration” strategy, Jesse Wang, senior manager of backend technology support and marketing at TSMC, said the silicon foundry giant has the in-house tools to provide the following steps: front-side through-silicon via (TSV) formation, chip-on wafer bonding, wafer and backside thinning, bonded interposer dicing, chip-on substrate bonding, and final test.

“We are doing everything in-house,” Wang told SemiMD. CoWoS “is an in-house flow.”

During a panel at LSI Corp.’s technology event in Milpitas, Calif. this week, Wang outlined the strategy and said the flow is designed to simplify the supply chain and resolve many of the technical issues associated with 2.5D designs.TSMC, according to Wang, is committed to bring down its 2.5D production and interposer cycle times by 50 percent by June or July of 2012.

TSMC not only wants to assume the responsibility for the risk and yields within its flow, but the silicon foundry vendor would like a bigger piece of the pie — and profits — in what could be an explosion of designs in 2.5D. Wang did not elaborate on cost. Some believe the cost for a 300-mm, 28-nm wafer at a foundry is around $5,000 today. In comparison, there are reports that the interposer itself is about $10,000 alone.

As other foundries enter the 2.5D interposer fray, the costs are expected to drop. And it will give customers choices. In fact, not all customers will go with TSMC’s entire CoWoS solution. As reported, Xilinx Inc.’s 2.5D FGPA is having the front-end manufacturing steps and interposer handled by TSMC. Amkor Technology Inc. is handling the backend steps for Xilinx, which itself does final test.

Mike Kelly, senior director of advanced 3D packaging at Amkor, said not all customers are comfortable in giving the entire 2.5D design to TSMC. “It’s OK for some customers and not OK for other customers,” Kelly said. Some chip makers would rather “spread the risk’’ or have the “freedom” to choose the best vendor for a particular flow or step, Kelly said.

Foundries and subcons collide in 2.5D supply chain (Source: Amkor)

Asked if TSMC’s CoWoS program puts the company on a further collision course with the traditional packaging houses, Kelly said the event is reminiscent of when TSMC entered the wafer bumping arena several years ago. “It was a pretty bold move,” he said. While TSMC appears to be competing against the IC-packaging houses, Amkor and others have stated that the subcontractors provide a wider range of services at better prices.

During the panel at the LSI event, Kelly said the IC-assembly houses face some new challenges in the 2.5D and 3D arena. Besides competing with the foundries, IC-packaging houses must now contend with fine defects and particulates in 2.5D and 3D assembly.

Now, the packaging houses must pay more attention to cleaner environments and contamination. “There is a paradigm shift,” he said. In the past, “you could get away with murder” in terms of having larger defects or particulates as large as 5um in assembly.

For the micro bumps in TSV production, all development and qualifications are at 40um pitch today, with 30um and 20um in R&D. Interposers range from 70um to 100um in thickness. In the future, the world could move to “smart interposers,” where these passive components may soon incorporate I/O and signaling technology, Kelly said.

The bottom line for 2.5D and 3D chip designs is clear: “Design done right makes assembly easy,” he added.

Steve Smith, senior director of platform marketing at Synopsys, said many of the EDA pieces are in place for the emerging 2.5D era. But overall, there is work to be done “on the place and route (tools) for the interposer,” he said.

Test is another key. Steve Pateras, product marketing director for Silicon Test Systems at Mentor Graphics, posed this question: “The other problem is how to test the interposer?”

The issue is the interposer is an inactive component. Some believe the next supply chain challenge will be to obtain so-called known-good interposers, that is, components with no defects. The stacked die, coupled with interposer, is driving the industry towards “partial stacked test” for 2.5D andr 3D designs, Pateras said, but there are more questions than answers in the arena.

“The question is how do you test a partial stacked device?” he quizzed. “How do I marry the tester to a partial stack?”

So in other words, having a robust flow is key in 2.5D and 3D designs. In June, Mentor Graphics announced support for 3D IC in TSMC’s Reference Flow 12.0. Mentor introduced support for 3D design rule checking (DRC), layout versus schematic (LVS) checking and extraction of back side metal in its Calibre platform last year with TSMC. RF12 adds specialized support for silicon interposer extraction and netlisting, new Calibre 3D rule decks for DRC and LVS, and enhanced debugging support enabling cross-probing across multiple die.

High defect coverage during wafer test is critical to achieving acceptable package yield in 3D-IC designs. Mentor’s Tessent solution for 3D-IC test provides a combination of ATPG and BIST capabilities.

The fab tool business is falling off a cliff.

North America-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 0.75 in September, down from 0.80 in August, according to SEMI.

A book-to-bill of 0.75 means that $75 worth of orders were received for every $100 of product billed for the month. The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers.

“Both billings and booking continue to decline with three-month average bookings almost reaching a value last reported in late 2009,” said Stanley Myers, president and CEO of SEMI. “While device makers are investing in advanced technology, broader investments await stability in the overall economic outlook.”

The three-month average of worldwide bookings in September 2011 was $984.8 million. The bookings figure is 15.3 percent less than the final August 2011 level of $1.16 billion, and is 40.4 percent below the $1.65 billion in orders posted in September 2010.

The three-month average of worldwide billings in September 2011 was $1.31 billion. The billings figure is 9.8 percent less than the final August 2011 level of $1.46 billion, and is 18.4 percent less than the September 2010 billings level of $1.61 billion.

By Mark LaPedus, SemiMD senior editor

Extreme ultraviolet (EUV) lithography is late to the market.

The critical power sources and other technologies remain behind schedule. And EUV throughput is far below what is needed in high-volume production fabs.

One source vendor, Cymer Inc., acknowledged it is behind its previous schedule for the development of sources for EUV lithography, but the company vows it will accelerate its efforts in the arena.

During a conference call to discuss its third quarter results on Thursday (Oct. 20), Bob Akins, Cymer’s chief executive officer, said the company’s EUV source developments are “tracking behind our power schedule.”

“This is very challenging technology,” Akins said, but “we are getting a handle” on the power source technology.

Cymer is one of three major players in the EUV source arena. The other players are XTREME Technologies and Gigaphoton.

The main EUV lithography scanner provider is ASML Holding NV. ASML recently confirmed the source technology is taking longer than previously expected. ASML’s current EUV tool is on track to have an overall throughput from current single digit levels to mid-teens in terms of wafers per hour by the fourth quarter of 2011. That’s far below the company’s stated goal of 60 wafers per hour by year’s end.

“The industry needs EUV at 14nm and below to stay on Moore’s Law, but that throughput issues related to the light source remains the #1 issue today,” said C.J. Muse, an analyst with Barclays Capital, in a report. Muse issued the report at this week’s International Symposium on EUV Lithography in Miami.

“Chipmakers are growing uneasy about the 14nm node as EUV will be necessary to stay on Moore’s Law,” Muse said. “With throughput on EUV still in the low teens, well below promised 60+/wph and then 100+/wph, there was clear frustration on part of participants with the roadmap slippage of EUV light source throughput. As one participant highlighted, the ‘roadmap slip for EUV sources must stop.’ “

EUV sources are based on two basic technologies: laser-produced plasma (LPP) and discharge-produced plasma (DPP). “In an LPP source, the plasma is generated by a focused laser pulse hitting an appropriate target material. The target (mass-limited droplets emitted at a very high frequency) is designed to minimize the generation of debris,’’ according to XREME. “In a DPP source, on the other hand, the plasma is generated within an electrode system by an electrical discharge in the gas phase (Xenon).”

There is a third technology, dubbed laser-assisted discharge plasma (LDP), which is a hybrid technology.

Cymer’s technology is based on LPP technology. So far, Cymer of San Diego has shipped four EUV light sources to Intel, Samsung, Toshiba, and Hynix, with a fifth that is being installed at TSMC, according to Muse.

The technical challenges include the droplet generator and the collector. “Today, the tool is showing a power of 8 watts and 50 percent availability in the field (equivalent to uptime), which is analogous to overall 11/wph throughput,” Muse said.

Cymer’s next upgrade, dubbed “Upgrade 1,” will result in increasing “exposure power to 20 watts, less than 0.5 percent dose stability and 90 percent duty cycle by December 2011,” he said. “Then, ‘Upgrade 2A’ is expected to drive to 50 watts exposure power at continuing mode using a different laser architecture by March 2012.”

“Upgrade 2B” should enable Cymer to see 100 watt exposure power at continuous mode with pre-pulse, which is analogous to 60/wph. Cymer expects to ship that upgrade by the second quarter of 2012, according to Akins.

Meanwhile, on Thursday, Cymer reported quarterly net income of $11.3 million, or $0.36 per share, compared to net income of $20.9 million, equal to $0.70 per share in the third quarter of 2010 and net income of $27.7 million, equal to $0.89 per share in the second quarter of 2011.

Quarterly revenue totaled $128.7 million, compared to revenue of $141.7 million in the third quarter of 2010, and revenue of $158.2 million in the second quarter of 2011.

“We believe we have identified and are addressing the key EUV source technical challenges facing us and we are working closely with ASML and our key suppliers to drive execution to our source power and performance roadmap,” Cymer’s Atkins said. “Our investment in EUV source development is substantial and one we view as essential to enable lithography scaling, and which we believe will drive significant long term growth.”

Others are also working on EUV sources. Earlier this year, rival Gigaphoton Inc. confirmed its LPP light source for EUV will be shipped in the beginning of 2012. “We are on track to prepare for the EUV business,” said Yuji Watanabe, president of Gigaphoton, in a recent statement.

The company has proposed a number of technologies in EUV sources, including mitigation of debris by using magnetic fields. The debris mitigation technology with magnetic fields allows greater reduction in Sn (tin) deposited on the collector mirror as well as in damage to the multi-layer film of the mirror, according to the company.

The other EUV source maker, XTREME, is developing products based on LDP technology. It combines the advantages of the traditional laser based and traditional discharge based technologies to generate EUV photons. Earlier this year, IMEC announced printing of the first EUV wafers with ASML’s NXE:3100 mounted with XTREME’s LDP source.

Suss MicroTec AG has sold its mask manufacturing business — Suss MicroTec Precision Photomask Inc. (formerly known as Image Technology Inc.) — in Palo Alto, Calif. to Compugraphics Inc.

Compugraphics is a mask manufacturer with mask shops in the U.S., U.K. and Germany.

The divestment of the mask business is a further step of Suss to focus on its profitable and high growth core business areas. The transaction will have no effect on the consolidated income statement.

Compugraphics Inc., a subsidiary of OM Group, has acquired all the assets of Suss MicroTec Precision Photomask. It will continue operations in the U.S.