By Mark LaPedus, SemiMD senior editor
Taking another step in the IC-packaging market, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) this week outlined its 2.5D chip interposer strategy, saying it would provide a turnkey solution for customers.
TSMC’s interposer strategy, dubbed Chip-on-Wafer-on-Substrate (CoWoS), is surprising to some observers: It is providing an end-to-end solution, including all of the traditional assembly and test steps handled by the IC packaging houses. Over the years, in fact, TSMC has moved into other IC-packaging fronts, such as wafer bumping, copper pillar bumping, and, most recently, chip-scale packaging (CSP).
Officials from TSMC have said the company is only offering these technologies as a service to some customers. But TSMC’s CoWoS program was given a lukewarm reception by some IC packaging houses, which believe that TSMC is stepping on their toes.
But in the 2.5D and 3D eras, the lines are blurring between front-end production and IC assembly. And the other leading-edge foundries are also moving into the fine-pitch 2.5D interposer fray, including IBM, GlobalFoundries, Samsung and UMC.
It’s unclear if those companies will provide a turnkey solution or not. In a recent interview, Sunil Patel, interim director for the Customer Package Technology Group at GlobalFoundries, said: “We will partner with the industry to do the silicon interposer. We are working on putting in the infrastructure.”
Within TSMC’s “interposer and assembly integration” strategy, Jesse Wang, senior manager of backend technology support and marketing at TSMC, said the silicon foundry giant has the in-house tools to provide the following steps: front-side through-silicon via (TSV) formation, chip-on wafer bonding, wafer and backside thinning, bonded interposer dicing, chip-on substrate bonding, and final test.
“We are doing everything in-house,” Wang told SemiMD. CoWoS “is an in-house flow.”
During a panel at LSI Corp.’s technology event in Milpitas, Calif. this week, Wang outlined the strategy and said the flow is designed to simplify the supply chain and resolve many of the technical issues associated with 2.5D designs.TSMC, according to Wang, is committed to bring down its 2.5D production and interposer cycle times by 50 percent by June or July of 2012.
TSMC not only wants to assume the responsibility for the risk and yields within its flow, but the silicon foundry vendor would like a bigger piece of the pie — and profits — in what could be an explosion of designs in 2.5D. Wang did not elaborate on cost. Some believe the cost for a 300-mm, 28-nm wafer at a foundry is around $5,000 today. In comparison, there are reports that the interposer itself is about $10,000 alone.
As other foundries enter the 2.5D interposer fray, the costs are expected to drop. And it will give customers choices. In fact, not all customers will go with TSMC’s entire CoWoS solution. As reported, Xilinx Inc.’s 2.5D FGPA is having the front-end manufacturing steps and interposer handled by TSMC. Amkor Technology Inc. is handling the backend steps for Xilinx, which itself does final test.
Mike Kelly, senior director of advanced 3D packaging at Amkor, said not all customers are comfortable in giving the entire 2.5D design to TSMC. “It’s OK for some customers and not OK for other customers,” Kelly said. Some chip makers would rather “spread the risk’’ or have the “freedom” to choose the best vendor for a particular flow or step, Kelly said.
Foundries and subcons collide in 2.5D supply chain (Source: Amkor)
Asked if TSMC’s CoWoS program puts the company on a further collision course with the traditional packaging houses, Kelly said the event is reminiscent of when TSMC entered the wafer bumping arena several years ago. “It was a pretty bold move,” he said. While TSMC appears to be competing against the IC-packaging houses, Amkor and others have stated that the subcontractors provide a wider range of services at better prices.
During the panel at the LSI event, Kelly said the IC-assembly houses face some new challenges in the 2.5D and 3D arena. Besides competing with the foundries, IC-packaging houses must now contend with fine defects and particulates in 2.5D and 3D assembly.
Now, the packaging houses must pay more attention to cleaner environments and contamination. “There is a paradigm shift,” he said. In the past, “you could get away with murder” in terms of having larger defects or particulates as large as 5um in assembly.
For the micro bumps in TSV production, all development and qualifications are at 40um pitch today, with 30um and 20um in R&D. Interposers range from 70um to 100um in thickness. In the future, the world could move to “smart interposers,” where these passive components may soon incorporate I/O and signaling technology, Kelly said.
The bottom line for 2.5D and 3D chip designs is clear: “Design done right makes assembly easy,” he added.
Steve Smith, senior director of platform marketing at Synopsys, said many of the EDA pieces are in place for the emerging 2.5D era. But overall, there is work to be done “on the place and route (tools) for the interposer,” he said.
Test is another key. Steve Pateras, product marketing director for Silicon Test Systems at Mentor Graphics, posed this question: “The other problem is how to test the interposer?”
The issue is the interposer is an inactive component. Some believe the next supply chain challenge will be to obtain so-called known-good interposers, that is, components with no defects. The stacked die, coupled with interposer, is driving the industry towards “partial stacked test” for 2.5D andr 3D designs, Pateras said, but there are more questions than answers in the arena.
“The question is how do you test a partial stacked device?” he quizzed. “How do I marry the tester to a partial stack?”
So in other words, having a robust flow is key in 2.5D and 3D designs. In June, Mentor Graphics announced support for 3D IC in TSMC’s Reference Flow 12.0. Mentor introduced support for 3D design rule checking (DRC), layout versus schematic (LVS) checking and extraction of back side metal in its Calibre platform last year with TSMC. RF12 adds specialized support for silicon interposer extraction and netlisting, new Calibre 3D rule decks for DRC and LVS, and enhanced debugging support enabling cross-probing across multiple die.
High defect coverage during wafer test is critical to achieving acceptable package yield in 3D-IC designs. Mentor’s Tessent solution for 3D-IC test provides a combination of ATPG and BIST capabilities.