Posts Tagged ‘Semicon West’
By Pete Singer
At Semicon West last week (and at The ConFab a few weeks ago) some key trends were clearly evident in the semiconductor industry.
It’s apparent that the world’s appetite for electronics has never been greater. That has increasingly taken the form of mobile electronics, including smartphones, tablets and tablets and the new “phablets.” People want to watch movies and live sports on their phones. They want their mobile devices to be “situationally aware” and even capable of monitoring their health through sensors. That drives higher bandwidth (6G is on the drawing board), faster data rates and a demand for reduced power consumption to conserve battery life. At the same time, “big data” and the internet of things (IoT) are here, which drives the demand for server networks and high performance semiconductors, as well as integrated sensors and inventive gadgets such as flexible displays and human biosensor networks.
It’s also pushing the semiconductor manufacturing industry in new directions. Chip makers typically face tradeoffs between power, performance, area and cost/complexity (PPAC). For mobile devices, the push is to low power, high performance, small area and low cost.
For me, one of the main themes of Semicon West was the demand for mobile devices and how they might impact what has become standard thinking in the semiconductor industry in terms of scaling, performance, power and cost.
At Semicon West 2013, Karen Savala, president of SEMI Americas, kicked things off, noting that it was the 43rd year of Semicon West (32nd consecutive one for me personally). “While much has changed over the years, the one that has been constant is the power of our industry to continually drive innovation, to overcome technical challenges and economic challenges, and develop new processes, new materials and technologies that continue to move Moore’s Law forward,” Savala said. “2013 is no different. The industry finds itself at a critical juncture where multiple technology developments, including 450mm, FinFETs, 3D ICs, advanced materials and processes, and EUV just to name a few, promise to move Moore’s Law ahead. But as we have done before, we will address these challenges, bring new technologies to market, and continue to amaze the world with the power of our collective innovation.”
Karen then introducde the keynote, Ajit Monacha, CEO of Global Foundries, who expanded on his Foundry 2.0 concept, and talked about how the requirements of mobile devices were, in fact, changing the entire semiconductor industry. He noted that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.
This incredible growth is driving new dynamics, said Manocha, and pushing the industry to the new technology node each year, which is presenting the industry with what Manocha deems the Big Five Challenges. Manocha believes these challenges are: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition. I don’t recall when cost wasn’t an issue, but an audience poll revealed that most people believe economic challenges will be the main factor limiting industry growth, not technical challenges, so cost moves to the top of the list.
After his talk, Ajit was presented with the “SEMI Outstanding EHS Achievement Award — Inspired by Akira Inoue” by Denny McGuirk, president and CEO of SEMI. During Semicon West, SEMI also honored 14 industry leaders for their outstanding accomplishments in developing standards for the microelectronics and related industries
Part of “the buzz” at the show was the rosy prediction issued by SEMI about growth in capital equipment for next year. SEMI forecasts semiconductor equipment sales will reach $43.98 billion in 2014, a 21 percent increase over estimated 2013 equipment spending, according to the mid-year edition of the SEMI Capital Equipment Forecast, released during the show.
A new spin on spintronics; Novel solid-state nanomaterial platform enables terahertz photonics; Novel crumpling method takes flat graphene from 2-D to 3-D
Fabrication of patterns with linewidths down to 1.5nm; New method allows for greater variation in band gap tunability; New pathway to valleytronics
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.