By David Lammers
Intel’s decision to invest as much as $4.1 billion in ASML has raised overall confidence levels in EUV lithography, and should allow the Dutch lithography vendor to funnel more funds into the stubbornly difficult effort to raise the EUV source power.

ASML has said it needs to reach 250 Watts of average source power to achieve the 125 wph throughputs sought by its early customers—roughly 10x today’s situation. However, with an influential Intel lithography manager saying that EUV source power needs to be in the 1,000 Watt range for contact holes and other critical layers, it is clear that source power remains far less than is needed.

Cymer Inc. (San Diego) recently said it has achieved 50 watts of average output power at a 40% percent duty cycle, operating for five hours in a closed loop. While scanners must step between die and pause for a few milliseconds, one lithography expert said a 40% duty cycle at 50W is essentially a 25W source at the required 80% to 90% duty cycle.

Hans Meiling, director of product management at ASML, emphasized the rate of progress, saying that a year ago the Cymer laser-produced-plasma (LPP) sources on the NXE: 3100 scanners were capable of only 1 to 2 watts of source power. “Today we are a factor of 10 higher, at 10 watts, which gives a throughput of six to seven wafers per hour,” he said. By the middle of next year ASML expects to have 70 watts of source power in its NXE:3300B EUV scanners.

EUV radiation is produced by hitting tin droplets with a powerful laser, and then filtering the 13.5 nm EUV wavelength. “Our suppliers are focused on the pre-pulse concept to create a mist of tin for higher conversion efficiency,” Meiling said at the Semicon West trade show.

Nigel Farrar, vice president of technical marketing at Cymer, said pre-pulsing the tin droplets—as they are dropping at 60 meters per second—“puffs them up a bit” so the CO2 laser can achieve a higher in-band conversion efficiency.

Three avenues at Cymer
Pre-pulsing is one of a trio of techniques Cymer is building in to the second-generation sources that ASML will integrate with its NXE:3300B scanners coming to market next year. These “HVM II” sources are a new architecture, and will boost the laser input power by using four amplifiers instead of three. Also, the collector efficiency is being improved by using a built-in capping layer on top of the molybdenum-silicon (MoSi) multilayer on the collector optics.

The vessel for the HVM II source being developed by Cymer, Inc. (Source: Cymer)

Farrar said Cymer was able to operate the collector module for four months, up from what Meiling said was about a week a year ago, extending the operating time by incorporating a hydrogen clean technique.

“We are going through learning cycles, using parallel activities on three dedicated systems,” Farrar said. While reaching its source-power goals is taking much longer than expected, he said there are no fundamental scientific reasons standing in the way of adequate source power. “It is not physics; it is engineering,” Farrar said.

Nevertheless, breakthroughs are needed. Meiling said ASML engineers are working at Cymer to create fully automated controls and introduce other techniques. “The leveling off can be eliminated. We can reach 90 to 100 watts with our current knowledge. A year ago we could not show you pre-pulse. Now we can do that for 5.5 hours,” he said.

Throughput, however, depends on combining a more-powerful source with a photoresist, which combines sensitivity and acceptable shot noise, line edge and line width roughness (LER and LWR) and other variables. Meiling noted that contacts—the holes that are one of the most critical device layers, requiring the best-resolution lithography—require a less-sensitive resist chemistry, which in turn calls for a higher source power.

“A joint effort has to come from both sides, from the resists and the source-scanner development,” Meiling said.

1,000 watts for contacts?
Yan Borodovsky, an Intel senior fellow and director of advanced lithography at the Technology and Manufacturing Group in Portland, said that EUV source power needs to be in the range of 1,000 watts for the contact holes, partly due to the much slower resists required for good contact hole patterning. Contact resists must be in the range of 60 to 70 milliJoules/cm².

Speaking at the 2012 International Workshop on EUV Lithography, held recently in Maui, Hawaii, Borodovsky spoke about the need for optical proximity correction (OPC) infrastructure development in order to overcome the 3D effects in EUV masks.

At the EUVL Workshop, Borodovsky concluded that EUV source power targets “need to be revised upwards” to more than a kilowatt of average in-band source power at the intermediate interface for EUV to be used for contact patterning and complementary lithography: a combination of gratings patterned with immersion ArF scanners with “cut mask” layers to create cuts in the lines.

Franklin Kalk, CTO at Toppan Photomasks, said EUV could be far more efficient that immersion ArF for the cut masks, requiring only one mask layer rather than four for 193 immersion.

The relationship between EUV source power and resist sensitivity has been hotly debated for the last decade, with EUV critics arguing that the ITRS roadmap assumes EUV resists which are far more sensitive than can be realistically achieved. Borodovsky said much of the discussion about EUV lithography has focused on using EUV for contacts and vias, while failing to fully acknowledge the shot noise, LER, and random or stochastic effects of EUV resists. At Semicon West, Borodovsky praised the rate of progress on EUV resist development, but emphasized that the most sensitive resists are not practical for the contacts and vias, where much slower resists are required to meet yield targets.

“Shot noise statistics alone lead to the conclusion that source in-band average power needed to expose resist capable of meeting the high-volume-manufacturing contacts and cuts patterning requirements might need to exceed 1,000W at the intermediate focus (IF),” Borodovsky said at the workshop.

Directed Self Assembly (DSA) might help relieve the situation, shrinking the contacts, vias, and cuts created either with 193i, EUV or direct-write E-beam, Borodovsky said during the lithography TechXPOT at Semicon West. “DSA will be used extensively, either in conjunction with 193i, or to shrink the cuts and vias down while rectifying EUV/EB size variability induced by shot noise and other stochastics,” he concluded.

Bettina Weiss, who heads SEMI’s solar effort, talks about what’s new at Semicon and Intersolar North America, how far the industry has progressed and what stands in the way of widespread adoption of solar technology.

IC packaging innovations are competing with next-node processing technologies as the critical platform for competition in the mobile segment.  OEMs, system developers, foundries, packaging and test subcontractors, chip manufacturers, and fabless chip companies are placing high-risk, high-stakes bets on next generation packaging solutions that are more able to deliver “faster, better, cheaper”  results than advances in wafer processing.  Many of these companies will be discussing their views of the increasing complex and varied IC packaging options at Semicon West, to be held on July 13-15, 2011 in San Francisco.

The drive for 3D, for example, has spawned a whole ecosystem, and silicon interposer (2.5D) technology based upon TSV has become an important technology in this first wave of 3D implementation. However,  without design standards, test platforms, and roadmaps that link the strategies of memory, MPU, GPU and other chip manufacturers— including foundries and packaging firms– to a common, achievable vision, the benefits of 3D-IC could be elusive.

These and other critical issues in 3D IC will be discussed in the open session, “3D in the Deep Submicron Era” to be held from 1:30-5:00pm at the NorthOne TechXPOT stage on Wednesday, July 13.  Hosted by session chairs, Jie Xue, director, Technology & Quality, Cisco Systems and Gamal Rafai-Ahmed, AMD fellow, AMD, the session will feature speakers from Xilinx, Sematech, ITRI, Georgia Institute of Technology, Amkor Technology, GlobalFoundries, Avago Technologies, Mentor Graphics, Yole Developpment, Renesas, IBM, ASE, Imec, Applied Materials, and Qualcomm.

While much has been written about emerging packaging and integration technologies like 3D TSV, a majority of today’s IC market is optimizing and migrating to advanced packaging technologies such as copper wire bonding, cu pillar flip chip, fan-out wafer level packaging, and other proven solutions.  Current trends and developments in these areas will be explored in the session, “Contemporary Packaging: Challenges and Solutions for 40nm and Beyond,” held on Wednesday, July 13 from 10:30am-12:30pm at the NorthTwo TechXPOT.  Led by session chairs, Tom Gregorich of MediaTek and Rich Rice of ASE, this session will feature presentations and panel discussions with representatives from Gartner, GlobalFoundries, TSMC, Siliconware Precision Industries (SPIL), Atmel, and STATS ChipPAC.

Mobile devices are also being transformed by MEMS sensors and devices that leverage advanced packaging technologies and require tight integration with ICs.  Session chair Klaus-Dieter Lang, head of Fraunhofer IZM, will lead the session, “Heterogeneous Integration with MEMS and Sensors” on Tuesday, July 12 from 2 pm-4 pm at the NorthOne TechXPOT.This session explores leading integration technologies and strategies in MEMS featuring speakers from Microsoft, TechSearch International, Fraunhofer IZM, Toshiba, CEA-Leti, Infineon Technologies, Silex Microsystems, NIST, and Analog Devices.

More information on packaging technology and trends sessions at Semicon West can be found at http://www.Semiconwest.org/Segments/Packaging.  Other activities at Semicon West that deal with packaging technology and solutions include: an Opening Keynote by Tien Wu, president of ASE, on July 12, the ITRS Summer Public Conference, the IMAPS Workshop on Advanced Interconnect Technologies on July 13, and the IMAPS Workshop on Wire Bonding on July 14. To learn more about Semicon West, visit:

By David Lammers

Now that Intel Corp. and TSMC have publicly committed to finFETs at the 22nm and 14nm nodes, respectively, attention is turning to what the next moves will be from the ultra-thin-body SOI camp.

At the recent Symposium on VLSI Technology, held in Kyoto, Japan, a 22nm technology platform based on extremely thin SOI substrates was presented, with a 25 percent improvement in ring oscillator speed compared with a 28nm bulk transistor. The presentation from a team based in Albany, N.Y. (IBM, STMicro, GlobalFoundries, Renesas, and Toshiba) included analog devices and SRAMs with a 0.08 square micron cell size.

A faceted raised source-drain design reduced parasitic capacitance. And the researchers said the undoped channel in ETSOI “greatly reduces the random dopant fluctuation, a major source of device variation.”

The competition between finFETs and the planar ultra thin body SOI is the subject of a TechXPOT at Semicon West on Tuesday, July 12^th, beginning at 10:30 a.m. The two-hour Emerging Architectures for Logic and Memory session includes presentations from Serge Biesemans, vice president of process technology at Imec, on FinFETs; Ali Khakifirooz,  ETSOI lead device engineer at IBM Research, on the ultra thin body SOI approach; and Raj Jammy, vice president of materials and emerging technologies at Sematech, on the heterogeneous integration of high mobility Ge/III-V channels on silicon.

Transistor at left has a silicon thickness of 5 nm. Photo at right shows first-level metal patterning of the SRAM cell. (Source: Symposium on VLSI Technology).

This week, several of the SOI wafer suppliers, including MEMC, SEH, and Soitec, said they are ready to supply the UTB-SOI wafers in high volumes. To support a fully depleted transistor, the critical silicon layer must be kept to 10 nm or less, with minimal variations. Because the cost of the wafers is partially offset by a less-expensive isolation process, the SOI Consortium is claiming no overall increase in the cost of a processed UTB-SOI wafer compared with bulk silicon.

The wafer suppliers in part are responding to comments made by Intel senior fellow Mark Bohr in early May, when Intel rolled out its 22nm finFET-like tri-gate technology. During the press conference, Bohr said Intel’s finFET process cost was just a few percent higher than its planar technology. “Those extremely thin (silicon and BOX layer) SOI wafers are available, but they are very expensive, and pretty hard to get,” Bohr said. He said Intel’s estimate is that using a thin-layered SOI wafer would add 10 percent to the finished wafer cost.

Those assertions riled executives at the SOI wafer suppliers, who have invested in facilities to make the SOI wafers in volumes, sufficient to meet demand from companies making chipsets for smart phones and other mobile systems.

Christophe Maleville, general manager of  Soitec’s microelectronics business unit, said Soitec has an installed industrial base of 2 million wafers per year at its two 300-mm SOI wafer production fabs in Bernin, France and in Singapore.  “We are prepared to expand our SOI capacity to accompany the introduction of FD-SOI technology in very high-volume consumer applications,” Maleville said.

The “Xtreme SOI” wafers from Soitec have “Angstrom-level uniformity, using the same technology platform as our large-volume current production,” Maleville said.

Soitec has licensed its Smart Cut SOI wafer-production technology to Shin-Etsu Handotai (SEH), the largest wafer supplier worldwide, and SEH has completed development of its UTB substrates. Noburo Katsuoka, director of the SOI program at SEH, said “SEH is delighted to deliver the products on request.”

MEMC, based in St. Louis, has been a second source to IBM for the SOI wafers it uses for its partially-depleted CMOS production. Shaker Sadasivam, president of MEMC Semiconductor Materials, said, “MEMC is ready to facilitate and encourage the faster adoption of fully depleted SOI for mobile applications. Large volume utilization is a key factor to achieve reduced pricing for FD SOI, and MEMC has capacity that can be readily expanded to meet industry needs for volume production.”

Sadasivam added that “plans have been developed to expand our FD SOI production to approximately 45,000 wafers per month.”

Horacio Mendez, executive director of the SOI Industry Consortium, said some high-volume mobile IC vendors may introduce fully depleted SOI technology before the 14/15nm node, though FD-SOI will “come in at full force at 14 nanometers.”

A key demand from the mobile IC providers is to have multiple wafer vendors, partially in order to gain lower wafer costs. Soitec has committed to $500 per-wafer pricing in volumes for FD-SOI wafers.

The SOI consortium has been working with a fairly large team of engineers from ARM Ltd. to prove out the advantages of FD-SOI at the 22nm node, Mendez said. Further information about that development project will be made public later this summer, he said.

Mendez said he strongly disagrees with Bohr’s assertion that FD-SOI will add 10 percent to the cost of a planar CMOS silicon process. Because the implant and isolation steps are so much simpler with an SOI substrate, the SOI Consortium believes the finished cost of an SOI wafer will be about 6 percent less than a bulk silicon wafer.

“At 20nm, the performance of a fully depleted technology is so good that companies feel they don’t need to add the stressors, saving on costs there,” said Mendez, a former MPU designer at Freescale Semiconductor.

While Intel may have the manufacturing muscle to implement its tri-gate technology, Mendez said there are few other companies that will be able to make finFETs at good yields. “The yields on finFETs have to be challenging. At the beginning, companies will run into rough patches, where they will not see the same yields as planar transistors,” Mendez said.

One thing the SOI Consortium and Intel agree on: bulk silicon CMOS “is not going to cut it past the 22nm node,” he said.

This year for the first time, Semicon West will directly address the need for design-manufacturing supply chain collaboration and communication. The Advanced Technology Manufacturing TechZone will include technical sessions and a specialized exhibit and networking area focused on the design to production test process flow.

Participating exhibitors at the Advanced Technology Manufacturing TechZone span the industry supply chain, including software (Mentor Graphics), foundries and device makers (GlobalFoundries, IBM Fishkill, Samsung America), packaging and test companies (Amkor Technology, ASE), and semiconductor test equipment (Verigy, Optimal Test). Other exhibitors include the College of Nanoscale Science and Engineering (CNSE), Connectec Japan, SET Smart Equipment Technology (SET), Soltec/NEC Avio, and Toppan Photomasks.

On the nearby TechXPOT technical presentation stage, two panel discussions will focus on design and manufacturing topics. The first, Improving Yield (Tuesday, July 12 from 10:30am-11:35am, NorthTwo TechXPOT), will look at improving yield from front-end design “must haves” such as ESL modeling and built-in test, to back-end restrictive design rules; lithography advances such as EUV and computational scaling; pattern optimization; the effects of CMP and new substrate options; and the future effects of Moore’s Law and 2.5D/3D stacking. Panelists include Applied Materials, GlobalFoundries, PDF Solutions, Tela Innovations, and Texas Instruments.

The second design-manufacturing panel, Stacking Effects (Tuesday, July 12 from 11:40am-12:45pm, NorthTwo TechXpot), will look at how 2.5D and 3D technologies will change the global supply chain and explore questions of collaboration and integration of design and manufacturing technologies involving IP from multiple vendors, multiple vendor tools, different process technologies, and companies that have never had to work together in the past. Confirmed panelists include speakers from ARM, eSilicon, Open Silicon, Qualcomm, and Tessera Technologies.

On Wednesday, July 13, SEMI and the Silicon Integration Initiative (Si2) will present a workshop on “DFM Standards: Driving Design Ecosystems from PDK’s to Manufacturing,” including presentations from Cadence, IBM, LSI, Mentor Graphics, Springsoft, and Texas Instruments. The workshop will be held from 1:00-4:00pm in Room 124 in the Lower North Hall Lobby at Moscone Center.

The challenges—and costs—of greater integration and collaboration across the supply chain are particularly risky for start-ups and fabless companies bringing new products to market, as well for IDMs, research organizations, and universities. The Enabling Advanced Technology Prototype/Pilot Design and Manufacturing session (Thursday, July 14, 10:30am-12:30pm, NorthTwo TechXPOT), will highlight the unique pilot scale design and manufacturing services available to facilitate the rapid commercialization of new and innovative products. Speakers represent Toppan Photomasks, College of Nanoscale Science and Engineering at the University at Albany, University of Washington, SVTC Technologies, Mosis, and eSilicon.

Karen Savala, president of SEMI Americas, said, “As the design community has expanded into the fabless space, and as the complexities of device manufacturing increase, there is a need for Semicon West to widen its scope, to bring these new audiences together at the show, and to create a platform for creativity, communication and collaboration.”

Two executive-level panel discussions planned for Semicon West will take up several of the challenges facing semiconductor manufacturers, including the transition to 450-mm wafers and new technologies including vertical transistors (FinFETs), 3D-IC, and EUV lithography.
The Semicon West Executive Summit on July 13 will take up the trends and issues facing the equipment and materials industry over the next 10 years, including market drivers, political and economic megatrend implications, and public policy. Panelists include Dave Miller, president, DuPont Electronics and Communications; Doug Neugold, chairman, chief executive officer, and president, ATMI; Stephen G. Newberry, chief executive officer and vice chairman, Lam Research; and Richard Wallace, president and chief executive officer, KLA-Tencor. The Executive Summit takes place on Wednesday, July 13 from 1:30-3:00pm at Moscone Center, Keynote Stage in Esplanade Hall.

The industry appears poised to go beyond talking and begin serious planning for 450-mm wafers.  On July 14 at SEMICON West, the 450-mm Transition Forum will feature a review of the R&D initiatives that may lead to fuller implementation of 450-mm wafer processing and provide a status of the prevailing challenges for device makers and their suppliers. Panelists include David Bennett, vice president of Alliances, GlobalFoundries; Bob Johnson, research vice president, Gartner; Hans Lebon, vice president, Fab and Process Step R&D&M Technology, IMEC; Brian Trafas, chief marketing officer, KLA-Tencor; and David Hemker, vice president, New Product Development, Lam Research. The 450-mm Transition Forum takes place on Thursday, July 14 from 10:30am-12:30pm at Moscone Center in North Hall at the NorthOne TechXPOT.

Both panel sessions, like all presentations on the Keynote Stage and the four TechXPOT technical stages on the SEMICON West show floor, are open to all registered attendees. For more information on these and other events, and to register, visit www.semiconwest.org.

Sematech and the International Sematech Manufacturing Initiative (ISMI) will present a variety of technology solutions at Semicon West, planned for July 11–15 in San Francisco.

Sematech and ISMI experts will report their latest advances in new materials and device structures and lithography with a special focus on addressing key opportunities and challenges in 3D interconnect technology.

Several Sematech experts are scheduled to speak on the Semicon West TechXPOT Stage, in the North and South Halls of the Moscone Center, including:

• Raj Jammy, Sematech’s vice president of Emerging Technologies, speaking on “Heterogeneous Integration of High Mobility Ge/III-V Channels on Si,” July 12 at 11 a.m.
• David Gilmer, Sematech’s project engineer of Advanced Memory Technologies, “Metal-Oxide based RRAM Materials and Development,” July 12 at 11:30 a.m.
• Stefan Wurm, Sematech’s associate director of Lithography, “EUV Mask Infrastructure (EMI) Partnership,” July 13 at 11:05 a.m.
• Sitaram Arkalgud, Sematech’s director of Interconnect, will co-moderate panel session 1 in the 3D in the Deep Submicron Era, July 13 at 1:50 p.m.
• Chris Hobbs, Sematech’s CMOS scaling program manager of Front End Process, “Non-Planar CMOS Device Challenges and Opportunities,” July 14 at the NCCAVS Advanced Process and Integration in Semiconductor Technologies session.

Additionally, Sematech and ISMI experts will host and present at various public workshops, at the Marriott Marquis, during Semicon West:

• Equipment suppliers will identify opportunities and bridge understandings on enabling 3D technology in the wafer handling process space at the workshop Enabling 3D: Temporary Bonding Workshop on July 11 at 1 p.m.
• Equipment suppliers and end users will meet to address topics such as SEMI S23 reporting and goals, applying high temperature process cooling water on process tools, and idle mode interface for process equipment subsystems at the ISMI Equipment Energy Workshop on July 12 at 8 a.m.
• Equipment suppliers will share their plans on how new and existing wafer metrology technologies can be used, modified, or enhanced to measure and improve 3D interconnect processes at Sematech’s 3D Metrology Workshop on July 13 at 12 p.m.
• Co-sponsored by SEMI and ISMI, the EDA Workshop will focus on the equipment data acquisition (EDA) interface requirements and implementation for the 0710 standards freeze level. Participants will be able to discuss with industry experts how the changes for the new freeze level can be implemented and evaluated on July 13 at 1 p.m.
• A day-long preview of this year’s International Technology Roadmap for Semiconductors will be offered at the Summer ITRS Public Conference on July 13.
• Hosted by Sematech, in collaboration with Fraunhofer IZFP, the fifth workshop on Stress Management for 3D ICs using Through Silicon Vias will discuss product-level reliability, including product qualification, product level test requirements, and failure analysis on July 14 at 9 a.m.
• Co-organizing and/or speaking at various SEMI standards workshops in 3D interconnect, lithography, and manufacturing.

The challenges in manufacturing HB-LEDs, MEMS, power solutions, and printed electronics will be discussed during the “Extreme Electronics” sessions planned for the three days of Semicon West 2011.

Described as “a show within the show,” more than 20 free technical sessions are planned for the Extreme Electronics TechXPOT stage during the exposition, planned for July 12-14 at the Moscone Center in San Francisco. In addition, several hundred of the exhibitors will describe their solutions for these emerging markets.

Technological advances in solid-state lighting, flexible displays and PV, micro-machines, thin film sensors, new power ICs, and many other emerging technologies are on the agenda, SEMI said. Extreme Electronics is a dedicated exhibition area and presentation forum for technical presentations on the challenges, trends and solutions addressing these high-growth markets.

The Extreme Electronics Sessions include:

Solid State Lighting and HB-LED

More Lumens per Dollar: Issues and Answers to Bring Costs Down to Create the General Lighting Market; Wednesday, July 13, 10:30am–4:30pm.  Speakers are expected from Cree, Philips Lumileds, Veeco, Dow Electronic Materials, UCSB, Fraunhofer IZM, Redwood Systems, Intematix, NNCrystal, Cascade Microsystems, KLA-Tencor and more.

MEMS

The Future of MEMS: Solutions for Moving from a Niche to a Mainstream Business; Tuesday, July 12, 10:30am–12:30pm. Speakers from GlobalFoundries, Teledyne Dalsa, Bosch, IMEC, Sand 9 and Yole Développement will participate.

Power ICs

Energy: Opportunities in Smart Power Management for Alternative Energy Applications; Tuesday, July 12, 2:00–4:30pm.  Speakers from Freescale, Yole Développement, Oakridge National Labs, International Rectifier, SemiSouth, and IBM.

Printed/Flexible Electronics

Printed/Flexible Electronics: Beyond R&D to Real Deal Technologies; Thursday, July 14, 10:30am–1:30pm. Speakers from FlexTech Alliance, Novacentrix, Xenon and more will join the event.

Premier sponsors for Semicon West 2011 are: Applied Materials, KLA-Tencor and Verigy. For more information, visit the Semicon West website at www.semiconwest.org.  Visitor registration is free through May 8; onsite registration will be $150.

The ATE Test Technology Technical Council (TTTC) of the IEEE Computer Society will hold its ATE Vision 2020 Conference on July 14 during the Semicon West exposition in San Francisco.

ATE Vision 2020 will focus on test instrumentation, automated test equipment (ATE), and emerging issues in semiconductor test including 3DIC, 450 mm wafers, and new functionality in RF, mixed signal and other applications.

Technical papers are being solicited for consideration in the areas of multiple cores on a die, 3D trends enabled by die-stacking and thru-silicon-vias (TSVs), adaptive test, BIST, and other areas. The conference’s objective will be to explore technology needs as they relate to the cost-of-test, time-to-market, and time-to-yield needs of the industry.

“Test is playing an increasingly critical role in next-generation semiconductors, both as an enabling technology and as a potential gating factor,” said Erik Volkerink, chief technologist of Verigy, and founder and general chair of ATE Vision. “Identifying test technology gaps and needs in critical areas such as 3D chip stacking and 450 mm wafers are essential today to enable tomorrow’s advanced chips.  This year’s program will be designed to compliment SEMICON West’s TechXPOT test sessions with more technical presentations and more interactive sessions with key industry stakeholders.”

The Call for Papers is open until May 15, 2011.  More information, including the Call for Papers, registration and corporate sponsorship information, is available at: www.atevision.com.