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What is Your China Strategy?

Wednesday, September 7th, 2016

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By Dave Lammers, Contributing Editor

Equipment vendors have a lot on their plates now, with memory customers pushing 3D NAND, foundries advancing to the 7 nm node, and 200mm fabs clamoring to come up with hard-to-find tools.

China, which has renewed its investments in displays, packaging, and both 200mm and 300mm front-end fab capacity, is another challenge.

“All the managers in my company are scrambling to adjust their budgets so they can support China. I can tell you people are booking lots of flights to Shanghai,” said one engineer at a major equipment supplier.

Bill McClean, president of IC Insights (Scottsdale, AZ), said China is fast becoming a center for 3D NAND production, as several companies expand production in China. Intel is converting its Dalian, China fab partly to 3D NAND, and Toshiba might very well make a deal in China to build a 3D NAND fab there, he said.

“China could be the 3D NAND capital of the world,” McClean said at The ConFab conference in Las Vegas. While the U.S. government limits exports of leading-edge technologies on national security concerns, 3D NAND relies more on overlay and etch techniques at relaxed (40nm) design rules, he noted.

“Since the 3D NAND makers are not pushing feature sizes, it doesn’t raise red flags like if Chinese companies wanted FinFET technology. That is when the alarms go off,” McClean said.

However, McClean said the 3D NAND market is not immune to the oversupply issues that now face the DRAM makers. “I’ve seen this rodeo before,” McClean said.

China’s domestic IC market is slightly more than $100 billion, McClean said, while chip production in China was about $13 billion last year, representing just under 5 percent of worldwide production (Figure 1).

Figure 1. Source: IC Insights.

The difference between consumption and domestic production, referred to as the delta, is made up by imports. “This 13 percent (from domestic suppliers) drives the Chinese government crazy. Yes, they will close that gap a little bit, but not to the extent that they think,” McClean told The ConFab audience in mid-June.

Robert Maire, who consulted for SMIC on its initial public offering in the United States, spoke at length about China at the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) in Saratoga Springs, N.Y. Amid the mergers and acquisition frenzy of last year, China managed to pull off the acquisitions of CMOS image sensor vendor Omnivision, memory maker ISSI, the RF business of NXP, Pericom Semiconductor, and Mattson Technology. (McClean said he believes that if the Omnivision acquisition were attempted in today’s more China-wary environment that Washington would block the deal).

Maire, principal at Semiconductor Advisors (New York), said China is far behind in its domestic semiconductor production equipment business. “If China has 14nm production capacity, but buys all of its equipment from abroad, it doesn’t really help them that much. China is getting started in equipment, but it has a lot of catching up to do.”

Scott Foster, a partner in market intelligence firm TAP Japan (Tokyo), said China must have an international scope in the equipment sector if it hopes to compete with the likes of Applied, Lam, and other well-established vendors. A few of Japan’s equipment suppliers are succeeding while operating in relatively narrow niches, but overall, competing globally is a challenge for mid-sized Japanese equipment companies. “If this is what is happening to Japanese equipment vendors, what chance do Chinese companies have?” Foster said.

Packaging may prove to be key

Skeptics of China’s prospects might take a long look at China’s success in packaging, an area where China is succeeding, in part by acquisitions of Asia-based companies, notably STATS ChipPAC (Singapore), which was acquired by Jiangsu Changjiang Electronics Technology Co. (JCET) last year. Separately, SMIC and JCET formed a joint venture to focus on chip scale packaging, wafer bumping, and fan-out wafer level packaging. The packaging joint venture is located 90 minutes from Shanghai, said Sonny Hui, senior vice president of worldwide marketing at SMIC.

Jim Walker, the packaging analyst at market research firm Gartner, said China-based packaging is now valued at nearly half (43 percent) of all worldwide packaging value by IDMs and OSATs. While the packaging industry overall is dealing with price pressures, the advent of wafer level packaging, and other forms of multi-chip integration, bodes well for the higher end of the back-end industry.

“As the semiconductor industry matures and Moore’s Law scaling slows, multi-chip integration via packaging is providing system vendors with a faster time-to-market, and a lower-cost means, of solving system-level challenges,” Walker said.

Packaging multiple chips in a module is likely to play a key role in the Internet of Things (IoT) markets, Walker said. Automotive, medical, home, and consumer solutions are all “heavily reliant on packaging,” he said.

Sam Wang, a Gartner analyst who focuses on foundries, pointed out at Semicon West that China’s semiconductor industry faces continued challenges in a hotly contested foundry market. Few China-based foundries have enjoyed the strong growth that SMIC has demonstrated, he said. (SMIC has been “running at very high utilizations, and we are working very hard to solve the problem,” said SMIC’s Hui.)

While SMIC has enjoyed double-digit growth for several years, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total worldwide foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

China-based companies are focusing partly on MEMS and other devices made on 200mm wafers, including analog, sensors, and power. SMIC’s Hui said “most of our customers don’t see much benefit to migrate to 12-inch. 200mm still has a lot of potential; just consider the hundreds of products still made on 180nm technology, which was developed 20 years ago. Many customers still see that as a sweet spot.”

Foster, who has three decades of tech-watching experience from his base in Tokyo, said the 200mm wafer fabs being built in China will make products that “do not need the gigantic scale” required of Intel, TSMC, Samsung and Toshiba. Figure 2, courtesy of SEMI, shows the seventeen 200mm wafer fabs/lines that are expected begin operation in 2015 to 2019. Six of the seventeen will be in China.

Figure 2. Source: SEMI

“After decades of trying, China has found a market-based strategy: building scale and experience from the bottom up. In the long run, this is likely to be far more effective than going out to buy foreign companies,” Foster said.

Display is another area China is counting on. In an Aug. 18 conference call following a strong quarter, Applied Materials chief financial officer Bob Halliday told analysts: “In display, we recorded record orders of $803 million with more than half coming from projects in China.”

The Applied CFO also said, “Just listening to the Chinese government, they’re in this for a long-term and their interest in investing in the semiconductor industry is probably only going to increase.”

Kateeva turns to China funds

China is often lumped together with other Asian nations as a country that has a government-led, me-too, follower mentality. But increasingly, China is either proving innovative itself, or able to quickly adopt innovations from the West.

At the Innovation Forum at Semicon West, Conor Madigan, co-founder of ink jet printer startup Kateeva (Newark, Calif.) spoke about the readiness of Chinese venture capital funds to step in where Silicon Valley-based VCs were overly hesitant. China proved a more receptive place to raise money than the United States, though the early establishment of the M.I.T. spinout did come from U.S. based sources.

After its initial development effort, Kateeva figured it needed more than $100 million to accomplish its goals. After making the rounds to raise funds in the United States without success, Kateeva turned to China, where five different funds eventually became investors.

Asked why Chinese investors were willing to back Kateeva when funds in the United States and other Asian countries were reluctant, Madigan pointed to a confluence of factors.

The Chinese government had identified OLED displays as a focus of its Five Year Plan. The follow-on economic plan further identified inkjet technology as a critical technology. Investors in China favor companies which can provide the equipment for products, such as OLEDs, which have the government’s blessing and financial support. That government support reduced the investment risks in ways that are not readily seen in Japan or the United States, he said.

Madigan had studied OLEDs as an undergraduate at Princeton University, and then studied under an M.I.T. professor who had developed ink jet technology for large formats.

Though an early goal was to use large-format inkjet to deposit the RGB materials in OLEDs, the Kateeva team learned that its YieldJet system could be adapted to solve a more urgent problem: thin film encapsulation (TFE). It “pivoted” on the advice of an early customer, which fortunately already had developed the “ink” which under UV light would form a uniform encapsulation layer for the large OLED substrates required for TVs and other large display applications.

Two display companies in China identified Kateeva as a strategic partner, which allowed Kateeva to raise money from private Chinese VC funds, rather than taking money from regional government funds which might have asked Kateeva to locate its manufacturing operations in their local area.

Madigan also pointed to the tendency of U.S.-based venture capital funds to favor software companies over manufacturing-focused opportunities. As VCs make money in software-related startups, the funds gradually have more partners and investors which favor software because that is what they are familiar with.

VC fund managers with backgrounds in software “want to invest in the space that they understand. In the United States, that often means software, because you pick companies in the space that you understand.”

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Goodbye, EDAC; Hello, ESD Alliance

Friday, April 1st, 2016

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By Jeff Dorsch, Contributing Editor

The Electronic Design Automation Consortium (EDAC) is no more. The industry organization, founded in 1989, is changing its name to the Electronic System Design Alliance, or ESD Alliance.

The name change is being accompanied by an expansion of the organization’s charter. Having taken on semiconductor intellectual property several years ago, the ESD Alliance will also address advanced packaging and embedded software, according to Robert Smith, who took over last year as executive director of EDAC. The ESD Alliance will also welcome service companies that offer design know-how and resources.

The alliance’s launch was marked by an evening event on Wednesday (March 30) at the SEMI headquarters in San Jose, Calif., where the ESD Alliance has its offices. In attendance at the social gathering were several EDAC directors, including Simon Segars, chief executive officer of ARM Holdings; Wally Rhines, chairman and CEO of Mentor Graphics; Lip-Bu Tan, president and CEO of Cadence Design Systems; and Aart de Geus, chairman and co-CEO of Synopsys.

“We’re part of this large ecosystem,” Bob Smith said Wednesday evening, adding, “Semiconductors – they need design.” He recognized by name many of the people involved in EDAC and now the ESD Alliance.

A slide presentation at the event began with “Kingdom of Rain,” by The The, segueing to “Love Shack” by the B-52’s – two songs dating to 1989, the year EDAC was formed. That also was the year Taylor Swift was born, one slide noted.

In 2016, marked musically by Mark Ronson’s “Uptown Funk” in the slide show, the ESD Alliance is taking the place of the EDA Consortium.

Imagining China’s IC Fab Industry in 2035

Friday, January 22nd, 2016

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By Ed Korczynski, Sr. Technical Editor

Editor’s Note:  In Solid State Technology’s November 1995 Asia/Pacific Supplement this editor wrote of the PRC’s status and plans for IC fabs titled “Progress creeps forward”. SEMICON/China 1995 was held in a small hall in Shanghai with 125 exhibitors and 5000 attendees discussing production of just 245M ICs units having happened in the entire country in 1994. Motorola’s Fab17 in Tianjin was planned to be able to yield 360M IC from 200mm wafers.

China has been successfully investing in technology to reach global competitiveness for many decades. Integrated circuit (IC) manufacturing technology is highly strategic for countries, enabling both economically-valuable commercial fabs as well as military power. The Wassenaar Arrangement (WA) between 40-some states has restricted exports to China of “leading” technology with potential “dual-use” by industry and military. Using the terminology of IC fab nodes/generations, WA has typically restricted exports to fab tools capable of processing ICs three nodes behind (n-3) the leading edge of commercial capability (https://en.wikipedia.org/wiki/14_nanometer). In 1995 the leading edge was 0.35 microns, so 1 micron and above was the WA limit. In 2015 the leading edge is 14nm, so 45nm and above is the WA limit, but local capability has already effectively bypassed this restriction.

On February 9, 2015, trade-organization SEMI announced (http://www.semi.org/en/node/54596) the successful lobbying of the U.S. Department of Commerce to declare the export controls on certain etch equipment and technology ineffective, thereby allowing US equipment companies to sell high-volume manufacturing (HVM) tools with capabilities closer to the leading-edge into China. Following years of discussion and negotiations, SEMI had submitted a formal petition for the Commerce Department’s Bureau of Industry and Security (BIS) to examine the foreign availably of anisotropic plasma dry etching equipment, having identified AMEC (amec-inc.com) as providing an indigenous Chinese manufacturing capability. AMEC has announced that it’s tool is being used by Samsung for V-NAND HVM (https://finance.yahoo.com/news/amec-ships-advanced-etch-tool-150000063.html), which is certainly a “leading-edge” product that happens to be made using 45nm node (n-3) design rules.

“The Future is in the Past: Projecting and Plotting the Potential Rate of Growth and Trajectory of the Structural Change of the Chinese Economy for the Next 20 Years” by Jun Zhang et al. from the Institute of World Economics and Politics, Chinese Academy of Social Sciences was first published online in 2015 (DOI: 10.1111/cwe.12098). Thanks to economic growth at an average speed of more than 9.7% annually in China over the past 35 years, it is estimated that today’s China per capital GDP has already reached approximately 23% of the USA. Because of the significant rise in per-capita income over the past 30 years, China has started to see a rapid demographic transition and a gradual rise in labor costs as seen in other high-performing East Asian economies. Benchmarking to the experiences of East Asian high-performing economies from 1950 to 2010, this paper projects potential growth rate of per-capita GDP (adjusted by purchasing power parity) for China at ~6.02% from 2015 to 2035.

The PRC still works with 5-year-plans. Figure 1 shows Deng Xiaoping touring a government-run fab during the 8th 5-year-plan (1991-1995) when central planning of local resources dominated Chinese IC industry. Paramount leader Deng had famously proclaimed, “Poverty is not socialism. To be rich is glorious,” which allowed for private enterprise and different economic classes. As reported by Robert Lawrence Kuhn in 2007’s “What Will China Look Like in 2035” in Bloomberg Business (http://www.bloomberg.com/bw/stories/2007-10-16/what-will-china-look-like-in-2035-businessweek-business-news-stock-market-and-financial-advice), researchers at the Institute of Quantitative & Technical Economics of the Chinese Academy of Social Sciences—the official government think tank housing more than 3,000 scholars and researchers—in 2007 predict that by 2030 China’s economic reform will have been basically completed, such that the major issue will be the “adjustment of interests” among different classes.

Figure 1: Deng Xiaoping is shown Shanghai Belling’s fab by General Manager Lu Dechun during the 8th 5-year-plan (1991-1995). Such small fabs are not globally competitive. (Source: Ed Korczynski)

In 2014, McKinsey&Company published proprietary research (http://www.mckinsey.com/insights/high_tech_telecoms_internet/semiconductors_in_china_brave_new_world_or_same_old_story) that >50% of PCs, and 30-40% of embedded systems contain content designed in China, either directly by mainland companies or emerging from the Chinese labs of global players. Since fewer chip designs will be moving to technologies that are 22nm node and below, low-cost Chinese technology companies will soon be able to address a larger part of the global market. Chinese companies will become more aggressive in pursuing international mergers and acquisitions, to acquire global intellectual property and expertise to be transferred back home.

Figure 2 shows that ICs represent the single greatest import cost for China, so there is great incentive to develop competitive internal fab capacity. The government, recognizing the failure of earlier centrally-planned investment initiatives, now takes a market-based investment approach. The target is a compound annual growth rate (CAGR) for the industry of 20%, with potential financial support from the government of up to 1 trillion renminbi ($170 billion) over the next five to ten years. To avoid the fragmentation issues of the past, the government will focus on creating national champions—a small set of leaders in each critical segment of the semiconductor market (including design, manufacturing, tools, and assembly and test) and a few provinces in which there is the potential to develop industry clusters.

Figure 2: The leading imports to China in 2014, showing that integrated circuits (IC) cost the country more than oil. (Source: China’s customs)

Global Cooperation and Competition

The remaining leading IC manufacturers in the world—Intel, Samsung, and TSMC—are all involved in mainland Chinese fabs. Intel’s Fab68 in Dalian began production of logic chips in 2010. Samsung’s Fab in Xian began production of V-NAND chips in 2014. TSMC has announced it is seeking approval to build a wholly-owned 300mm foundry in Nanjing (http://www.wsj.com/articles/taiwan-semiconductor-plans-to-build-chip-plant-in-china-1449503714), after rival UMC’s has invested in a jointly-owned foundry now being built in Xiamen.

“We do see significant growth, and a big part of that is due to investment by the Chinese government,” said Handel Jones of IC Insights during SEMICON Europa 2015. “Up to US$20B of government subsidy has been earmarked for IC manufacturing investment in China.” Jones forecasts that by 2025 up to 30% of global design starts will be in China, many to be designed by the ~500 fabless companies in China today. Jones estimates the total R&D investment in China today for 5G wireless technology is about US$2B per year, with about one-half of that just by Huawei Technologies Co. Ltd.

Due to the inevitable atomic-limits of Moore’s Law scaling, it is likely that the industry will have reached the end of new nodes in the next 20 years. By then, “trailing-edge” will include everything that is in R&D today, from quantum-devices to CMOS-photonic chips, of which it is highly likely that China will have globally competitive design and manufacturing capability. While today a net importer of ICs, by the year 2035 it seems likely China will be a net exporter of ICs.

—E.K.

Infineon CEO Says Robot Cars Will Drive Semiconductor Demand

Monday, October 12th, 2015

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By Pete Singer, Editor-in-Chief

Infineon’s CEO, Reinhard Ploss, says that the autonomously driven cars of the future will create a large demand for a variety of new semiconductors and sensors. Speaking in a keynote address at SEMI’s Semicon Europa’s Fab Manager’s Forum in Dresden, Germany, Ploss outlined the “drivers” behind the evolution of robot cars and autonomous cars and what we might expect in terms of semiconductor requirements.

Ploss expects a slow evolution to fully autonomous cars, but eventually the experience may be no different than what stepping into an elevator and pushing a button is like today.

Among the many advantages of autonomous driving:

  • Traffic fatalities (1.3 million deaths a year across the globe) can be reduced, as 90% of all accidents are caused by human errors
  • Less traffic congestion: Today, US commuter spend 38 hours/year in traffic jams, which are causing total costs of $121 billion/year
  • Increasing commuter productivity, as time in car can be used for e.g. working (48 min/day per average American)
  • Improved fuel efficiency (up to 50%)
  • Offering mobility for everybody, e.g. disabled, elder or young people
  • Reduction of accidents enables lower insurance rates

Figure 1 shows how automotive safety has evolved over time, and where increased automation is likely to come into play. Ploss said in the five levels of autonomous driving – assisted, partially automated, highly automated and fully automated – everything is still under the control of the driver in the fourth, highly automated, stage.

Figure 1

“Traffic management is a huge opportunity when you have a connected autonomously driving car,” Ploss said. “If you manage traffic to go smoothly at a lower speed, or even the same speed as the trucks, then you have the optimum load for the road.”

“As we move on the, the next big step for automated driving will be on highways,” Ploss said it will take some time to get to fully automated driving. “You need rules on how you can operate. Think about a small Italian village where you have a road which is good for one car. Who goes first?”

An automated car must have the ability for:

  • Recognizing surrounding: roads, traffic participants, traffic signs
  • Speed and direction control: motor, brakes, steering
  • Monitoring of driver

It enables:

  • Assisted/Automated driving
  • Free time while commuting Higher road efficiency (platooning) Automated parking
  • Emergency assist, e.g. braking

Ploss also touched on the advantages and challenges in connecting cars to the internet. “Many believe the autonomous driving car must be a connected car. If we connect to the internet, we can gain more information, and even add capabilities to the car,” he said.

The connected car requires ability for:

  • V2X connections
  • Infotainment, real-time maps, adverts
  • Fleet/network management

It enables:

  • V2X aids automated driving, e.g. road condition, weather info
  • More safety by further ‘looking ahead’
  • Vehicle on demand and ride sharing
  • Traffic flow management
  • Remote servicing, e-Call

Ploss said an automated car will require an “unbelievable” number of sensors. “It will look like a cocoon going around,” Ploss said. Figure 2 shows the number of cameras, radar and Lidar (laser-based radar) we’ll likely see if future generations of cars.

Figure 2

“The car will become a unit with a lot of sensors in order to recognize what is going on. These signals have to be computed, so you also have a very high level of computing power in the car to process this data,” he said.

In addition, the various motors and actuators will be required to apply brakes and steer the car. “When you see something going on the road, you have to take the right action in order to brake, steer away, etc. You have to be able to do it under a certain reliability,” Ploss said.

As in airplanes, there will be some redundancy built in, although Ploss said he believe 2X redundancy will be sufficient (vs 3X in airplanes). “Two times redundancy will be something we see more and more,” he said.

In terms of added semiconductor content, Ploss said a partially automated car will have about $100 in added in semiconductor content (today’s cars already have about $330 in semiconductor content. A highly automated car would have $400 added and a fully automated would have about $550 (Figure 3).

Figure 3

“When you look at the engine, there is a huge need for microcontrollers, sensors and power semiconductors,” Ploss said. “When you go for the hybridization, the pure electrical vehicle, it’s all about semiconductors because the efficiency of the electric drive train is highly dependent on how you are running the engine and how you regain the power when you are braking.”

Ploss added that reducing CO2 emissions was another important aspect of automotive electronic demand. “In today’s combustion engine, there is still a lot of potential to reduce the CO2 emissions. You need an awful lot of sensors and controls in order to run this engine at a very high efficiency. A significant improvement can still be done (for gas and diesel),” he said.

One challenge for the semiconductor industry is to innovate while reducing costs. “We have to go in two directions – innovation for new and better functionality and innovation for cost reduction,” Ploss said. He noted that cost reductions from the pure shrink is “not coming so easy” but sees potential in the Industry 4.0 movement. “When you have a fully connected manufacturing then you can get a lot of data that enables you to learn faster and to manufacture at zero defects,” he said.

Another challenge is that radar employs high frequency GHz electronics (Figure 4). “High frequency brings a lot of specialization,” Ploss said. He said mixed-signal bipolar will first be used, but “as we move to 20nm and 14nm, we will be able to have CMOS-based processes.”

Figure 4

He noted the advantages of silicon carbide for switching applications, citing a 50% loss reduction compared to a silicon solution. This could improve the efficiency of electric vehicles by 3% he noted. “When you think about electric driving, you always think about the last percentage point of gaining efficiency. SiC has a huge potential to enable this. It is a wide bandgap material and you can much smaller size, higher switching frequency, less conduction losses at the higher switching frequency,” he said.

Already, car manufacturers have shown autonomous concept cars, such as the Mercedes Benz F 015.

Managing Dis-Aggregated Data for SiP Yield Ramp

Monday, August 24th, 2015

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By Ed Korczynski, Sr. Technical Editor

In general, there is an accelerating trend toward System-in-Package (SiP) chip designs including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces—primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within and between chips and packages—influence the electrical properties of ICs. In this era, the industry needs to be able to model and control the mechanical and thermal properties of the combined chip-package, and so we need ways to feed data back and forth between designers, chip fabs, and Out-Sourced Assembly and Test (OSAT) companies. With accelerated yield ramps needed for High Volume Manufacturing (HVM) of consumer mobile products, to minimize risk of expensive Work In Progress (WIP) moving through the supply chain a lot of data needs to feed-forward and feedback.

Calvin Cheung, ASE Group Vice President of Business Development & Engineering, discussed these trends in the “Scaling the Walls of Sub-14nm Manufacturing” keynote panel discussion during the recent SEMICON West 2015. “In the old days it used to take 12-18 months to ramp yield, but the product lifetime for mobile chips today can be only 9 months,” reminded Cheung. “In the old days we used to talk about ramping a few thousand chips, while today working with Qualcomm they want to ramp millions of chips quickly. From an OSAT point of view, we pride ourselves on being a virtual arm of the manufacturers and designers,” said Cheung, “but as technology gets more complex and ‘knowledge-base-centric” we see less release of information from foundries. We used to have larger teams in foundries.” Dick James of ChipWorks details the complexity of the SiP used in the Apple Watch in his recent blog post at SemiMD, and documents the details behind the assumption that ASE is the OSAT.

With single-chip System-on-Chip (SoC) designs the ‘final test’ can be at the wafer-level, but with SiP based on chips from multiple vendors the ‘final test’ now must happen at the package-level, and this changes the Design For Test (DFT) work flows. DRAM in a 3D stack (Figure 1) will have an interconnect test and memory Built-In Self-Test (BIST) applied from BIST resident on the logic die connected to the memory stack using Through-Silicon Vias (TSV).

Fig.1: Schematic cross-sections of different 3D System-in-Package (SiP) design types. (Source: Mentor Graphics)

“The test of dice in a package can mostly be just re-used die-level tests based on hierarchical pattern re-targeting which is used in many very large designs today,” said Ron Press, technical marketing director of Silicon Test Solutions, Mentor Graphics, in discussion with SemiMD. “Additional interconnect tests between die would be added using boundary scans at die inputs and outputs, or an equivalent method. We put together 2.5D and 3D methodologies that are in some of the foundry reference flows. It still isn’t certain if specialized tests will be required to monitor for TSV partial failures.”

“Many fabless semiconductor companies today use solutions like scan test diagnosis to identify product-specific yield problems, and these solutions require a combination of test fail data and design data,” explained Geir Edie, Mentor Graphics’ product marketing manager of Silicon Test Solutions. “Getting data from one part of the fabless organization to another can often be more challenging than what one should expect. So, what’s often needed is a set of ‘best practices’ that covers the entire yield learning flow across organizations.”

“We do need a standard for structuring and transmitting test and operations meta-data in a timely fashion between companies in this relatively new dis-aggregated semiconductor world across Fabless, Foundry, OSAT, and OEM,” asserted John Carulli, GLOBALFOUNDRIES’ deputy director of Test Development & Diagnosis, in an exclusive discussion with SemiMD. “Presently the databases are still proprietary – either internal to the company or as part of third-party vendors’ applications.” Most of the test-related vendors and users are supporting development of the new Rich Interactive Test Database (RITdb) data format to replace the Standard Test Data Format (STDF) originally developed by Teradyne.

“The collaboration across the semiconductor ecosystem placed features in RITdb that understand the end-to-end data needs including security/provenance,” explained Carulli. Figure 2 shows that since RITdb is a structured data construct, any data from anywhere in the supply chain could be easily communicated, supported, and scaled regardless of OSAT or Fabless customer test program infrastructure. “If RITdb is truly adopted and some certification system can be placed around it to keep it from diverging, then it provides a standard core to transmit data with known meaning across our dis-aggregated semiconductor world. Another key part is the Test Cell Communication Standard Working Group; when integrated with RITdb, the improved automation and control path would greatly reduce manually communicated understanding of operational practices/issues across companies that impact yield and quality.”

Fig.2: Structure of the Rich Interactive Test Database (RITdb) industry standard, showing how data can move through the supply chain. (Source: Texas Instruments)

Phil Nigh, GLOBALFOUNDRIES Senior Technical Staff, explained to SemiMD that for heterogeneous integration of different chip types the industry has on-chip temperature measurement circuits which can monitor temperature at a given time, but not necessarily identify issues cause by thermal/mechanical stresses. “During production testing, we should detect mechanical/thermal stress ‘failures’ using product testing methods such as IO leakage, chip leakage, and other chip performance measurements such as FMAX,” reminded Nigh.

Model but verify

Metrology tool supplier Nanometrics has unique perspective on the data needs of 3D packages since the company has delivered dozens of tools for TSV metrology to the world. The company’s UniFire 7900 Wafer-Scale Packaging (WSP) Metrology System uses white-light interferometry to measure critical dimensions (CD), overlay, and film thicknesses of TSV, micro-bumps, Re-Distribution Layer (RDL) structures, as well as the co-planarity of Cu bumps/pillars. Robert Fiordalice, Nanometrics’ Vice President of UniFire business group, mentioned to SemiMD in an exclusive interview that new TSV structures certainly bring about new yield loss mechanisms, even if electrical tests show standard results such as ‘partial open.’ Fiordalice said that, “we’ve had a lot of pull to take our TSV metrology tool, and develop a TSV inspection tool to check every via on every wafer.” TSV inspection tools are now in beta-tests at customers.

As reported at 3Dincites, Mentor Graphics showed results at DAC2015 of the use of Calibre 3DSTACK by an OSAT to create a rule file for their Fan-Out Wafer-Level Package (FOWLP) process. This rule file can be used by any designer targeting this package technology at this assembly house, and checks the manufacturing constraints of the package RDL and the connectivity through the package from die-to-die and die-to-BGA. Based on package information including die order, x/y position, rotation and orientation, Calibre 3DSTACK performs checks on the interface geometries between chips connected using bumps, pillars, and TSVs. An assembly design kit provides a standardized process both chip design companies and assembly houses can use to ensure the manufacturability and performance of 3D SiP.

—E.K.

Solid State Technology: August 7-14, 2015

Monday, August 24th, 2015
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Solid State Watch: July 17-23, 2015

Friday, July 24th, 2015
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Solid State Watch: July 10-16, 2015

Friday, July 17th, 2015
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