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International Consortium Sets Up Shop for Advanced Manufacturing Research

Thursday, July 16th, 2015

By Jeff Dorsch, Contributing Editor

Here we go again.

A metropolitan area in the center of the state is putting together a public-private partnership to attract high-tech companies, convincing them to set up shop and create jobs. Part of the attraction is a big public university, engaging in advanced research.

Austin, Texas? No, now it’s Orlando, Florida.

Yes, the home of Walt Disney World, Universal Orlando, and other magnets for visiting families.

About one-third of the jobs in Orlando are in hospitality and tourism, according to Dave Porter, senior vice president of business development for the Orlando Economic Development Commission. The other two-thirds are in a variety of other industries, including energy, military contracting, and telecommunications.

Porter is a veteran of attracting industry to a metropolitan area;  he previously spent a decade working for the Austin Chamber of Commerce, which actively worked with the city and state governments to bring many high-tech employers to the capital of Texas, before joining the Orlando EDC this year.

One of Orlando’s big gets is the International Consortium for Advanced Manufacturing Research (ICAMR), which has a hand in constructing a facility in Osceola County known as the Florida Advanced Manufacturing Research Center, or FAMRC, in cooperation with the University of Central Florida. Osceola County has chipped in nearly $138 million for building the FAMRC, which is scheduled to open in 2016 and will house ICAMR and other parties, especially those interested in the development and manufacturing of smart sensors.

UCF kicked in $17 million of funding, while other Florida universities contributed toward building the center, and the State of Florida may invest in the facility, as well.

ICAMR is modeled after Sematech, the semiconductor manufacturing technology consortium once based in Austin, which helped attract many chip-related businesses to Central Texas over 25 years, according to Porter.

“Orlando is well known, but poorly understood,” he says. “It’s the youngest city in Florida.” The metro area has a labor pool of more than 1.2 million people, with 500,000-plus students within a 100-mile radius.

Sensors are at the heart of the grand scheme known as the Internet of Things. Whether IoT takes off or not, there will be greater demand for more sophisticated sensing technology in the years to come, and ICAMR wants to help lead that field. Porter says business leaders and politicians are always talking about “bringing manufacturing back to the U.S.,” and ICAMR/FAMRC could help that.

Safe CMP slurries for future IC materials

Wednesday, April 29th, 2015


By Ed Korczynski, Sr. Technical Editor, Solid State Technology

New chemical-mechanical planarization (CMP) processes for new materials planned to be used in building future IC devices are now in research and development (R&D). Early data on process trade-offs as well as on environmental, health, and safety (EHS) aspects were presented at the CMP Users Group (of the Northern California Chapter of The American Vacuum Society) meeting, held in Albany, New York on April 16 of this year in collaboration with the College of Nanoscale Science and Engineering (CNSE) SUNY Polytechnic Institute and SEMATECH.

Mike Corbett, principle with Linx Consulting, presented his company’s forecast on CMP consumable materials growth for both logic and memory. “We’re no longer in the era of 2D scaling. Right now the semiconductor industry is scaling through the use of novel materials and 3D structures. It started with memory cells going vertical for storage structures. All of these technologies rely on CMP as a key enabler:  for 3D NAND there’ll be new tungsten, TSV need new copper, and transistors need CMP for high-k/metal-gate processing.”

Corbett estimates the current global market for pre-interconnect CMP consumables—slurries, pads, and conditioning disks—at >$US1.5B annually with steady growth on the horizon. While the fabricated cost/wafer at the leading edge is estimated to increase by 25-60% when moving to the next leading-edge node, the cost of CMP consumables should only increase by 12-14%. The Figure shows the specific example of 2D NAND wafer cost increasing by 60% in moving from 20nm- to 16nm-node production, while the fab’s CMP costs increase just ~12%. Until the IC HVM industry begins using materials other than Si/SiGe for transistor channels it seems that CMP costs will be well controlled.

Fig.1: Cost modeling shows that 2D NAND memory fab cost/wafer increases 65% when moving from 20nm- to 16nm-node production, while the cost of CMP consumable materials may increase only 12% for that fab. (Source: Linx Consulting)

Alternate channel materials toxicity in CMP

With alternate channel materials on the horizon for future logic transistor, III-V materials such as gallium-arsenide (GaAs), gallium-indium-phosphide (GaInP), and indium-phosphide (InP) are now in R&D which leads to questions regarding direct process costs as well as indirect EHS costs. Hsi-An Kwong, SEMATECH EHS Program Manager, provided an important overview of these issues in his presentation on “Out-gassing from III-V Wafer Processing.” Much of the concern involves the possible reaction and release of toxic hydrides such as arsine, and phosphine. SEMATECH worked with imec to monitor hydrides produced during CMP processes for high-mobility compound semiconductors.

With 1.5% H2O2 in a relatively low-pH slurry, phosphine was measured on the tool from InP but not from GaInP. Use of higher pH with the same 1.5% H2O2 resulted in no phosphine from InP, but arsine outgassing from GaAs. Use of the highest pH resulted in no outgassing of phosphine or arsine. “When we develop the CMP process, particularly when moving to HVM we need to study the layers on the wafer and the slurry used to evaluate if outgassing will be an issue,” explained Kwong. “FTIR is the metrology instrument needed to be able to distinguish between different evolved hydride species.” HVM fab personnel working on or near CMP tools would have to wear personal breathing apparatus if processes evolve hydrides; for example, the SEMATECH/CNSE continuous exposure EHS specification allows a maximum human exposure level of just 1.25 ppb arsine.

In technical sessions at SEMICON West in San Francisco last year, SEMATECH presented on EHS issues with CMP of III-V materials in high-volume manufacturing (HVM). Toxic hydride gases evolve during direct CMP and during over-polish of contacts. Metallic arsenic could potentially build-up on tools over time, and will have to be treated in CMP waste water. To minimize risks, dedicated CMP tools will likely be needed for R&D and for HVM.

Solid State Watch: November 25-December 4, 2014

Monday, December 8th, 2014
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Solid State Watch: November 7-14, 2014

Thursday, November 20th, 2014
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Research Alert: June 17, 2014

Tuesday, June 17th, 2014

Research on high-performance field-effect transistors to be presented at 2014 VLSI Symposium

A team of researchers from Purdue University, SEMATECH and SUNY College of Nanoscale Science and Engineering will present today at the 2014 Symposium on VLSI Technology on their work involving high-performance molybdenum disulfide (MoS2) field-effect transistors (FETs).

The team’s research is an important milestone for the realization of the ultra-scaled low-power 2D MoS2 FETs and the advancement of photonic and electronic devices based on transition metal dichalcogenide (TMD) materials such as solar cells, phototransistors and low-power logic FETs. The research is supported by Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductors and related technologies, and SEMATECH.

As part of the research, the team leveraged MoS2, which has been studied closely in recent years by the semiconductor industry due to its potential applications in electrical and optical devices. However, high contact resistance value limits the device performance of MoS2 FETs significantly. One method to resolve this issue is to dope the MoS2 film, but doping the atomically thin film is nontrivial and requires a simple and reliable process technique. The technique used by the research team provides an effective and straightforward way to dope the MoS2 film with chloride-based chemical doping and significantly reduces the contact resistance.

“Compared with other chemical doping materials such as PEI (polyethylene imine) and potassium, our doping technology shows superior transistor performance including higher drive current, higher on/off current ratio and lower contact resistance,” said Professor Peide Ye, College of Engineering, Purdue University.

In order to obtain high-performance FETs, three parts of the device should be carefully engineered: semiconductor channel (carrier density and its mobility); semiconductor-oxide interface; and semiconductor-metal contact. This research is particularly aimed at eliminating the last major roadblock toward demonstration of high-performance MoS2 FETs, namely, high contact resistance.

The MoS2 FETs using the doping technique, which were fabricated at Purdue University, can be reproduced now in a semiconductor manufacturing environment and show the best electrical performance among all the reported TMD-based FETs. The contact resistance (0.5 kΩ·μm) with the doping technique is 10 times lower than the controlled samples. The drive current (460 μA/μm) is twice of the best value in previous literature.

“Due to recent advances such as the research being presented at the VLSI symposium, 2D materials are gaining a lot of attention in the semiconductor industry,” said Satyavolu Papa Rao, director of Process Technology at SEMATECH. “The collaborative effort among world-class researchers and engineers from this team is a prime example of how consortium-university-industry partnerships further enable the development of cutting-edge process techniques.”

“Improved contacts are always desirable for all electronic and optical devices,” said Kwok Ng, Senior Director of Device Sciences at SRC. “The doping technique presented by this research team provides a valid way to achieve low contact resistance for MoS2 as well as other TMD materials.”

UC Santa Barbara researchers introduce highest performing III-V metal-oxide semiconductor FET

Researchers from the University of California, Santa Barbara (UCSB) will introduce today the highest performing III-V metal-oxide semiconductor (MOS) field-effect transistors (FETs) at the 2014 Symposium on VLSI Technology.

The UCSB research promises to help deliver higher semiconductor performance at lower power consumption levels for next-generation, high-performance servers. The research is supported by the Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductors and related technologies.

The UCSB team’s III-V MOSFETs, for the first time in the industry, exhibit on-current, off-current and operating voltage comparable to or exceeding production silicon devices — while being constructed at small dimensions relevant to the VLSI (very-large-scale integration) industry.

For the past decade, III-V MOSFETs have been widely studied by a large number of research groups, but no research group had reported a III-V MOSFET with a performance equal to, let alone surpassing, that of a silicon MOSFET of similar size. In particular, UCSB’s transistors possess 25 nanometer (nm) gate lengths, an on-current of 0.5mA and off-current of 100nA per micron of transistor width and require only 0.5 volt to operate.

“The goal in developing new transistors is to reach or beat performance goals while making the transistor smaller—it is no good getting high performance in a big transistor,” said Mark Rodwell, professor of Electrical and Computer Engineering, UCSB. “In time, the UCSB III-V MOSFET should perform significantly better than silicon FinFETs of equal size.”

To reach this breakthrough in performance, the UCSB team made three key improvements to the III-V MOSFET structure. First, the transistors use extremely thin semiconductor channels, some 2.5nm (17 atoms) thick, with the semiconductor being indium arsenide (InAs). Making such thin layers improves the on-current and reduces the off-current. These ultra-thin layers were developed by UCSB Ph.D student Cheng-Ying Huang under the guidance of Professor Arthur Gossard.

Next, the UCSB transistors use very-high-quality gate insulators, dielectrics between the gate electrode and the semiconductor. These layers are a stack of alumina (Al2O3, on InAs) and zirconia (ZrO2), and have a very high capacitance density. This means that when the transistor is turned on, a large density of electrons can be induced into the semiconductor channel. Development of these dielectric layers was led by UCSB Ph.D student Varista Chobpattana under the guidance of Professor Susanne Stemmer.

Third, the UCSB transistors use a vertical spacer layer design. This vertical spacer more smoothly distributes the field within the transistor, avoiding band-to-band tunneling. As with the very thin InAs channel design, the vertical spacer makes the leakage currents smaller, allowing the transistor’s off-current to rival that of silicon MOSFETs. The overall design, construction and testing of the transistor was led by UCSB Ph.D student Sanghoon Lee under Rodwell’s guidance.

“The UCSB team’s result goes a long way toward helping the industry address more efficient computing capabilities, with higher performance but lower voltage and energy consumption,” said Kwok Ng, Senior Director of Device Sciences at SRC. “This research is another critical step in helping ensure the continuation of Moore’s Law — the scaling of electronic components.”

The Week in Review: June 13, 2014

Friday, June 13th, 2014

According to the IMF and predictions by many other market research firms, 2014 and 2015 are expected to be growth years, comparable to or even better than the past few years.

Worldwide shipments of flat-panel televisions rose convincingly in the first quarter of 2014 compared to the same period last year, a stronger-than-expected showing that puts the industry on firm footing for the year, according to a new report from IHS.

Researchers from the University of California, Santa Barbara (UCSB) introduced the highest performing III-V metal-oxide semiconductor (MOS) field-effect transistors (FETs) at the 2014 Symposium on VLSI Technology.

A team of researchers from Purdue University, SEMATECH and SUNY College of Nanoscale Science and Engineering presented at the 2014 Symposium on VLSI Technology on their work involving high-performance molybdenum disulfide field-effect transistors.

Crystal IS, a developer of high-performance ultraviolet (UVC) LEDs, this week announced availability of Optan. The first commercial semiconductor based on native Aluminum Nitride (AIN) substrates, Optan provides a unique technology platform for increased detection sensitivity.

Dow Corning established a higher industry standard for silicon carbide (SiC) crystal quality by introducing a product grading structure that specifies ground-breaking new tolerances on killer device defects, such as micropipe dislocations (MPD), threading screw dislocations (TSD) and basal plane dislocations (BPD).

The Week in Review: May 16, 2014

Friday, May 16th, 2014

On May 14, 2014, it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.

Applied Materials announced its Applied Endura Volta CVD Cobalt system, the only tool capable of encapsulating copper interconnects in logic chips beyond the 28nm node by depositing precise, thin cobalt films.. The introduction of cobalt as a superior metal encapsulation film marks the most significant materials change to the interconnect in over 15 years.

Dow Corning introduced Dow Corning EE-3200 Low-Stress Silicone Encapsulant – the latest addition to its portfolio of advanced solutions designed to expand performance and durability of solar micro-inverters, power optimizers and other high value components.

Element Six today announced that its Gallium Nitride (GaN)-on-Diamond wafers have been proven by Raytheon Company to significantly outperform industry standard Gallium Nitride-on-Silicon Carbide (GaN-on-SiC) in RF devices.

A newly finalized Department of Defense (DoD) rule reduces the risk of counterfeit semiconductor products being used by our military by implementing needed safeguards in the procurement of semiconductors and other electronic parts.

Noel Technologies, a Silicon Valley specialty foundry offering process development and substrate fabrication, is now offering services for nanoimprint technology that reduce the costs of the nanoimprint stamps.

SEMATECH announced that researchers have reported progress which could significantly improve resist sensitivity by incorporating metal oxide nanoparticles for extreme ultraviolet (EUV) lithography, bringing the technology another step toward enabling the development of high performance resists required to enable EUV for high-volume manufacturing (HVM).

Mentor Graphics Corporation this week announced the new MicReD Industrial Power Tester 1500A for power cycling and thermal testing of electronics components to simulate and measure lifetime performance. The MicReD Industrial Power Tester 1500A tests the reliability of power electronic components that are increasingly used in industries such as automotive and transportation including hybrid and electrical vehicles and trains, power generation and converters, and renewable energy applications such as wind turbines.  It is the only commercially available thermal testing product that combines both power cycling and thermal transient measurements with structure function analysis while providing data for real-time failure-cause diagnostics.

Research Alert: May 13, 2014

Tuesday, May 13th, 2014

SRC and UC Berkeley pursue a more cost effective approach to 3D integration

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

The research focuses on integrating extra layers of transistors on a vertically integrated 3D monolithic chip using printing of semiconductor “inks” as compared to the current method of chip-stacking through 3D interconnect solutions.

The new process technology could help semiconductor manufacturers develop smaller and more versatile components that are less expensive and higher performing by enabling cost-effective integration of additional capabilities such as processing, memory, sensing and display. The low-temperature process is also compatible with polymer substrates, enabling potential new applications in wearable electronics and packaging.

To fabricate such devices, new material and process methodologies are needed for depositing nanoparticles for semiconductors, dielectrics and conductors. The research is particularly focused on solution-based processing due its low temperature compatibility with CMOS metallization as well as the potential for lower cost manufacturing.

“Initial results from the Berkeley team show that reasonably high performance can be obtained from ink-jet printed devices with process temperatures that are compatible with post-CMOS metallization, thus enabling a new route to monolithic 3D integration,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

SEMATECH reports higher dose sensitivity progress in novel photoresist platforms

SEMATECH announced today that researchers have reported progress which could significantly improve resist sensitivity by incorporating metal oxide nanoparticles for extreme ultraviolet (EUV) lithography, bringing the technology another step toward enabling the development of high performance resists required to enable EUV for high-volume manufacturing (HVM).

SEMATECH engineers, in association with scientists from Cornell University, have demonstrated significantly higher dose sensitivity by incorporating metal oxide nanoparticles, with a resolution dose that is less than one fifth of that normally used with EUV scanner throughput calculations. These significant advances are critical in moving forward the infrastructure that will prepare EUV lithography for HVM at 20nm half-pitch.

“These resist platforms have the potential to significantly relax the EUV source power requirements to enable high-throughput EUV lithography—which has been the most critical barrier to enabling EUV to enter high-volume manufacturing,” said Michael Lercel, SEMATECH’s senior director of Technology. “With these disruptive photoresist platforms, SEMATECH is working toward enabling breakthrough high performance resists that move forward the infrastructure that will prepare EUV for cost-effective manufacturing.”

Taking the lead out of a promising solar cell

Northwestern University researchers are the first to develop a new solar cell with good efficiency that uses tin instead of lead perovskite as the harvester of light. The low-cost, environmentally friendly solar cell can be made easily using “bench” chemistry — no fancy equipment or hazardous materials.

“This is a breakthrough in taking the lead out of a very promising type of solar cell, called a perovskite,” said Mercouri G. Kanatzidis, an inorganic chemist with expertise in dealing with tin. “Tin is a very viable material, and we have shown the material does work as an efficient solar cell.”

Kanatzidis, who led the research, is the Charles E. and Emma H. Morrison Professor of Chemistry in the Weinberg College of Arts and Sciences.

The new solar cell uses a structure called a perovskite but with tin instead of lead as the light-absorbing material. Lead perovskite has achieved 15 percent efficiency, and tin perovskite should be able to match — and possibly surpass — that. Perovskite solar cells are being touted as the “next big thing in photovoltaics” and have reenergized the field.

Kanatzidis developed, synthesized and analyzed the material. He then turned to Northwestern collaborator and nanoscientist Robert P. H. Chang to help him engineer a solar cell that worked well.

“Our tin-based perovskite layer acts as an efficient sunlight absorber that is sandwiched between two electric charge transport layers for conducting electricity to the outside world,” said Chang, a professor of materials science and engineering at the McCormick School of Engineering and Applied Science.

Their solid-state tin solar cell has an efficiency of just below 6 percent, which is a very good starting point, Kanatzidis said. Two things make the material special: it can absorb most of the visible light spectrum, and the perovskite salt can be dissolved, and it will reform upon solvent removal without heating.

“Other scientists will see what we have done and improve on our methods,” Kanatzidis said. “There is no reason this new material can’t reach an efficiency better than 15 percent, which is what the lead perovskite solar cell offers. Tin and lead are in the same group in the periodic table, so we expect similar results.”

Perovskite solar cells have only been around — and only in the lab — since 2008. In 2012, Kanatzidis and Chang reported the new tin perovskite solar cell with promises of higher efficiency and lower fabrication costs while being environmentally safe.

“Solar energy is free and is the only energy that is sustainable forever,” Kanatzidis said. “If we know how to harvest this energy in an efficient way we can raise our standard of living and help preserve the environment.”

The solid-state tin solar cell is a sandwich of five layers, with each layer contributing something important. Being inorganic chemists, Kanatzidis and his postdoctoral fellows Feng Hao and Constantinos Stoumpos knew how to handle troublesome tin, specifically methylammonium tin iodide, which oxidizes when in contact with air.

The first layer is electrically conducting glass, which allows sunlight to enter the cell. Titanium dioxide is the next layer, deposited onto the glass. Together the two act as the electric front contact of the solar cell.

Next, the tin perovskite — the light absorbing layer — is deposited. This is done in a nitrogen glove box — the bench chemistry is done in this protected environment to avoid oxidation.

On top of that is the hole transport layer, which is essential to close the electrical circuit and obtain a functional cell. This required Kanatzidis and his colleagues to find the right chemicals so as not to destroy the tin underneath. They determined what the best chemicals were — a substituted pyridine molecule — by understanding the reactivity of the perovskite structure. This layer also is deposited in the glove box. The solar cell is then sealed and can be taken out into the air.

A thin layer of gold caps off the solar-cell sandwich. This layer is the back contact electrode of the solar cell. The entire device, with all five layers, is about one to two microns thick.

The researchers then tested the device under simulated full sunlight and recorded a power conversion efficiency of 5.73 percent.

Solid State Watch: May 2-8, 2014

Friday, May 9th, 2014
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The Week in Review: May 9, 2014

Friday, May 9th, 2014

SEMATECH announced this week that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet lithography, pushing the technology another significant step toward readiness for high-volume manufacturing.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

GlobalFoundries this week introduced an optimized semiconductor manufacturing platform aimed specifically at meeting the stringent and evolving needs of the automotive industry.

Peregrine Semiconductor announced shipment of the first RF switches built on the UltraCMOS 10 technology platform.

BASF inaugurated a new Electronic Materials Sampling and Development facility in Hillsboro, Oregon. The new facility is a strategic step towards establishing a North American footprint to supply materials for semiconductor manufacturing applications related to the electronics industry.

Veeco Instruments Inc. has appointed Shubham Maheshwari, 42, as its new Executive Vice President, Finance and Chief Financial Officer (CFO). Mr. Maheshwari replaces David D. Glass, who announced his retirement from Veeco last December.

Avago Technologies Limited and LSI Corporation announced Avago has completed its acquisition of LSI Corporation for $11.15 per share in an all-cash transaction valued at approximately $6.6 billion.

Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, this week introduced a new parallel Flash memory device.

The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $78.47 billion during the first quarter of 2014, marking the industry’s highest-ever first quarter sales.

Qualcomm elected Harish Manwani to board of directors. Manwani brings more than 35 years of consumer product and global management experience, and currently serves as the Chief Operating Officer at Unilever PLC.

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