By Mark LaPedus
Directed self-assembly (DSA) is making progress for potential use in semiconductor production, but the industry must make some major advances in a sometimes forgotten and unsung segment—materials.

DSA is a complementary patterning technology that makes use of block copolymer materials to enable fine pitches in chip designs. But today’s block copolymers based on poly (MMA-co-styrene), or better known as PS-b-PMMA materials, do not scale beyond 11nm.

To bring DSA from the lab to the fab, Arkema, AZ, Dow, IBM, JSR, SEH, TOK and others are separately developing next-generation DSA copolymers that promise to scale beyond 11nm. But for the most part, the commercial vendors are keeping their R&D work close to the vest.

To date, most of the research in the public domain has originated at universities. Given that the universities provide a clue of what’s coming down the pike, there are several DSA materials candidates on the table, including high chi copolymers, blended compounds, and even one based on simple sugar.

Each approach, which is still in R&D, consists of complex chemical compounds that resemble a mix of letters in a bowl of alphabet soup. The candidates have various trade-offs, but there is no clear leader in the next-generation copolymer race right now.

“The field is much more wide open than it was for the first generation PS-b-PMMA materials,” said Ralph Dammel, chief technology officer for AZ Electronic Materials, a supplier of materials for DSA and other applications. “There certainly are a number of possible high chi materials. It may be that one single high chi polymer technology will evolve, or several ones may co-exist, possibly for different applications. It is too early to say.”

DSA to the rescue?
DSA is one of several lithographic options for chip production. In the current lithography landscape, chipmakers are expected to use 193nm immersion and double patterning at 20nm. Then, at 14nm and 10nm, the industry would like to insert extreme ultraviolet (EUV) lithography. If EUV misses those windows, the industry will extend 193nm immersion and move to a more complex multi-patterning scheme.

The wild card is DSA, which is still in R&D. Technically, DSA is a complementary scheme. When used in conjunction with a pre-pattern that directs the orientation for patterning, DSA is said to reduce the pitch of the final printed structure. Used in conjunction with 193nm immersion, DSA could extend 193nm lithography beyond 10nm, eliminate expensive multi-patterning steps and push out EUV.

In the lab, DSA has demonstrated the ability to devise features down to 5nm. The likely insertion point for DSA is the 10nm node, said Moshe Preil, manager of emerging lithography and tools at GlobalFoundries. “If it was only about the chemistry, we would know how to implement DSA at 14nm,” Preil said. “We still don’t know how to design a chip using DSA.”

Design enablement and defectivity are among the challenges with DSA. And to put DSA in a production fab, chipmakers must make some complex choices. First, there are two main types of DSA methods: graphoepitaxy and chemical epitaxy. In chemical epitaxy, self-assembly is guided by a sparse chemical pre-pattern. Graphoepitaxy is based on a topographical pre-pattern.

Chipmakers must come up with the right DSA materials, which is also a challenge. “The design of high chi block copolymers has a number of pitfalls. It is not easy, but there has already been a lot of progress, enough that we can say there will not be a technical issue with availability of high chi materials for <10nm patterning,” said AZ’s Dammel.

A polymer is a molecule that consists of repeating structural units. A copolymer is a polymer compound derived from two or more structural units. Block copolymers consist of dissimilar structural units or chains linked by covalent bonds.

In DSA, the dissimilar units are able to phase separate into distinct domains and then self-assemble into controllable dimensions. The trouble is today’s block copolymers based on PS-b-PMMA materials have a chi factor of about 0.04. If the chi N factor is less than 10.5 in certain mixes, the blocks will not phase separate. N denotes the degree of polymerization, while chi represents the interaction parameter.

So, the industry must find a suitable material that scales. In this area, there are two basic approaches: organic-organic versus organic-inorganic. Academia has focused on organic-organic compounds, while commercial vendors are narrowing their options down to organic-inorganic materials, said Mark Slezak, vice president of sales and technology at JSR Micro, the U.S. sales arm for JSR.

IBM and JSR have been co-developing a technology that blends a copolymer and organosilicate material. This blended approach can scale and consists of fewer process steps using sidewall image transfer technology, according to JSR and IBM. “This has opened Pandora’s Box,” said Yoshi Hishiro, director of R&D at JSR Micro. “The blended approach enables several possibilities. The chi for the blended system can be defined.”

IBM also is working on other solutions, including non-blended copolymers with AZ Electronic Materials. “Both polymer blends and block copolymers phase separate on annealing. Polymer blends are very easy to make, and they also are easier to process. Usually, they require lower annealing temperatures and it is easier to achieve short annealing times,” AZ’s Dammel said. “But the blended approaches are restricted to 2x frequency duplication. For 3x or more, one has to use the longer range self-assembly capability of block copolymers.”

Frequency duplication is key for DSA. “Let’s say we have 20nm lines with 160nm pitch. Let’s say we also use a copolymer with a natural period L0 of 40nm. After the process, we have 20nm equal lines and spaces, or 4x the lines that were there before. That’s what is called 4x frequency multiplication,” Dammel explained.

Today’s block copolymers have scaling limitations. “So, one needs to make block copolymers with higher chi factors. One problem is that some types of block copolymers with high chis are difficult to phase separate by thermal annealing. The blocks repel each other so strongly that they have a hard time moving past each other. One has to use solvent vapor to soften them enough to get them to phase separate.” Dammel explained.

The problem is that solvent annealing may not be the right solution, because the technology is incompatible with today’s semiconductor manufacturing processes, he added.

The contenders
At present, there are several promising next-generation, high chi copolymer candidates on the table. “All of them have their strong attributes. They also have their shortcomings,” said Christopher Ober, professor in the Department of Materials Science and Engineering at Cornell University.

For years, Cornell has been developing block copolymers. The other pioneers in the DSA materials field include the University of Massachusetts Amherst (UMASS) and the University of Wisconsin.

In a more recent effort, Intel and the University of Queensland in Australia described a diblock copolymer, based on poly(styrene)-b-poly(DL-lactide) or PS-b-PDLA materials. Using a graphoepitaxy process flow with 4x frequency multiplication, the entities demonstrated 8nm lines and spaces with PS-b-PDLA materials.

“The new high chi systems such as p(S-b-DLA) have even better selectivity than p(S-b-MMA),” Dammel said. “The p(S-b-DLA) system also has much lower annealing temperatures than the p(S-b-MMA) system.”

In another effort, the Massachusetts Institute of Technology (MIT) recently disclosed that self-assembly can form 3D structures. MIT used a poly (styreneb-dimethylsiloxane) or PS-b-PDMS block copolymer. PS-b-PDMS has a chi factor of 0.27. MIT also HAS devised higher chi materials based on poly(2-vinylpyridine-b-dimethylsiloxane) or P2VP-PDMS.

“I would not treat the chi parameter as the only figure of merit,” said Caroline Ross, professor in the Department of Materials Science and Engineering at MIT. “Chi is one consideration, but there are others that are relevant to microphase separation, such as the molecular weight, volume fraction, surface energy of the blocks and relative etch resistance.”

Hitachi and CNRS-CEA/LETI also are pursuing PS-b-PDMS. In a separate effort, CNRS and the University of Texas at Austin have recently described the synthesis and self-assembly of block copolymers “composed of naturally derived oligosaccharides” or sugar.

These block copolymers enable 5nm feature sizes. “However, that system can never be annealed thermally,” said C. Grant Willson, professor of chemical engineering at the University of Texas at Austin. “It has to be annealed with a solvent. I personally do not think that long solvent annealing processes are compatible with semiconductor manufacturing.”

Willson and his associates are working on other materials. “We have designed a new block copolymer that has all of the attributes of the sugar polymer, but can be annealed thermally with a top coat. This new material looks very promising,” he added.

Meanwhile, UMASS and others are developing copolymers based on polystyrene-block-poly(ethylene oxide) or PS-b-PEO materials. UMASS is also exploring tri-block copolymers based on poly(ethylene oxide) or PEO-b-PPO-b-PEO materials.

In another effort, Pohang University of Science and Technology, Tokyo Institute of Technology, and the University of Wisconsin-Madison, Wisconsin recently described an organic-inorganic diblock copolymer, dubbed poly(styrene-b-methacrylate) or PS-b-PMAPOSS.

Cornell has been developing the concept of orthogonal processing of block copolymers. By using a semi-flourinated photoresist/solvent system, researchers are able to selectively pattern or lift-off and then recover the block copolymer film intact. This relates to “orthogonal lithography,” a new patterning process for organic semiconductors. The process is based on a novel photoresist that is compatible with sensitive organic systems. The specially designed photoresist is composed of polymeric or molecular glass that enables the use of fluorous solvents, thus not damaging the organic material while enabling pattern formation.

By Mark LaPedus, SemiMD senior editor

It’s been a topsy-turvy period for silicon wafer makers. 2010 was strong for vendors, but 2011 has been slow and disappointing. And now, silicon wafer makers are seeing a slowdown heading into 2012.

It’s a double-whammy for vendors, which are experiencing a downturn in both of their key markets: semiconductors and solar. A slowdown in power semiconductors and microcontrollers has caused a cutback in 200mm silicon wafer production, according to Japan’s Sumco Corp., the world’s second largest silicon wafer maker, behind Shin-Etsu Handotai (SEH).

And the gloomy forecast for PCs has hit 300mm production, prompting some silicon wafer makers to rush into the cost-cutting mode. MEMC Electronic Materials Inc. has recently announced a layoff and cut production in select plants. Rival Siltronic, Wacker Chemie AG’s silicon wafer division, plans to close its production site in Japan.

The other two major silicon wafer makers — SEH and Sumco — have recently announced lackluster results.

The semiconductor industry is in the midst of a “cyclical downturn,’’ said Ahmad Chatila, MEMC’s chief executive, in a recent conference call, adding that solar faces “significant challenges,” as “wafer and module prices are falling rapidly.”

“In early 2011, semi wafer demand was forecast to grow at an 8 percent level,” said Richard Winegarner, an analyst at Sage Concepts, a research firm. “Lately, that has been reduced to about 3 percent. I usually wait until ISS to hear the 2012 forecasts, but early pronouncements have been in the 3 percent range.”

The analyst was referring to SEMI’s upcoming Industry Strategy Symposium (ISS) event, which is in Half Moon Bay, Calif.

Over the years, silicon wafers have expanded by putting new plants in various markets. But more recently, vendors are consolidating their plants. “I think that most industry restructuring moves are being driven by cost cutting pressures,” Winegarner said. “In the old days, wafer companies placed their facilities near to their customers so as to provide custom service. Now that wafers are more of a commodity, consolidating manufacturing into large specialty factories to cut costs seems to be the trend.”

Another trend is a push into solar. For example, besides selling silicon wafers for semiconductors, MEMC has made polysilicon materials for solar cells. Then, in 2009, it took a major step into the solar business by acquiring Sun Edison LLC, a developer of solar power projects. Last year, MEMC acquired Solaicx, a developer of crystal growth manufacturing technology for silicon wafers in the photovoltaic solar industry.

U.S.-based MEMC made these acquisitions before the current and major downturn in the solar business, which appears to be dragging the company down. Earlier this month, the company announced a layoff and other cost cutting actions. MEMC’s Chatila blamed the problems on the downturn in the solar and semiconductor business, adding the moves were “not a retraction” within its business.

As part of the announcement, the company will reduce its total workforce by over 1,300 persons worldwide, approximately 20 percent of the company’s employees. Of the reductions, approximately 250 positions are in the United States, and an estimated 41 percent are in the semiconductor materials segment and 47 percent are in the solar materials segment.

The company also intends to idle its Merano, Italy polysilicon facility, up to 6,000 metric tons of annual capacity, and may close the plant. The company will reduce production capacity at its Portland, Oregon crystal facility. And it will limit the ramp of the Kuching, Malaysia wafering facility to 300MW. In total, it expects to incur total charges of approximately $700 million, of which approximately $520 million is non-cash.

Also earlier this month, Germany’s Siltronic, Wacker’s silicon wafer division, intends to streamline its 200mm wafer production capacities. As a result, Siltronic plans to close its production site in Hikari, Japan, by mid-2012.

Hikari’s production volumes will be transferred to Siltronic’s existing 200mm wafer plants in Singapore and Portland, Ore. The planned closure is expected to involve expenses of some €70 million ($91.8 million).

Currently, Siltronic is producing at its Hikari site wafers for the semiconductor industry as well as monocrystalline silicon ingots, employing a staff of some 500. The company will continue to employ a local sales force and application engineering unit in Japan. It plans to offer its Hikari staff severance packages as well as consultancy and support in their search for new employment outside the company.

In Japan, it was a tough year for SEH, the world’s largest silicon wafer maker. The company’s 300mm silicon wafer plant in Shirakawa, Japan was temporarily suspended in March following the major earthquake in that nation.

Sales for the SEH’s silicon wafer unit were 124.2 billion yen ($1.595 billion) in the first half of its fiscal year, down 12.8 percent from a year ago, according to the company’s results, which were reported in October. Operating income was 21 billion yen ($269.9 million) for the period, up 0.4 percent.

Earlier this month, Sumco reported sales of 62.3 billion yen ($800.9 million) for the third quarter, down 6.9 percent from the previous quarter. It reported a net loss of 800 million yen in the period, compared to a 600 million yen profit in the previous quarter.

Sumco also cut its sales forecast for the second half of its fiscal year due to a decrease in demand for 200mm wafers. The company also sees a temporary drop in demand for 300mm wafers amid a slowdown in the PC market. The PC market has been impacted by the flood in Thailand, which has hit the disk drive supply chain.

By David Lammers

Now that Intel Corp. and TSMC have publicly committed to finFETs at the 22nm and 14nm nodes, respectively, attention is turning to what the next moves will be from the ultra-thin-body SOI camp.

At the recent Symposium on VLSI Technology, held in Kyoto, Japan, a 22nm technology platform based on extremely thin SOI substrates was presented, with a 25 percent improvement in ring oscillator speed compared with a 28nm bulk transistor. The presentation from a team based in Albany, N.Y. (IBM, STMicro, GlobalFoundries, Renesas, and Toshiba) included analog devices and SRAMs with a 0.08 square micron cell size.

A faceted raised source-drain design reduced parasitic capacitance. And the researchers said the undoped channel in ETSOI “greatly reduces the random dopant fluctuation, a major source of device variation.”

The competition between finFETs and the planar ultra thin body SOI is the subject of a TechXPOT at Semicon West on Tuesday, July 12^th, beginning at 10:30 a.m. The two-hour Emerging Architectures for Logic and Memory session includes presentations from Serge Biesemans, vice president of process technology at Imec, on FinFETs; Ali Khakifirooz,  ETSOI lead device engineer at IBM Research, on the ultra thin body SOI approach; and Raj Jammy, vice president of materials and emerging technologies at Sematech, on the heterogeneous integration of high mobility Ge/III-V channels on silicon.

Transistor at left has a silicon thickness of 5 nm. Photo at right shows first-level metal patterning of the SRAM cell. (Source: Symposium on VLSI Technology).

This week, several of the SOI wafer suppliers, including MEMC, SEH, and Soitec, said they are ready to supply the UTB-SOI wafers in high volumes. To support a fully depleted transistor, the critical silicon layer must be kept to 10 nm or less, with minimal variations. Because the cost of the wafers is partially offset by a less-expensive isolation process, the SOI Consortium is claiming no overall increase in the cost of a processed UTB-SOI wafer compared with bulk silicon.

The wafer suppliers in part are responding to comments made by Intel senior fellow Mark Bohr in early May, when Intel rolled out its 22nm finFET-like tri-gate technology. During the press conference, Bohr said Intel’s finFET process cost was just a few percent higher than its planar technology. “Those extremely thin (silicon and BOX layer) SOI wafers are available, but they are very expensive, and pretty hard to get,” Bohr said. He said Intel’s estimate is that using a thin-layered SOI wafer would add 10 percent to the finished wafer cost.

Those assertions riled executives at the SOI wafer suppliers, who have invested in facilities to make the SOI wafers in volumes, sufficient to meet demand from companies making chipsets for smart phones and other mobile systems.

Christophe Maleville, general manager of  Soitec’s microelectronics business unit, said Soitec has an installed industrial base of 2 million wafers per year at its two 300-mm SOI wafer production fabs in Bernin, France and in Singapore.  “We are prepared to expand our SOI capacity to accompany the introduction of FD-SOI technology in very high-volume consumer applications,” Maleville said.

The “Xtreme SOI” wafers from Soitec have “Angstrom-level uniformity, using the same technology platform as our large-volume current production,” Maleville said.

Soitec has licensed its Smart Cut SOI wafer-production technology to Shin-Etsu Handotai (SEH), the largest wafer supplier worldwide, and SEH has completed development of its UTB substrates. Noburo Katsuoka, director of the SOI program at SEH, said “SEH is delighted to deliver the products on request.”

MEMC, based in St. Louis, has been a second source to IBM for the SOI wafers it uses for its partially-depleted CMOS production. Shaker Sadasivam, president of MEMC Semiconductor Materials, said, “MEMC is ready to facilitate and encourage the faster adoption of fully depleted SOI for mobile applications. Large volume utilization is a key factor to achieve reduced pricing for FD SOI, and MEMC has capacity that can be readily expanded to meet industry needs for volume production.”

Sadasivam added that “plans have been developed to expand our FD SOI production to approximately 45,000 wafers per month.”

Horacio Mendez, executive director of the SOI Industry Consortium, said some high-volume mobile IC vendors may introduce fully depleted SOI technology before the 14/15nm node, though FD-SOI will “come in at full force at 14 nanometers.”

A key demand from the mobile IC providers is to have multiple wafer vendors, partially in order to gain lower wafer costs. Soitec has committed to $500 per-wafer pricing in volumes for FD-SOI wafers.

The SOI consortium has been working with a fairly large team of engineers from ARM Ltd. to prove out the advantages of FD-SOI at the 22nm node, Mendez said. Further information about that development project will be made public later this summer, he said.

Mendez said he strongly disagrees with Bohr’s assertion that FD-SOI will add 10 percent to the cost of a planar CMOS silicon process. Because the implant and isolation steps are so much simpler with an SOI substrate, the SOI Consortium believes the finished cost of an SOI wafer will be about 6 percent less than a bulk silicon wafer.

“At 20nm, the performance of a fully depleted technology is so good that companies feel they don’t need to add the stressors, saving on costs there,” said Mendez, a former MPU designer at Freescale Semiconductor.

While Intel may have the manufacturing muscle to implement its tri-gate technology, Mendez said there are few other companies that will be able to make finFETs at good yields. “The yields on finFETs have to be challenging. At the beginning, companies will run into rough patches, where they will not see the same yields as planar transistors,” Mendez said.

One thing the SOI Consortium and Intel agree on: bulk silicon CMOS “is not going to cut it past the 22nm node,” he said.

By David Lammers

Shortages of wafers, chemicals, and other essential semiconductor-manufacturing materials are likely to persist if Japan’s power-generation capabilities remain impaired, IHS iSuppli analysts said Friday (April 1).

Analyst Len Jelinek said “the most overwhelming issue we’ve run into is the issue of power. If rolling brownouts continue for suppliers such as Shin Etsu Handotai (SEH), the impact of the quake will continue longer than expected,” he said.

Source: IHS iSuppli

“At this point, TEPCO (Tokyo Electric Power Co.) is not discriminating between industrial and residential customers,” Jelinek said. With TEPCO’s power generating capacity down 30 percent in the cool spring season, the hot summer may result in rolling brownouts that could impact the return to production of facilities key to the semiconductor production supply chain.

The main worry is the silicon wafer suppliers, though key chemicals are not far behind on the list of concerns. SEH has the world’s largest integrated wafer manufacturing facility in the quake-affected region, and two other major suppliers of wafers also are being impacted. SEH performs the entire wafer manufacturing cycle — from crystal growth through final epitaxial deposition — at its Kamisu and Nishigo facilities. Together, they account for 20 percent of the world’s 300-mm wafer supply.

The wafer-production process requires a clean, uninterrupted supply of power to operate, and any power outages could result in a shortage. “Supplies may be tight,” Jelinek said, adding that “other wafer suppliers are ramping as hard as they can. Customers are scrambling right now to qualify their suppliers.” Most chip manufacturers have a three to four week supply.

“If we run the timeline through, we can count on three to four weeks of limited production, during which companies will be able to procure additional supplies from competitors to SEH,” he said.

SUMCO, another major wafer supplier, has suffered “a minimal amount of damage” at its Yonezawa plant, and is getting ready to restart. SUMCO is shifting wafer production to other plants that were not damaged, he added.

MEMC’s Utsunomiya wafer production facility takes in ingots grown in Taiwan, slices and polishes them in Japan, and does some epitaxial deposition. “Epitaxial manufacturing requires clean power,” Jelinek said, adding that MEMCO could be “one of the key suppliers to recapture some of the lost capacity taken offline by SEH. But MEMC must have a clean, reliable power source.”

Jelinek said chemicals are another key concern, particularly BT resin production needed by the packaging sector, and hydrogen peroxide (H₂O₂) needed for wafer cleaning.

“The real issue is that about 60 percent of the BT resin comes from Mitsubishi Gas and Chemical’s Electrotechno facility in Fukushima. They believe they can get 25 percent of their facilities up and running in the first part of April, and be in full production in May. The customers have a few months supply, so there may be minimal impact on the BT resin supply,” he said.

The Yonezawa Daiya Electronics facility making BT resin in Yamagata is impacted by power outages, as is the Kashima Corp. facility in Ibaraki.

However, the supply of hydrogen peroxide is less assured. A Mitsubishi Gas and Chemical facility in the Fukushima region supplies roughly half of the world’s production of hydrogen peroxide. “The problem is that they need power and raw materials,” Jelinek said. Two other hydrogen peroxide manufacturers are based in Japan, which, together with the Mitsubishi facility, account for 75 percent of the world supply. Akeda-Fuji Corp. produces about 50,000 tons of H₂O₂ per year. Nippon Peroxide’s facility in Koriyama is out of operation currently.

The supply of hydrogen peroxide is “rapidly turning into a very concerning issue. The question is: How quickly can these Japan facilities come back online?” he said.

Dale Ford, manager of the semiconductor industry group at IHS iSuppli, said the March 11 quake has had “the biggest impact on the supply chain in the history of the electronics industry,” exceeding the 1995 Kobe earthquake and the Taiwan quake in 1999. “None of them were as broad in their impact as the effect the Japan quake has had. I would argue this is the most significant supply chain incident ever,” Ford said.

IHS iSuppli reported that the Japanese earthquake has resulted in the suspension of one-quarter of the global production of silicon wafers used to make semiconductors.

Manufacturing operations have stopped at both the Shin-Etsu Handotai (SEH) Shirakawa facility and the Utsunomiya plant of MEMC Electronic Materials Inc., which together account for 25 percent of the global supply of silicon wafers used to make semiconductors.

The SEH Shirakawa facility produces 300mm wafers used mainly for DRAM and NAND memories, resulting in a larger impact on memory production than other types of semiconductors.

Shin-Etsu’s Shirakawa plant is responsible for 20 percent of the global silicon semiconductor wafer supply. Shin-Etsu reported that there has been damage to the plant’s production facilities and equipment. To compensate for the lost manufacturing, Shin-Etsu said it would set up production systems at other facilities. However, the company warned it was unclear how long it would take to restore the damaged facilities and equipment.

MEMC said it evacuated employees and suspended operations at its Utsunomiya plant after the earthquake. The Utsunomiya facility accounts for 5 percent of worldwide semiconductor wafer supply. MEMC said it expects that shipments from this facility will be delayed during the near term.

In another development, two Japanese companies announced they have stopped production that amounts to 70 percent of the worldwide supply of copper-clad laminate (CCL), the main raw material used to make printed circuit boards (PCBs). Mitsubishi Gas Chemical Company Inc. and Hitachi Kasei Polymer Co. Ltd., said they will resume CCL production within two weeks.

With current inventory levels, IHS iSuppli said it believes that there likely is a sufficient supply of finished PCBs and raw CCL material to keep electronics production lines running at global electronics manufacturers, as long as the interruption doesn’t last significantly longer than two weeks.

Elpida Memory Inc. said its semiconductor assembly facility in Yamagata has been damaged. The company also said a lack of electricity is impacting production, keeping the Yamagata facility’s utilization rate at less than 50 percent.

Confirming what IHS iSuppli noted in a previous release, AKM Semiconductor said its fab producing electronics compasses for the iPad 2 has not been damaged, as previously reported. The main fab for the production of the compass is located in Nobeoka, in southern Japan, and did not suffer damage or power disruptions.

The earthquake has damaged about 40 percent of the total wafer capacity of Renesas Electronics Corp. The company has stopped production at its Tsugaru fabs producing analog and discrete devices, at its Naka facility making system-on-chip and microcontroller devices, and at its Takasaki and Kofu fabs making analog and discrete parts.

Half of the total wafer capacity at Fujitsu has been damaged. While the company’s fabs and wafer equipment are intact, the shortage of electricity, gas and wafers means it will take three or four weeks for the company to recovery production, IHS iSuppli reported.