By Mark LaPedus
It’s the tale of two promising and separate 3D chip architectures. One technology is slowly taking root, while the other one is heating up.

3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and SK Hynix are accelerating their efforts in the arena.

Presently, NAND vendors are on the 2xnm or 1xnm nodes. The prevailing thought was that vendors would scale existing planar NAND at three distinct points down the 1xnm node. Typically, NAND vendors denote those points as 1x, 1y and 1z. Then, after the so-called 1z or 1znm node, planar NAND supposedly would hit the scaling wall, forcing vendors to migrate to 3D NAND.

In fact, 2D NAND will have difficulties scaling beyond 10nm. This is because the critical structure in NAND—the floating gate—is seeing an increase in the dreaded cell-to-cell interference in the word lines.

SanDisk still plans to scale NAND for two more generations until 2016, and then, it will debut 3D NAND. But in what appears to be a switch in strategy, Samsung and SK Hynix plan to develop 2D NAND at the 1x and 1y nodes. Then, “it appears that Samsung is bypassing 1z, similar to SK Hynix,” said Doug Freedman, an analyst with RBC Capital Markets.

Instead of going to 1z, Samsung and Hynix will move directly to 3D NAND. In fact, Samsung will begin sampling parts in the second half of 2013, with production slated for 2014, Freedman said.

“As there is maybe one more shrink left for planar NAND, some manufacturers are making the transition earlier to 3D NAND,” said Greg Wong, an analyst with Forward Insights. “Scaling of planar NAND is nearing its end, and 3D NAND is seen as the way to continue density increases and cost reductions for NAND flash memory.”

With 3D NAND, memory vendors also will move from a costly lithography-centric production environment to a less-expensive etch/deposition flow, said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “The overall cost of the tools will be cheaper with 3D NAND,” Lee said “This is mainly driven by the difference in the number of critical lithography and double-patterning steps.”

3D NAND contenders
Samsung will bring out 3D NAND first, followed in order by SK Hynix, Toshiba and Micron, Forward Insights’ Wong said. In 3D NAND, Samsung hopes to leapfrog the competition and grab the early profits with its so-called terabit cell array transistor (TCAT) architecture.

In TCAT, NAND layers are stacked using an oxide and nitride deposition process. Then, the nitride is removed by an etch process. Finally, the bit and word lines are created using a tungsten fill. TCAT and other 3D NAND architectures are different than 2.5D/3D stack-die technologies, where devices are stacked and connected using TSVs.

Another NAND vendor, SanDisk, has a different strategy. “SanDisk is planning to remain planar until 2016, while competitors begin to develop and produce 3D (NAND) into the market late this year and early next,” said RBC’s Freedman. “SanDisk’s (3D NAND) solutions are being judiciously developed to cater to the high-performance market. The high-performance side of the market will not be ready to qualify 3D for another two to three years.”

Using 193nm immersion lithography, the SanDisk-Toshiba duo is producing 19nm planar NAND with a 19- x 26-nm cell size. Then, at 1y, SanDisk’s goal is to devise planar NAND with a 19- x 19.5nm cell size, with production slated by the end of this year.

Then, unlike Samsung and SK Hynix, SanDisk will scale planar at 1z. “There is no need to rush into 3D” until it is cost effective, said Ritu Shrivastava, vice president of technology at SanDisk. In reality, 2D NAND will remain the mainstream technology for some time. Over time, 3D NAND will move into high-end applications, like solid-state storage.

By 2016, SanDisk hopes to debut the Bit Cost Scalable (BiCS) technology, a 3D NAND technology that was originally conceived by Toshiba. BiCS makes use of a “punch-and plug” structure. Toshiba has fabricated a prototype 32-Gbit BiCS test array, with a 16-layer memory cell based on 60nm design rules.

The advantage of 3D NAND is that it doesn’t require leading-edge lithography. Going to 3D NAND will present some challenges, namely the development of quality parts with good read/write performance with endurance. “3D NAND will require a different equipment set,” Shrivastava said. “The burden will shift from lithography to deposition and etch.”

3D NAND process challenges
It also will present NAND vendors with some difficult decisions. First, despite their public roadmaps, vendors may be forced to migrate to 3D NAND sooner than later. “Most leading-edge producers are doing 2D NAND manufacturing at the 20nm or 19nm node, which is the last generation of self-aligned double patterning technology,” Applied’s Lee said. “By using self-align double patterning, one can pattern about 19nm or 19.5nm half-pitch.”

But for some time, the problem with 2D NAND has been apparent—it is running out of steam. “With existing planar NAND, there is not much room to squeeze in the materials for the charge-trap flash or the floating-gate,” Lee said.

In theory, NAND hits the wall at 10nm. “In order to scale NAND manufacturing beyond that, the industry must adopt self-aligned quadruple patterning or self-aligned triple pattering,” he said. “That allows for 10nm half-pitch. But doing 10nm half-pitch patterning will be extremely difficult. It will add a lot more process steps, which will increase the cost of manufacturing.”

Clearly, 3D NAND is the future based on two factors: scaling and cost. “If you compare the cost between sub-20nm planar versus 3D NAND, I believe it will be a lot cheaper to build a 3D NAND fab,” he said. “Planar is driven by litho. In 3D NAND, the bit growth is enabled by increasing the number of vertical layers. This has nothing to do with litho.”

3D NAND can be produced using existing 193nm lithography. Other expensive steps, such as self-align double-patterning etch and low-temperature atomic layer-deposition (ALD), are also eliminated. All told, 3D NAND is largely dependent on two technologies: deposition and etch.

The big challenge is to enable high-aspect ratios using new etch techniques. “There are three distinctly new etch processes in 3D NAND,” Lee said. “This includes high-aspect ratio memory hole etch, which did not exist in planar NAND. There is also a high-aspect ratio trench-line etch, which also did not exist in planar. And then another one is a so-called staircase etch. This is a very long process, which has to provide the landing pads for the contacts.”

3D NAND also introduces alternating stack deposition, which defines the vertical stack. In a 32-layer NAND device, for example, the process could involve some 64 layers of deposition, plus some dummy layers. All told, the flow requires some 70 alternating deposition steps. “The existing tools cannot provide such high productivity,” Lee said. “So that involves a new type of chamber design and technology.”

Metrology is also a critical part of the equation. “Nanometrics believes that 3D NAND will use 20% to 25% more OCD tools relative to planar NAND,” said Weston Twigg, an analyst with Pacific Crest Securities.

“In planar NAND, the gate width is defined by lithography,” added Applied’s Lee. “Now, the gate width is defined by deposition. So, the uniformity of PECVD deposition of each layer, and the quality of the films, are very critical. When we deposit several layers, it’s not a big deal. But let’s say we deposit 40, 50 or 70 layers in-situ. That means we have to control the surface of the interface very smoothly from the beginning. Otherwise, we end up with a rough surface on the top, which will not work.”

So far, Micron, Samsung, SanDisk-Toshiba and SK Hynix have yet to discuss the exact specifications for their respective 3D NAND devices. It’s unclear how many layers the initial devices will have, prompting many to ask a simple question: How far will 3D NAND scale? “I see it going for several generations,” Lee said. “But after 3D NAND, the industry will require another breakthrough.”

By Mark LaPedus
Gartner released its top five IT predictions for China in 2013 and beyond. In one prediction, Chinese PC maker Lenovo will become the top smartphone vendor in China by 2013. The company’s smartphone market share rose from 1.7 percent in 3Q ‘11 to 14.8% in 3Q ‘12, making it now the No. 2 smartphone brand, ahead of Apple (6.9%) and behind Samsung (16.7%).

The SOI Industry Consortium has organized a symposium that will address the world of fully-depleted SOI. The symposium will be held at the San Francisco Hilton Hotel on Dec. 10, concurrent with the IEDM 2012 Conference.

MagnaChip has expanded its foundry production for Peregrine Semiconductor’s STeP5 UltraCMOS technology, which is used for RF devices. UltraCMOS is an advanced form of silicon-on-insulator technology based on a sapphire substrate.

At the IEEE International Solid-State Circuits Conference (ISSCC), which is in San Francisco from Feb. 17 to 21, 2013, IBM will present a paper on a next-generation processor for its System z mainframe. The processor combines six 5.5 GHz processor cores and two memory chips in a ceramic MCM package. The processor has 2.75 billion transistors on a 598mm2 die. The 32nm chip makes use of a high-k/metal-gate scheme and SOI technology with 15 layers of metal. The chips are placed on a 102-layer MCM with two 192MB L4 cache ICs. This is said to achieve a total MCM bandwidth of 530GB/s.

Also at ISSCC, IBM will describe a 22nm SOI SRAM operating over a wide voltage range of 0.7V to 1.1V. It employs a fine granularity power-gating feature, which reduces bit cell leakage by 37% and also reduces peripheral circuit leakage by 40%.

During the event, AMD will describe a 28nm, 11-metal layer x86 processor. The so-called “Jaguar”quad-core processor runs at up to 1.85 GHz.

Oracle will take ISSCC to introduce its next-generation SPARC T5 processor in 28nm technology with 13 metal layers containing 1.5 billion transistors. The chip integrates 16 3.6 GHz cores and a shared 8MB L3 cache with a 9-port crossbar. Oracle also will demonstrate glueless scaling to 8 sockets, or 128 cores, to deliver a total of 1024 threads in a single system. Its new I/O system architecture enables over 5TB/s bandwidth.

At ISSCC, China’s Loongson Technology will demonstrate its latest 8-core microprocessor, dubbed the Godson-3B1500, based on a MIPS64 instruction set. Fabricated in a 32nm, high-k/metal-gate process with 10 layers of metal, the chip contains 1.14 billion transistors. The processor operates at 1.35 GHz.

On the memory side at ISSCC, SanDisk and Toshiba will present a 32 Gbit ReRAM test chip in a 24nm process with a diode as the selection device. Separately, TSMC will present a cycling-endurance optimization scheme for a 1-Mbit STT-MRAM in 40nm technology with a dynamic load balance circuit. And Micron will present the first ever 128-Gbit, 3-bit-per-cell NAND design using 20nm planar cell technology.

Mentor Graphics announced the availability of a GENIVI 3.0 specification-compliant Linux- based Infotainment product. The solution integrates graphics, communication and multimedia middleware with libraries, system infrastructure and management components on top of Linux. http://www.mentor.com/company/news/mentor-embedded-genivi-3-compliant

TSMC recently approved capital appropriations totaling approximately $2.975 billion for the purpose of expanding advanced process capacity and the construction of a 300mm GigaFab. It also approved R&D capital appropriations and 2013 sustaining capital appropriations totaling approximately $209.5 million. In addition, it approved the subscription of approximately $42.28 million in new shares to be issued by TSMC Solid State Lighting Ltd. in 2013. And finally, it approved the subscription of approximately $21.63 million in new shares to be issued by TSMC Solar Ltd. in 2013.

Creative Technology has entered into an agreement with Intel under which Intel will license certain GPU technology and patents from ZiiLABS, a subsidiary of Creative. Intel will acquire certain engineering resources and assets related to the U.K. subsidiary of ZiiLABS. The deal is worth $50 million.

MIPS Technologies has received an unsolicited and rival proposal from CEVA to acquire all of the outstanding shares of MIPS. This follows MIPS’ proposed patent sale transaction with Bridge Crossing.

Global GDP growth is now expected to expand by an estimated 2.6% in 2012, close to the global recession threshold of 2.5% and well below the long-term average growth rate of 3.5%. However, the forecast for worldwide GDP in 2013 is 3.2% growth, according to IC Insights.

Smartphones will account for a larger share of NAND flash memory usage, as compared to feature phones, according to iSuppli.

Global demand and pricing in October for solar polysilicon fell at the highest rate seen since February, indicating that supply still exceeds demand, according to the IHS Solar Polysilicon Price Index.

By Mark LaPedus
The NAND flash memory market is entering into a new and painful cycle, a period that will impact suppliers, OEMs and fab tool vendors alike.

For some time, there has been an oversupply and depressed pricing in the NAND market. In mid-2011, Micron, Samsung, SK Hynix and Toshiba put on the brakes in their capital spending plans. And in recent months, NAND suppliers in total have announced plans to cut 150,000 wafer starts per month, or about 12% of the world’s NAND capacity, amid ongoing losses and sluggish demand.

Just as suppliers moved to cut their production, spot shortages of NAND surfaced at some OEMs in early September. Most OEMs are not seeing any shortages, but that could all change. Apple, the world’s largest buyer of NAND, could cause some gyrations in the channels as it ramps up its new iPhone 5.

So what’s the outlook in the fluid and confusing NAND market? Amid a bitter legal battle with Samsung, speculation is rampant throughout the NAND industry about whether Apple will swap suppliers from Samsung to SK Hynix, Toshiba and Micron. If that happens, Samsung would face an oversupply in NAND, while others may see capacity shortfalls.

The outlook is also not so rosy for fab tool vendors, which counted on a big capital spending cycle for NAND. In fact, NAND suppliers are expected to push out their capital spending plans until June of 2013 and perhaps beyond, said Vijay Rakesh, an analyst with Sterne Agee.

The lack of capital spending is expected to create a shortfall in NAND capacity, creating perhaps a long cycle of acute shortages. Presently, there is a capacity glut for NAND. “Demand should catch up with capacity by mid-2013,” said Jim Handy, an analyst with Objective-Analysis. “Then, there could be NAND shortages from then until the middle of 2015.”

In total, suppliers are expected to ship 28.013 billion gigabits of NAND in 2012, which represents a bit growth of 49% over 2011, according to Stern Agee. The figure is lower than the historical averages in terms of bit growth, which ranges from 65% to 85%, according to the firm. In total, suppliers are expected to ship 43.756 billion gigabits of NAND in 2013, which represents a bit growth of 56%, according to Stern Agee.

Boom to bust
NAND has seen its share of boom and bust cycles. Several years ago, NAND vendors witnessed a meteoric rise amid a boom for cell phones, flash cards, USB drives and other products.

Then, over the last two or so years, Micron, Samsung, SK Hynix and Toshiba began to expand their NAND production at a dramatic pace. The goal was to meet the anticipated demand for the next wave of product drivers, such as smartphones, solid-state drives (SSDs), tablets and ultrabooks.

Seeking to drive down product costs, particularly for SSDs, NAND vendors took the lead in process technology. For example, the Toshiba-SanDisk duo has been ramping up parts based on the world’s most advanced process, a 19nm technology.

The bottom fell out of the NAND market in recent times. NAND vendors built up too much fab capacity. Average selling prices (ASPs) for NAND fell by 46% in the first half of 2012. Demand for NAND in smartphones and tablets remains overwhelming, but SSD and ultrabook shipments have been disappointing thus far.

“The adoption of solid-state drives is not ramping as quickly as forecast, and with only a modest increase in the bits per box for mobile devices, we now see NAND bit growth in the range of 60% to 65%,” said Mike Splinter, chairman and chief executive of Applied Materials, during a recent conference call. As a result, NAND vendors in total plan to cut production by roughly 150,000 wafer starts per month “on top of a reduction in their capital spending,” Splinter said.

Based on recent announcements, Toshiba is cutting 30% of its NAND production, Micron is reducing its output by 15%, and SK Hynix and Samsung are each at 10%, said Hans Mosesmann, an analyst with Raymond James. “Using these percentages, this would equate to a 12% reduction in supply,” he said.

NAND vendors expected bit growth of about 70% in 2012, but they have lowered their forecasts to about 45%, said Robert Witkow, president of Westwood Marketing, a research firm. “All manufacturers are regulating bit growth by slowing the transitions of 2xnm to the 1xnm node,” Witkow said. “All manufacturers are slowing their transitions from 64-Gbit to 128-Gbit devices.”

One OEM, OCZ Technology, lowered its quarterly forecast in September, saying it could not obtain enough NAND parts for its SSDs. “My price survey and other feedback I’ve received confirm some tightness (in NAND supply),” Witkow said. “If we have allocation in NAND, which I think is possible in 2012, it will be short-lived. I think the NAND market will ease at the end of October, as production sold for Christmas winds down.”

The average selling price (ASP) outlook is good for consumers, but horrific for suppliers. In September 2010, NAND crossed the $1.00/GB price point. The price dropped to $0.35/GB in May of 2012, according to Objective-Analysis’ Handy. “It hit $0.31/GB in June, but then it went back up to $0.36/GB in August,” Handy said. “The June pricing was below manufacturing costs, which is unsustainable. It could go as low as $0.31/GB again, but not temporarily as it did before. That would be permanent.”

NAND CapEx slows
On the fab tool side of the equation, Applied Materials and others saw a softening in demand for gear in the summer, due in part to sharp declines in foundry and NAND spending. By late August, tool vendors saw a further deterioration in NAND, causing more tool pushouts, according to Applied’s Splinter.

Capital spending will remain anemic in DRAMs. The foundries expanded their 28nm capacities earlier this year. But more recently, foundries put the brakes on spending to digest their new tool buys, Splinter said. In total, fab tool capital spending is expected to reach $30 billion to $33 billion in 2012, down 10% to 20% from 2011, he said. In its original projection, Applied forecasted a flat year in fab tool spending.

There’s good and bad news for fab tool vendors. For example, Samsung, the world’s largest NAND vendor, is cutting some NAND production. But the company also is converting some of its NAND production to system LSI and foundry services. As it turns out, logic is more profitable than NAND.

Samsung still wants to remain the leader in NAND. Last year, for example, the company began ramping up NAND production in Line 16 in Korea. “Samsung has slowed its expansion of Line 16, but it did not cut wafer starts,” said Westwood Marketing’s Witkow.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, is a foundry plant dedicated for Apple.

The other fab in Austin is currently a NAND facility. Austin represents about 20% of Samsung’s total NAND capacity, according to Barclays Capital. However, Samsung is converting that fab from NAND into a system LSI plant, said Christian Gregor Dieseldorff, an analyst with SEMI. “Ultimately, all of Austin will be converted to system LSI,” Dieseldorff said.

In Korea, Samsung’s main logic/foundry fab is called S1, which is being expanded. Samsung is converting its Line 14 plant in Korea from NAND to 28nm logic capacity. Line 14 is now part of S1, he said.

Meanwhile, Toshiba, the world’s second largest NAND vendor, in June announced plans to cut NAND production by about 30% at its Yokkaichi Operation fab in Mie Prefecture, Japan. At a minimum, this could remove 6% of worldwide NAND supply, according to Barclays Capital.

Micron, the world’s third largest NAND vendor, is re-balancing its capacity. “Micron increased its triple-level-cell (TLC) wafer production slightly, but reduced its multi-level-cell (MLC) slightly in June. My belief is that the move was taken to support the Lexar consumer product builds for Christmas. Micron will likely shift (its production) back to MLC shortly,” said Westwood Marketing’s Witkow.

SK Hynix, the world’s fourth largest NAND vendor, added 10,000 wafer starts at its new M12 fab in Korea. But SK Hynix is also mulling plans to shift its capacity from NAND to DRAM in M12, according to Barclays Capital.

By Mark LaPedus
For years, many have predicted the end of flash memory scaling, particularly NAND, but the technology continues to defy the odds as it moves down the process curve.

Still, there are signs that the floating gate structure in today’s flash memory is on its last legs. The floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio. And there is an increase in cell-to-cell interference in the word lines.

“The floating gate has been very successful in scaling down to the current 20nm node or even the 1xnm node,” said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “There is not much room for the floating gate to scale. Nobody really believes that planar NAND can go below 10nm.”

Today, the Toshiba-SanDisk duo is shipping NAND devices based on the world’s most advanced process, a 19nm technology. Going forward in NAND, Lee and others see at least two or more nodes remaining in the 1xnm regime.

The question is what’s after NAND flash? Currently, the industry is pursuing three basic categories in the NAND replacement sweepstakes: scaling existing NAND; 3D NAND; and the next-generation memory types.

There is no clear-cut winner right now. But in some circles, the initial and most promising successor is 3D NAND. “3D NAND is an extension of existing NAND,” Lee said. “Vertical NAND is in the development stage right now. The timeline for mass production is as early as 2013. Some companies have announced 2015.”

Defying the odds
Clearly, flash scaling has defied the odds. Ten years ago, Intel, the first vendor that commercialized NOR flash, predicted that flash would hit the wall at 65nm. Banking on those predictions, a number of firms began to develop various next-generation memory technologies that could replace NAND, NOR or DRAM—or all three. FeRAM, MRAM, phase-change and ReRAM are among those candidates.

The prediction was wrong, however. NAND has scaled down to 19nm, while NOR has migrated to 45nm. Thanks to 193nm immersion lithography and self-aligned double patterning (SADP), flash vendors have been able to scale the floating gate.

The ability to scale NAND and NOR has also pushed out the need for the next-generation memory types. And besides, most of these new memory types are still in R&D. They are expensive to make and difficult to scale.

Scaling today’s NAND down to 10nm is also difficult. NAND vendors may have to use self-aligned quadruple patterning, as extreme ultraviolet (EUV) lithography remains delayed. “NAND is even beyond current EUV resolutions. Even if EUV is available as of today, double patterning has to be used together with EUV,” Lee said.

There is also a remote chance that today’s 2D NAND could scale further using charge trap technology. Charge trap uses a silicon nitride film to store electrons. “I think the generation of charge trap flash as a planar device is limited,” he said.

Initially, if or when today’s NAND runs out of gas, the industry is banking on 3D NAND. “With 3D NAND, scaling is no longer driven by lithography. The gate length is defined by deposition,” Lee said.

3D NAND is also challenging, but the production steps are slightly different than 3D stacked DRAM and logic. The key step to 3D NAND is to build a multitude of oxide/nitride or oxide/doped polysilicon stacked layers. Another key step is to fill the deep memory holes or trench slits. “The top foreseeable challenges are ultra-high-aspect ratio (>40:1) conductor etch and dielectric etch with high etch selectivity to the hard mask,” Lee said in a recent paper.

There’s another challenge as well: Can the 3D NAND developers put their products into production? The main 3D NAND contenders are Toshiba’s BiCS, Samsung’s VG-NAND, Macronix’ BE-SONOS, Hynix’ vertical cylindrical FG, SanDisk’s 3D memory and Intel/Micron’s stackable PCM, according to Forward Insights.

The 3D NAND industry emerged in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. BiCs makes use of a “punch-and plug” structure and charge trap memory films. Toshiba has fabricated a prototype 32-Gbit BiCS flash memory test array with a 16-layer memory cell using 60nm design rules.

In 2009, Samsung described its 3D NAND technology based on a terabit cell array transistor (TCAT). A year later, Macronix talked about a BE-SONOS charge-trapping technology. And Hynix is developing a 3D dual control-gate with a surrounding floating-gate.

One of the newer candidates is the stackable phase-change memory (PCM) device from Intel and Micron. Micron recently announced a 2D PCM device based on a 45nm process. In PCM, it is difficult to scale the cell array. PCM is also limited by the power required to change from the crystalline to an amorphous state.

Researchers are looking at new materials beyond traditional GST-225 schemes to overcome these limitations. Among those materials are binary and ternary alloys like germanium telluride (GeTe). “GeTe is one of the enablers,” said Jean-Luc Delcarri, general manager of Altatech, a CVD and inspection equipment subsidiary of Soitec. Altatech has installed its CVD system at CEA-Leti, which is developing PCM for the sub-20nm node.

It’s unclear which 3D NAND devices will eventually move into production, but there is a huge appetite for NAND in mobile and other applications. “I can’t say which vendor is ahead,” Applied’s Lee said. “I think vertical NAND will likely be adopted in traditional applications. The biggest applications are smartphones, tablets and mobile computing. What is still to come are SSDs.”

3D NAND debate
Analysts have slightly different viewpoints. “The only company that has told me a schedule is Toshiba, who plans to sample 3D NAND in 2013,” said Jim Handy, an analyst with Objective-Analysis, a research firm.

“The thing that is driving (3D NAND) is the use for more bytes in video,” Handy said. “3D NAND is straightforward for a DRAM maker since it has stacked SiO2 and polysilicon layers like a stacked capacitor DRAM and trenches like a trench cell DRAM. I have heard that the aspect ratios for the trenches are somewhat tricky.”

Greg Wong, an analyst with Forward Insights, does not see commercial production for 3D NAND until 2015 or so. “NAND flash manufacturers are pushing planar NAND flash to sub-20nm nodes. As they extend the roadmap for 2D NAND, the introduction of 3D NAND gets pushed out,” Wong said.

“There are technical challenges with etching a high aspect ratio pillar and multiple stacks, but the big challenge is economic. The investment required is significantly more for 3D than 2D NAND,” Wong said. “3D NAND employing charge trapping technology will have some challenges in meeting the performance specifications of 2D NAND. However, by stacking multiple layers, lower cost per bit can be attained.”

Alan Niebel, president of Web-Feet Research, agreed. “3D NAND should enter the market around 2015 (or after). Designing and qualifying 3D NAND will probably be a seven year process, which started in 2007. Concurrently, it takes easily another five years to perfect the manufacturing and especially in manufacturing 3D ICs,” Niebel said.

“3D NAND should have a much higher areal density and lower cost than 2D NAND, since the F2 divides in half with each layer, probably four layers max per chip. Performance in both speeds (read and write) and endurance will deteriorate with 3D NAND compared to 2D,” he added. “The stacked structure will have more bits to address, more interconnects with each layer and longer distance from cell to controller that will add latency to the 3D. Perhaps endurance may not suffer too much if the lithography is the same for 2D and 3D NAND cells, but by stacking them in 3D, these additional steps could possibly fatigue the control gate oxides and further reduce endurance.”

Besides the technology challenges, Applied’s Lee sees another hurdle—cost. “NAND vendors will go into 3D only if they can meet a cost target. We are quite confident the cost structure of 3D NAND will be lower than 2D NAND. The reason is that 3D NAND is less lithographic and double-patterning heavy,” he said.

Synthetic diamond process enables quantum computing
There is a growing interest in the area of quantum computing. A quantum computer works by storing the 0s and 1s of information in quantum superposition states. They could one day solve problems that are impossible for even the fastest conventional supercomputers.

In one of the latest efforts, Element Six, Harvard University, the California Institute of Technology and Max-Planck-Institut für Quantenoptik, have devised a single-crystal synthetic diamond to enable the development of a quantum-bit memory. Using Element Six’s synthetic diamond technology and its chemical vapor deposition (CVD) process, the researchers also demonstrated a quantum bit memory that exceeds one second at room temperature.

This is said to be the first time that such long memory times have been reported for a material at room temperature, giving synthetic diamonds an advantage over rival materials and technologies, such as cryogenic cooling.

Mikhail Lukin of Harvard’s Department of Physics, said: “These findings might one day lead to novel quantum communication and computation technologies, but in the nearer term may enable a range of novel and disruptive quantum sensor technologies, such as those being targeted to image magnetic fields on the nano-scale for use in imaging chemical and biological processes.”

Element Six’s synthetic diamonds are ideal for applications that require extreme hardness and thermal conductivity. Applications include semiconductors, lasers, quantum computing, and magnetometry and bio-medical sensors.

ReRAMs take another step towards commercialization
R&D organization IMEC recently presented improvements in performance and reliability of resistive RAM (ReRAM) cells by process improvements and stack engineering. RRAM is a promising next-generation memory technology that could replace NAND flash.

IMEC demonstrated asymmetric bipolar RRAM cells with high-performance and ultra-low operation current at <500nA. A hafnium scavenging layer was proven to be key in the stack asymmetry of defect distribution and in the forming process. The state resistances were controlled by introducing aluminium oxide as insert layer, hafnium oxide was kept as a buffer material for further improving the filament resistance control, and stack thinning allowed a lower forming current.

These results were obtained in cooperation with IMEC’s key partners in its core CMOS programs, including Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, SK Hynix, Fujitsu, Toshiba/SanDisk, and Sony.

By Mark LaPedus

For years, the shift to the next process node has always presented new, difficult and sometimes costly challenges in the IC manufacturing flow.

At the 130nm node, for example, chip makers saw the ongoing migration to sub-wavelength lithography, the transition to low-k dielectrics, and the emergence of design-for-manufacturing (DFM). And at that node, there were also two basic physical verification steps in the flow:  one-dimensional design rule checks (DRCs) and layout versus schematic (LVS).

At the time, the 130nm node seemed like a difficult process to master. Fast forward. As the logic world migrates from the 40nm to the 32/28nm process nodes, chip production is obviously more complex and expensive.  At 32/28nm, for example, the foundries must extend 193nm wavelength lithography and implement their initial high-k/metal-gate schemes.

From a physical verification standpoint at 32/28nm, IC makers will continue to use the old standbys: DRC and LVS. But starting at the 40/28nm nodes, vendors added more complex physical verification steps to the mix: 2.5/3D verification, parasitic extraction, advanced device parameter extraction, lithography checks/simulation, patterning matching, dummy fill, among others.

And if that wasn’t enough, there are even more challenges at the 20nm node and beyond. IC design, process and fab tool costs will continue to soar. From a DFM and physical verification standpoint, chip makers will also face some new challenges. Among the newer physical verification steps — and challenges — at 20nm and 14nm include double-patterning, delta-voltage DRC, advanced fills, design-for-reliability (DFR) and others.

“At every technology node, the designer must address more and more manufacturability concerns,” said Michael White, product marketing director for Calibre Physical Verification at Mentor Graphics Corp. “This has manifested itself as an increase in DRC checks as well as other verification checks node over node.”

Here’s some of the newer physical verification steps that chip makers will face at 20nm and 14nm:

Double patterning: Not a show stopper (yet)

The biggest step from the 28nm to the 20nm node is clear. “Double patterning is the major thing at 20nm,” said Andy Brotman, vice president of design infrastructure at silicon foundry vendor GlobalFoundries Inc.

Brotman believes the industry is ready for the double patterning era at 20nm. But at 14nm, it’s unclear if extreme ultraviolet (EUV) lithography will be ready in time. If not, the industry must extend 193nm immersion and may be forced to use triple-patterning. “Double-patterning is doable,” Brotman said. “For triple-patterning, there is work to be done.”

In other words, chip makers face the dreaded multi-patterning era as they march down the process curve. On the device side, the SanDisk/Toshiba duo are ramping up the industry’s most advanced process – a 19nm NAND flash line. On the logic front, Intel Corp. is moving from planar transistors at 32nm to finFETs at 22nm. At 20nm, the foundries will continue to use planar transistors. The foundries plan to move to finFETs at 14nm.

To continue scaling, the NAND crowd has already inserted a technology called self-aligned double-patterning (SADP). At 20nm, the logic vendors are looking to adopt a relatively expensive double-pattering technique called litho-etch-litho-etch (LELE).

Double-patterning “is a very complex step,” said Mentor’s White. “But all of my competitors are saying: ‘Double patterning is here and the sky is falling.’ Will this be a giant (show stopper)? I don’t think so.”

So, at least from a physical verification standpoint, double patterning is doable, he said. On average, the number of physical verification steps are increasing by some 30 percent at each process node. There are a total of 3,000 individual physical verification or DRC checks at the 32/28nm node, according to Mentor.
In comparison, there are a total of 3,500 checks at the 20nm node, a 30 percent increase from 32/28nm. But surprisingly, less than 1 percent of those checks are related to double-patterning at 20nm, he said.

There are some challenges, however. In double-patterning, the layout patterns are split and decomposed into two different masks. The polygons or features are assigned different colors. If the features are too close, then so-called “coloring conflicts” may emerge. This can be solved by using cut and stitch techniques. In this scenario, the polygons on a mask are cut into different pieces and then recombined through stitching points.

“Using cuts in (an) auto decomposition tool can fix a majority of cycle violations but is adds complications in OPC correction and potentially more electrical variation,” he said.

At 14nm, it’s unclear if EUV will be ready in time. If not, leading-edge logic vendors are looking at triple-patterning or SADP. And there is also still uncertainty at the 10nm node. Some hope EUV will be ready at 10nm. Since EUV is a 13.5nm wavelength technology, EUV will likely be combined with double-patterning at 10nm.  Another technology called directed self-assembly (DSA) could swoop in and save the day.

Summarizing the trends in lithography, White said: “Multi-pattering is here to stay.”

Voltage-based DRC technology

At the 20nm node, most of the attention is currently centered around the emergence of double patterning. But there are new technologies emerging at 20nm, namely delta-voltage or voltage-based DRC.

DRC technology verifies the layout of a circuit and ensures that the design does not violate any rules associated with the process. Over time, Mentor has developed equation-based DRC, which allows users to check and correct issues that are difficult to perform with classic DRC. This includes gate and interconnect checking, poly corner rounding, among others. “DRC has been around forever, but it gets harder and harder,” White said.

At 20nm and 14nm, there is expected to be the emergence of voltage-based DRC. “You want a larger spacing between nets, where there is a large voltage differential (e.g. between ground and 5V).  You can afford a smaller spacing between net with less (e.g. ground and 1.5V or between 1.3V and 1.5V),” White said.  “Some of these types of checks were in place at 28nm, but they always assumed the worst case (e.g. ground and VDD).  At 20nm, they are more sophisticated.”

Don’t forget about DFM

For some time, a designer has only had two options for identifying DFM issues in the design phase: run accurate but computationally intensive simulations or rely on metrology measurements directly from the fab. Attempts have been made to improve upon standard DRC with additional rules, but these approaches have had mixed success.

To solve the issue, GlobalFoundries has implemented a technology called DRC+. This goes beyond standard DRC and uses two-dimensional shape-based pattern-matching to enable a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy. DRC+, together with rule-based DFM verification and model-based litho/etch and CMP simulators, can identify new yield-detracting patterns.

Fill it up

In chip design, there is a step called fill. This involves adding shapes or polygons to the design, which ensures each layer has the proper density. One option for metal fill was sometimes called “dummy fill.” But dummy fill solutions become more challenging at each process node, requiring advanced or “smart” fill techniques at 20nm and beyond.

“That is, the fill must be ‘smart,’ meaning it integrates an analysis engine with the filling algorithm and performs analysis concurrently with fill insertion; a technique that qualifies as correct-by-construction,” said Jean-Marie Brunet, product marketing director at Mentor, in a recent blog posted on SemiMD.  “The result is minimum fill, complete adherence to constraints, improved manufacturability, and a faster run time.”

More DFx?

Yet another DFx term is hitting the airwaves: Design-for-reliability or DFR. In design scaling, there are ongoing stress effects, electrostatic discharge (ESD) and other issues that crop up. In other words, there is a need for “comprehensive reliability checks,”Mentor’s White said.

Electrical rule checking has been around for some time to address ESD and other issues in designs.  Still, there some vast changes taking place in ESD standards, prompting chip makers to re-think their strategies.

It has been widely known that ESD causes an inordinate percentage of chip failures in the field.  For years, ESD target levels for chips in the human body model (HBM) and machine model (MM) have stayed constant at 2KV and 200V, respectively. But a group called the Industry Council on ESD Target Levels believes that these ESD levels are taking up too much silicon real estate, prompting the need for lower target levels. For some time, the group has proposed a reduction in ESD levels to 1kV for HBM and 30V in MM.

Some OEMs are moving to lower their ESD target levels. Others are reluctant to lower their ESD standards. What this implies is that chip makers must be flexible and have a sound ESD strategy, in additionl to the associated IP and EDA tools in place.

Solution to the problem: Go with the flow

“The challenge at 20nm centers around double-patterning and a lot of design rules,” said GlobalFoundries’ Brotman. “The question is how do we continue to shrink to 2xnm with more restrictive design rules?”

One of the solutions is to provide flexible options in the design flow.  Mentor recently disclosed pieces of the 20nm design flow for the Common Platform alliance, which includes IBM, GlobalFoundries and Samsung.

There are four different options in the flow, each with a set of trade-offs. On one end of the spectrum, a colorless flow is more restrictive but also more automated.  On the other end of the spectrum, there is a manual flow that is less restrictive. There are hybrid flows in between. “I would expect to see similar flows at 14nm and beyond,” Mentor’s White said.

By Mark LaPedus

For some time, the NAND flash market has been primarily dominated by five vendors: Micron, Samsung, SanDisk, SK Hynix and Toshiba.

Other vendors have been seeking to get a foothold in the exploding market — with little or no luck. Intel Corp. and Powerchip Semiconductor Corp. have separately experienced limited success in NAND. And Elpida Memory Inc. and Spansion Inc. are co-developing NAND, although one analyst claims Elpida has bailed out of the alliance.

Now, Spansion has signed a new NAND deal with SK Hynix Semiconductor Inc. And two Taiwan vendors — Macronix International Co. Ltd. and Winbond Electronics Corp. — have recently entered the fray.

NAND flash is a tough business to crack despite soaring demand. It requires technology, intellectual-property (IP) and deep pockets. The capital required at the leading-edge of NAND is astronomical. And it is cyclical. For example, on April 3, SanDisk Corp. lowered its forecast for its first fiscal quarter 2012 ended April 1. Due to weaker than expected pricing and demand for its flash products, the company estimates total revenue to be approximately $1.2 billion, down from the previously forecasted revenue range of $1.30 to $1.35 billion.

Despite the challenges, several new vendors want to enter the sector. The new players are not looking to go toe-to-toe against the established vendors, but rather they are looking at niche markets.

On April 2, for example, NOR flash specialist Spansion entered the market by launching lower-density, single-level-cell (SLC) NAND products for the embedded market. Built around on an older-generation, 4xnm process node, the parts are based on technology from South Korea’s SK Hynix. Recently, South Korean mobile vendor SK Telecom took a controlling share of Hynix, resulting in the renaming of the memory maker to SK Hynix.

In any case, the deal raised questions about Spansion’s deal with Elpida. In 2010, Elpida and Spansion forged a joint NAND development deal. The companies were devising NAND based on Spansion’s so-called MirrorBit charge-trapping technology.

Used in its NOR flash lines, Spansion’s MirrorBit technology doubles the density of a flash memory array by storing two physically distinct quantities of a charge on opposite sides of a memory cell. Charge-trap flash (CTF) depends on a SONOS (semiconductor-oxide-nitride-oxide-semiconductor) capacitor structure, storing the information in charge traps in the nitride layer.

“We are still working with Elpida on our charge trapping NAND technology, which we believe provides a unique ability to achieve 1xnm NAND,” according to a spokeswoman for Spansion. “Our alliance with SK Hynix accelerates our time to market to deliver Spansion SLC NAND products for the embedded market, utilizing their manufacturing capability in 4xnm, 3xnm, and 2xnm.”

Greg Wong, an analyst with Forward Insights, a research firm, believes that Elpida is no longer working with Spansion. Elpida has recently filed for bankruptcy in Japan. “Elpida is no longer working on NAND,” Wong said. “CTF has some fundamental reliability issues, which is the reason for the Hynix alliance.’’

Hynix’ NAND technology is based on conventional floating-gate flash memory. When asked if the problem resides with Spansion’s CTF technology, Wong said: “CTF in general has reliability issues. It’s related to the technology itself, not specifically to Spansion.”

The analyst also believes that the new players — Spansion, Macronix, Powerchip and Winbond — do not pose a threat to NAND leaders. “They are focusing on low-density products for embedded applications — and not competing in mainstream high density consumer markets. All these players are using older technologies,” he added.

Jim Handy, an analyst with Objective-Analysis, agreed. “These companies are going after the markets that are being abandoned by the high-volume NAND makers,” he said.

Spansion’s SLC NAND product portfolio will be available in 1-, 2-, and 4-Gbit densities with 1 bit ECC. The first SLC NAND products resulting from its alliance with Hynix will be available beginning in the second quarter of 2012. As part of the relationship, Hynix and Spansion will enter into a patent cross-licensing agreement. 3xnm products will be available in the second half of 2012 and early 2013. The 2nm parts schedule will be announced soon.

Another vendor, Taiwan’s Macronix, recently entered the NAND market. The supplier of NOR flash and other products launched its first-generation SLC NAND line, dubbed the MX30LF family. Macronix has begun sampling SLC NAND products. Fabricated within Macronix’ fabs, the new MX30LF family consists of two products. The MX30LF1208AA and MX30LF1G08AA come in 512-Mbit and 1-Gbit densities, respectively. Both products utilize 75nm floating gate technology.

Using 19nm process technology, SanDisk Corp. and Toshiba Corp. said they have  developed the world’s smallest 128Gbit NAND memory IC currently in production. Using 3-bit-per-cell (X3) technology, the die size is just 170mm² — a little more than a quarter of an inch squared.

SanDisk said the partners’ 19nm technology is the ninth generation of multi-level cell (MLC) NAND products, and the fifth generation of X3 technology. The 128Gb device has a write performance of 18 MB/s, using SanDisk’s all bit line (ABL) architecture. A technical paper will be presented at the International Solid-State Circuits Conference (ISSCC) in San Francisco Wednesday (Feb. 22).

Products based on the 128Gb three-bit per cell technology began shipping late last year and have already started to ramp into high-volume production. SanDisk has also developed a derivative product based on the 128Gb chip – a 64Gb, X3 NAND flash memory chip that is compatible with the microSD format. SanDisk has started to ramp production of this chip as well.