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GLOBALFOUNDRIES and Samsung join forces on 14nm finFETs

Thursday, April 17th, 2014

By Ed Korczynski and Pete Singer, SemiMD and Solid State Technology

Fabless companies could skip the 20nm node and move straight to 14nm FinFETs. That is the hope of GLOBALFOUNDRIES and Samsung who are announcing a joint program that offers a single process design kit (PDK) and manufacturing at four different fabs with identical processes. The PDKs are available now, and 14nm manufacturing could move into high volume production by the end of the year.

This is unprecedented,” said Kelvin Low, senior director of marketing at Samsung. “It never has happened in the industry, especially at the very leading edge nodes. We are confident that this will transform the supply chain model,” he added.

Fabless companies such as Qualcomm have been lobbying for such multi-sourcing for some time, and are eager to move to FinFETs which offer higher performance and reduced power consumption. 14nm FinFETs offer a 20% improvement in performance and a 35% reduction in power compared to 20nm technology.

“For both Samsung and GLOBALFOUNDRIES, we will be providing our customers with a choice and assurances of supply, enabled by the unprecedented global capacity across our respective manufacturing facilities throughout different locations worldwide,” Low said. “For Samsung, we have facilities in the U.S. in Austin. We also have a couple of plants in Korea. For GLOBALFOUNDRIES, the 14 nm capacity will be in Malta, NY.”

The single process design kit will allow customers to do a single design that is capable of being multi-sourced from different locations.

“This really is a change from the existing supply chain model where customers are trying to design multiple designs to multi-source their products,” Low said. “True design compatibility in this collaboration will allow customers to better manage their design NRE and they can focus on bringing the product to market on time. Both companies see this as a necessary advancement of the supply chain model and we start off with the 14nm LPE as well as the 14nm LPP technology node.” 14nm LPP is a follow-on offering which has additional performance enhancements as well as power reduction attributes.

Samsung had already developed much of the process technology for LPP and LPE flows to run using 14nm node finFETs, while GLOBALFOUNDRIES was working independently on another 14nm node process variant. The two companies decided to pool resources to save both time and money in bringing 14nm node finFET capability to the commercial IC foundry market.

Because of customer interest in having that assurance of supply and being able to do one GDS and being able to work off of one common PDK and source at both of our companies, we decided to work together and go with the 14 LPE and 14 LPP as common offerings between Samsung and GLOBALFOUNDRIES,” said Ana Hunter, VP of product management at GLOBALFOUNDRIES.

Low said that Samsung is already running 14nm products in its fab in Korea. The 14nm LPE, for example, was qualified earlier this year.

“We are already in silicon validation of our lead customer products. We expect to ramp production by the end of this year,” he said. Design activities started almost three years ago. “Right now, we are seeing a lot more pickup overall by the lead adopters and even other customers following suit, mainly because the marketplace does see that the 14nm FinFET is at the right maturity level for volume production,” Low said.

Although there is still lot of activity at 28nm, the technology is considered to be in a mature phase. “We still continue to see healthy, new design-ins,” Low said. “Of course, there are a lot of requests to see what additional enhancements we can do at our 28nm node to prolong the lifespan of that node.”

What about 20nm? “From Samsung’s viewpoint, we see that a relatively short-lived node, mainly because of the overall resonance of FinFETs and the eagerness of customers to migrate from 28nm directly to 14nm FinFETs.”

Hunter agrees, noting that 28nm has been in high volume production for several years now. She said GLOBALFOUNDRIES does have 20nm product tapeouts running in the line, but said that she does not see 20nm being a very extensive node in that most customers are eager to get onto FinFETs.

“We do have products running at 20nm, but I think the design efforts will quickly go over to FinFET and we’ll see that be a much longer lived node with a lot more product tapeouts,” she said.

The companies say the 14nm FinFET offering could be up to 15% smaller than that available from other foundries due to aggressive gate pitch, smaller memory solution and innovative layout schemes for compact logic.

Hunter, having been a VP at Samsung before holding her current position at GLOBALFOUNDRIES, noted that the two companies, along with IBM, have been in collaboration for quite some time on “The Common Platform” at 65, 45, and 28nm nodes, but this announcement is strictly between GF and Samsung.

“We do continue to work with IBM in other areas at the Albany Nanotech center, where there is continuing collaboration on more advanced nodes, on materials research, pathfinding, and advanced module development kind of work,” she said.

Fabless customers use a single PDK to do a single design, allowing a single GDS file to be sent to either company. The design-for-manufacturing (DFM) and reticle-enhancement technologies (RET) needed at the 14nm node are challenging.

“We go deep into the collaboration, even to the OPC level and a lot of sharing on DFM as well. It is a very extensive collaboration,” confirmed Hunter. “At 14nm the designs are extremely complex, and to be able to truly supply multi-sourcing from one GDS, you have to have that level of collaboration to ensure that the output from all of our factories is the same. That’s a huge advantage to customers because the idea that you could source from two different companies without the kind of collaboration that GLOBALFOUNDRIES and Samsung are doing is just simply impossible when you get into 14nm FinFETs. When you get into the complexity of the designs, the databases, the amount of reticle enhancement techniques that are required to be able to print these geometries, you need to have that kind of in-depth collaboration.”

Low said that the two companies have a “fabsync” structure running in the background to ensure the fabs are fully synchronized.

“There are a couple of things we are doing proactively,” he said. “The technology teams are deeply engaged with each other. We have technology workshops across both companies. We have test chips that are run regularly to ensure that the process continues to stay synchronized. These test chips are not just simple transistors. We have product level elements that we’ve included to make sure we measure the critical parameters. This is only enabled through open sharing of technology information.”

Hunter adds: “We run the same test chips, we share wafers back and forth to measure each other’s products to make sure all of our equipment is calibrated, test equipment calibrated, results are the same on exactly the same test chip.We have test-chips with product-level structures that run in all fabs and both companies share all data to ensure that all fabs stay in alignment. Not just SPICE models and SRAMs, but full chip-like design features.”

However, customers will have to re-do lithography masks if they want to move manufacturing from one company to the other, in part because of issues with shipping masks. Kevin Low, Samsung’s senior director of marketing, commented, “We’ll be providing our customers choice and secure supply. At Samsung we have capacity in Texas and Korea.”

Cost/transistor for 14nm may not be lower compared to 20nm and 28nm. Hunter said, “To continue with optical lithography, it is challenging to do double-patterning and keep costs low.” However, since much of the motivation in moving from 20nm to 14nm is for power-sipping mobile SoCs, by reducing the power consumption by the claimed 35% there could be cost-savings at the packaging level such that the overall product cost is reduced.

To be able to offer essentially the same manufacturing process to customers, GLOBALFOUNDRIES and Samsung had to harmonize not just process recipes but many of the OEM tools used in these fabs.

Hunter says, “To get the same results at this node, it does require engineering down to the tool level and the individual recipe level. That doesn’t mean all tools are exactly the same, however, since cost and availability of tools may have been different when the fabs were equipped.”

Customers can choose which foundry that choose to work with, and then they can choose to discuss commercial terms such as which specific foundry site may be booked to do the work.

The Week in Review: March 28, 2014

Friday, March 28th, 2014

Altera Corporation and Intel Corporation announced their collaboration on the development of multi-die devices that leverage Intel’s package and assembly capabilities and Altera’s leading-edge programmable logic technology. The collaboration is an extension of the foundry relationship between Altera and Intel, in which Intel is manufacturing Altera’s Stratix 10 FPGAs and SoCs using the 14nm Tri-Gate process. Altera’s work with Intel will enable the development of multi-die devices that efficiently integrates monolithic 14nm Stratix 10 FPGAs and SoCs with other advanced components, which may include DRAM, SRAM, ASICs, processors and analog components, in a single package.

Samsung introduced a new lineup of flip chip LED packages and modules offering enhanced design flexibility and a high degree of reliability. The new offerings, for use in leading-edge LED lighting such as LED bulbs, MR/PAR and downlights, will be available in the market during the second quarter of this year. Samsung’s new flip chip (FC) LED package and flip chip on module (FCOM) solutions feature highly efficient and versatile LED structures, created by flipping over blue LED chips and adhering phosphor film to each of them. Unlike conventional LED packages that dispense phosphor and then place a plastic mold over each chip, Samsung’s FC package technology can produce LED packages down to a chip-scale size without any mold, enabling more compact lighting fixture designs.

eInfochips, a semiconductor and product engineering company, this week launched design services for chips based on 16nm geometry. The comprehensive suite of services includes Netlist to GDSII, Sign-off, and Design for Testability. eInfochips is one of the few engineering services companies in the world capable of delivering 16nm chip designs which reduce a chip’s power consumption by half, while improving performance by one-third over 28nm technology.

SEMATECH announced this week that Particle Measuring Systems has joined SEMATECH to advance the development of nanoscale particle removal processes and cleaning technologies for next-generation wafers and devices. This collaboration will address many of the profound changes taking place in the semiconductor industry that are impacting fundamental aspects of process and equipment design, including integration of new materials and process technology for sub-20nm node manufacturing, next-generation lithography requirements.

CEA-Leti will demonstrate its new prototype for wireless high data rate Li-Fi (light fidelity) transmission at Light + Building 2014 in Frankfurt, Germany, March 30-April 4. The technology employs the high-frequency modulation capabilities of light-emitting diode (LED) engines used in commercial lighting. It achieves throughputs of up to 10Mb/s at a range of three meters, suitable for HD video streaming or Internet browsing, using light power of less than 1,000 lumens and with direct or even indirect lighting. With this first proof of concept and its expertise in RF communications, Leti forecasts data transmission rates in excess of 100Mb/s with traditional lighting based on LED lamps using this technology approach and without altering the high-performance lighting characteristics.

Solid State Watch: February 14-20, 2014

Friday, February 21st, 2014
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Experts At The Table: Commercial potential and production challenges for 3D NAND memory technology

Thursday, February 6th, 2014

The last six months have seen several developments concerning 3D memory concepts moving into production, from companies such as Samsung, Micron, Toshiba and Sandisk. What follows are excerpts from a roundtable discussion with SemiMD, Samsung Electronics (SE) in South Korea, which has begun production of its proprietary 3D NAND technology, Bradley Howard, Vice President of Advanced Technology Group, Etch Business Unit, at Applied Materials and Jim Handy from Objective Analysis, which specialises in coverage of the memory industry.

SemiMD: Where does 3D NAND fit into the long-term roadmap for memory technology and is there one technology most likely to dominate?

SE: We successfully came out with the industry’s first 3D NAND (V-NAND) in August 2013, which offers 128 GB on a chip and vertically stacks cell layers that make use of charge trap flash (CTF) technology. The V-NAND has already been used in 960 GB solid state drives (SSDs) for server and enterprise applications.

The V-NAND technology is expected to replace planar NAND market gradually, starting from the high-end enterprise market. We will continue to come up with more advanced V-NAND products with higher density and reliability. The company has also been working on a diversity of next-generation memory technologies including RRAM (or ReRAM) while strengthening its future business competence.

Howard: All major memory customers have 3D NAND transition in their roadmap. We’ll soon see the first generation of 24-layer 3D cell array devices enter the market. RRAM and STT-MRAM technologies are further out from the market as there are still critical process and manufacturing challenges for both the materials and patterning.

Handy: NAND will dominate. 3D NAND is less disruptive than alternative technologies, like RRAM, since it involves the same materials that have been used to produce NAND for its entire lifetime, while RRAM, MRAM, FRAM and so on require new materials that are not as well understood. After 3D NAND has reached a limit and can no longer place increasing numbers of transistors onto a wafer then the door is opened for alternative technologies like RRAM, but that won’t happen until 2023.

How is the semi industry (such as foundries and designers) preparing for the transition to 3D memory?

Handy: The bulk of the semiconductor industry doesn’t need to transition since these technologies are only being used for the highest-density discrete memory chips. The most significant impact should be to the capital equipment market, where a move to 3D could increase materials equipment usage while decreasing spending on lithography tools.

SE: We are working closely with global IT companies in a wide range of fields to expand the market base and application of 3D V-NAND, and we expect that the market will grow rapidly throughout the year. The 3D V-NAND is expected to be adopted in many different applications including SSDs, high-density memory cards and other applications for consumer electronics. While Samsung will work on more V-NAND based applications, the company also will contribute to global IT companies’ development of next-generation IT systems using our 3D V-NAND products.

Are there specific tooling challenges that must be overcome?

SE: The key technologies for V-NAND would be applying 3D CTF structure for individual cells and constructing vertically interconnected cell arrays. We have mastered these technological challenges and will continue to come up with more advanced V-NAND products.

Howard: Fabricating vertically to build multilayer stacks of 3D NAND cells reduces the historical reliance on lithography as the dominant and limiting factor in scaling, and increases the role of materials-enabled deposition and etch to drive vertical scaling. This shift brings formidable device performance and yield challenges for deposition and etch technologies including distortion-free high aspect ratio etching, complex staircase patterning with precise step-width control, and uniform and repeatable deposition.

From a 3D NAND fab perspective, the changing balance of tool types toward significantly more deposition and etch equipment will have a substantial impact on tool footprint and fab layout to enable optimum manufacturing efficiency. Moreover, this new tool balance compromises the capability to adjust manufacturing capacity between NAND and DRAM since planar NAND and DRAM share a high level of commonality with regard to the balance of tool types and lithography.

Handy: For 3D NAND there are significant challenges in putting down layers that have uniform thickness across the entire wafer. There are also issues with pull-back etching for stairsteps that currently increase the lithography load more than was originally anticipated, but this issue should eventually be solved. For alternative technologies there will be issues in bringing new materials into the fab, some of which are antagonistic to the underlying silicon.

To what extent can 3D memory chips be scaled and what challenges does this pose?

Howard: Scaling for the first few generations, from 32 to 48 to 64 and higher cell layer stacks will largely be a matter of adding more vertical layers. The general consensus is that this is sustainable to around 100 device layers, and this will likely require some amount of reduction on the layer thicknesses to control the aspect ratios that must be etched. Even small reductions in thickness are critical, because any reduction gets multiplied by the number of layers. Scaling beyond this will likely require more effort towards thinning the layers through advancements on the device architecture.

Lithographic-based horizontal scaling will continue, but instead of the historical 15-20 percent CD reduction per generation, we expect planar scaling to slow dramatically, equivalent to a CD shrink more on the order of ~5 percent per generation. In addition, layout changes in the peripheral circuits to achieve more efficiency, along with more efficient designs for the complex staircase structure to allow for access to the different layers, are expected. These will all play a role in overall die size efficiency.

For deposition, major challenges to effectively scale vertically are advanced thickness and uniformity controls layer to layer. Any non-uniformity in a film layer will propagate throughout the stack as subsequent layers are deposited on top of it. With more layers in the device stack, this results is more devices potentially impacted by topography.

The challenge for etch is growing high aspect ratios despite a thinning down of individual layers in the stack. Aspect ratios today are already at 60:1. Achieving etch fidelity at such aspect ratios puts pressure on getting higher selectivity to the mask material which already is very thick. In some cases, the aspect ratio for the hard mask is already greater than 20:1, and this is the aspect ratio before even starting the etch into the device stack. While thinning the hard mask layer reduces the overall aspect ratio of the feature, new more resilient patterning films will be required. Higher selectivity will be through a combination of new materials with higher etch resistance and improvements to the etch process chemistry.

SE: We have core technologies to develop more advanced high-density V-NAND devices and are seeking to define manufacturing technologies for stacking more than 24-cell-layer structure which was applied to our first 3D V-NAND device.

The most advanced process technology for conventional NAND using floating gate would be 10 nm-class technology. However, process technology refers to the width of integrated circuitry that is used for NAND on a conventional planar structure. Applying the same considerations to our V-NAND would not be appropriate because the cell array structure has been totally changed.

For example, if we compare the wafer productivity of Samsung’s new 128 GB V-NAND to previous products, it has the approximate chip size of a conventional NAND that was built using approximately mid-10nm-class process technology.

The 3D V-NAND has its strength in scalability. There are plans to continue developing more advanced V-NAND products and applications including 1 TB and higher-density SSDs for servers and enterprise systems and other next-generation memory storage which should lead to the growth of the overall NAND flash market.

Handy: 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will probably find ways of placing these strings closer to each other through more aggressive lithography. There is a lot of room for scaling in 3D.

Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer. This is also true of the layers that are deposited on the walls of the hole. The entire issue of 3D is its phenomenal complexity.

The Week In Review: Jan. 10, 2014

Friday, January 10th, 2014

This week in Las Vegas, the 2014 International Consumer Electronics Show focused on the Internet of Things, displaying many connected gadgets and services. This year’s show featured more than 3,200 exhibitors, many of which were excited to show off new Internet-enable devices.

As of December 2013, Samsung had the most installed wafer capacity with nearly 1.9 million 200mm-equivalent wafers per month.  That represented 12.6 percent of the world’s total capacity and most of it used for the fabrication of DRAM and flash memory devices.  Next in line was the largest pure-play foundry in the world TSMC with about 1.5 million wafers per month capacity, or 10.0% of total worldwide capacity.  Following TSMC were memory IC suppliers Micron, Toshiba/SanDisk, and SK Hynix.

Xicato announced that it has relocated its San Jose headquarters to accommodate a new manufacturing line for the company’s next generation of products. The new 24 thousand-square-foot space is more than double the size of Xicato’s previous San Jose facility. The privately held company has invested millions of dollars in equipment and resources to meet the increasing global demand for its LED modules.

Toshiba Corporation announced the development of “Bright Mode,” a CMOS image sensor technology that allows smartphones and tablets to record full HD video at 240 frames per second (fps), the industry’s highest frame rate. “Bright Mode” realizes high quality slow motion playback.

The TOWA Corporation of Japan, a supplier of packaging equipment for semiconductor, electronics and LED industries, has decided to expand their activities in Europe with an Innovation Center for Packaging Development and announced the launch of TOWA Europe B.V.

Blog Review November 18 2013

Monday, November 18th, 2013

Dick James of Chipworks says that 28-nm samples they have seen from GLOBALFOUNDRIES and Samsung are remarkably similar, and ponders the possibility of Apple’s A7 chips being fabricated in New York in the not too distant future.

Recent progress in silicon photonics and optical interconnects is the focus of Pete Singer’s blog. Fujitsu and Intel recently demonstrated the world’s first Optical PCIe Express (OPCIe) based server, using Intel’s silicon photonics chip. Ludo Deferm of imec talks about what’s’ needed for intrachip optical communication.

Rich Wawrzyniak of Semico talks about what he learned from a discussion with Sundar Iyer, CEO of Memoir Systems, on the company’s new Pattern Aware Memory IP technology. Memoir has identified several different types of memory-processor operations and has created memories that perform these functions in the normal course of their operation within the system. In addition, this approach can save designers and device architects a considerable amount of die area, producing tangible power savings while increasing device performance.

Phil Garrou covers three new developments in the area of 3D integration this week. He looks at work from Leti/ST Microelectronics that explored the limits of conventional interconnects on RDL (vs damascene). They were able to achieve 8 µm line/spaces with high uniformity and reproducibility. He also reports on work from BESI and imec on thin wafer handling, and a new low temp via reveal process developed by SPTS.

3D-IC Testing With The Mentor Graphics Tessent Platform

Thursday, June 20th, 2013

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore’s Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time.

3D chips connected via interposers are in production at Xilinx, Samsung, IBM, and Sematech [1]. Interposers are providing the logical first step to industrialization of 3D based on through-silicon vias (TSV)s. The next generation of 3D integration incorporates TSV technology as the primary method of interconnect between the die.

To download this white paper, click here.

IEDM Preview: 20nm and Below

Sunday, November 11th, 2012

By Pete Singer

As the industry works to perfect 28nm devices in volume manufacturing and early 20nm processes, attention is focusing on next-generation 14nm and below technologies.

There have been three primary drivers in the semiconductor industry for the last four decades: Area, power/performance and cost. The well-known push to cram more functionality onto a single chip through continued scaling — or into a single package through 3D integration and other advanced packaging techniques — has been well documented. Today, with the exception of Intel, the industry’s leading edge devices in high volume manufacturing have critical dimensions of 28nm. Intel, racing ahead, introduced the 22nm IvyBridge chip in 2011 and has announced plans to have 14nm by the end of 2013. How long this kind of scaling can continue is the subject of some debate, with most recognizing the EUV lithography will be required at some point, most likely for the 10nm generation (Intel has said it doesn’t need it for 14nm).

It’s clear, though, that continued scaling is running out of steam, and that the industry most look for other means by which to say on the path defined by the proverbial “Moore’s Law.” Those advances are one of the primary focal points of the upcoming 58th annual IEEE International Electron Devices Meeting (IEDM), which will take place December 10-12, 2012 at the San Francisco Hilton Union Square. The conference will be preceded by a day of short courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.
As reported in last month’s issue, highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel’s unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM’s demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to ever smaller sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.

Following, we’ve assembled a list of the “be sure not to miss” papers and sessions slated for IEDM 2012.

Invited papers

In the plenary session, imec’s Luc Van den hove, will describe how ultimate transistor and memory technologies are the core of a sustainable society. He says that several key societal challenges in domains such as healthcare, energy, urbanization and mobility call for sustainable solutions that can be enabled by combining various technologies. These solutions will be backboned by wireless sensor systems, smart mobile devices and huge data centers and servers, the key constituents of a new information universe. They will require extreme computation and storage capabilities, bound by (ultra)low-power or heat dissipation constraints, depending on the application. This drives the need, he says, to keep on scaling transistor technologies by tuning the three technology knobs: power/performance, area and cost. To get to ultra-small dimensions, advanced patterning integration, new materials such as high-mobility Ge and III-V materials, and new device architectures such as fully depleted devices are being introduced. This comes along with an increasing need for process complexity reduction and variability control. Equally important are the continued R&D efforts in scaling memory technologies. NAND Flash, DRAM and SRAM memories are now approaching the point where new scaling constraints force exploration of new materials, cell architectures and even new memory concepts. This opens opportunities for resistance based memories such as resistive RAM, phase-change RAM or spin-torque transfer magneto resistive RAM.

In another invited paper, in the regular sessions, researchers from Micron and Intel will discuss scaling directions for 2D and 3D NAND Cells. They note that many 2D NAND scaling challenges are addressed by a planar floating gate (FG) cell, which has a smaller aspect ratio and less cell to cell interference. Figure 1 compares a wrap FG cell (left) and a planar FG cell (right). The wrap cell is limited by a required aspect ratio of >10 for both the wordline and the bitline direction in a sub-20nm cell. The planar cell eliminates this limitation.

Of course, not all IEDM presentations are focused on leading-edge logic and memory. In the plenary session, John Rogers from the University of Illinois at Urbana-Champaign, will talk on bio-integrated electronics. He notes that biology is curved, soft and elastic, while silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that require intimate integration with the human body. He plans to cover ideas for electronics, sensors and actuators that offer the performance of state-of-the-art, wafer-based systems but with the “mechanical properties of a rubber band.” He’ll explains the underlying materials science and mechanics of these approaches, and illustrate their use in bio-integrated, ’tissue-like’ devices with unique diagnostic and therapeutic capabilities, when conformally laminated onto the heart, brain or skin.In the third plenary talk, Joo-Tae Moon of Samsung Display will give a talk titled “State of the Art and Future Prospects in Display Technologies.” There are two parts which satisfy this vision, he notes. One is the picture quality and the other is design of the display. From picture quality point of view, bigger screen size and higher pixel density are the main factors. The need for a bigger screen size requires expediting technologies with lower RC delay and higher transistor performance. Higher pixel density mandates a smaller unit pixel area and each unit pixel has the dead space for the transistor and metal line which is protected from the light by the black matrix. Clearly, the design factor is the one of the main driving forces for the changes from CRT era to flat panel display era, he says.

Notable papers

imec, in a paper titled “Ultra Thin Hybrid Floating Gate and High-k Dielectric as IGD Enabler of Highly Scaled Planar NAND Flash Technology,” will describe — for the first time — a demonstration of ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4 nm with improved performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacture and scalability for high density memory application. Figure 2 is a TEM image of a polysilicon/TiN HFG cell. The stack consists of an ISSG tunnel oxide, a dual layer FG (PVD polysilicon + PVD TiN), a high-k IPD (ALD Al2O3) and an n-type polysilicon CG.

In a paper jointly authored by GLOBALFOUNDRIES and Samsung, titled “Stress Simulations for Optimal Mobility Group IV p- and n-MOS FinFETs for the 14 nm Node and Beyond,” researchers provide calculations of stress enhanced mobilities for n- and p-FinFETs with both Si and Ge channels for the 14nm node and beyond. Results indicate that both for nFETs and pFETs, Ge is “very interesting,” provided the correct stressors are used to boost mobility. Figure 3 is a XTEM of a Ge-channel FET with SiGe source/drain. They conclude that strained channels grown on a strain relaxed buffer is effective for 14nm nodes and scalable to future nodes. TCAD simulation trends are experimentally confirmed by nano-beam diffraction (NBD).

Luncheon presentation

Ajit Manocha, CEO, GLOBALFOUNDRIES, Inc. is sure to provide an interesting luncheon talk on Tuesday, December 11th, addressing some recent jabs from Intel’s Mark Bohr. The title of Manocha’s talk: “Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!”

Manocha says that industry experts and observers have predicted for a long time that the fabless model has some cracks in it, and may in fact be headed for extinction at some point. “We in the foundry industry dismissed such chatter as we continue to enjoy growth rates that outpace the overall semiconductor industry,” he notes in his pre-conference abstract. “But it wasn’t until an executive from — surprise — Intel officially declared the fabless model is collapsing recently that many of us really got our feathers ruffled. We firmly believe that the rumors of its death are greatly exaggerated. Evidence would seem to support that it is actually the IDM model which is dead, survived only by a very small number of anomalies that have either the financial wherewithal or stubbornness to continue down this path.”

The foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together, says Manocha. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy. Recent talks of fabless companies investing in their own fabs, and of foundries developing single company fabs’ underscore the sense of urgency. “Clearly, we must change – Call it Foundry 2.0,” he says.

Unprecedented technical and business challenges have driven semiconductor manufacturing to this new fork in the road. On the one side is the option to ‘go it alone’, an option available to less than a handful of companies. The temptation here is to circle the wagons, dig deep into the bank and develop an optimized, but relatively closed, solution that will hopefully work for most every need. Manocha said a second option, ironically, is a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies. “With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration ‘early, often and deep’ is really the only practical approach given the cost and complexities involved,” he said.

Evening panel

One of the two evening panels on Tuesday at 8pm is titled “The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?” The moderator will be Suresh Venkatesan of GLOBALFOUNDRIES. He notes that the 22nm node spelled the dawn of the fullly-depleted device architecture with the implementation of FinFETs as the workhorse of the technology. However, projecting out to the 10nm node and beyond the scalability of the FinFET architecture, the materials systems used to create it, and the fundamental electrostatics and parasitic components associated with the transistor once again loom large as significant challenges that need to be overcome.