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SPIE Photomask Technology Wrap-up

Tuesday, September 23rd, 2014

Extreme-ultraviolet lithography was a leading topic at the SPIE Photomask Technology conference and exhibition, held September 16-17-18 in Monterey, Calif., yet it wasn’t the only topic discussed and examined. Mask patterning, materials and process, metrology, and simulation, optical proximity correction (OPC), and mask data preparation were extensively covered in conference sessions and poster presentations.

Even with the wide variety of topics on offer at the Monterey Conference Center, many discussions circled back to EUV lithography. After years of its being hailed as the “magic bullet” in semiconductor manufacturing, industry executives and engineers are concerned that the technology will have a limited window of usefulness. Its continued delays have led some to write it off for the 10-nanometer and 7-nanometer process nodes.

EUV photomasks were the subject of three conference sessions and the focus of seven posters. There were four posters devoted to photomask inspection, an area of increasing concern as detecting and locating defects in a mask gets more difficult with existing technology.

The conference opened Tuesday, Sept. 16, with the keynote presentation by Martin van den Brink, the president and chief technology officer of ASML Holding. His talk, titled “Many Ways to Shrink: The Right Moves to 10 Nanometer and Beyond,” was clearly meant to provide some reassurance to the attendees that progress is being made with EUV.

He reported his company’s “30 percent improvement in overlay and focus” with its EUV systems in development. ASML has shipped six EUV systems to companies participating in the technology’s development (presumably including Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing, which have made equity investments in ASML), and it has five more being integrated at present, van den Brink said.

The light source being developed by ASML’s Cymer subsidiary has achieved an output of 77 watts, he said, and the company expects to raise that to 81 watts by the end of 2014. The key figure, however, remains 100 watts, which would enable the volume production of 1,000 wafers per day. No timeline on that goal was offered.

The ASML executive predicted that chips with 10nm features would mostly be fabricated with immersion lithography systems, with EUV handling the most critical layers. For 7nm chips, immersion lithography systems will need 34 steps to complete the patterning of the chip design, van den Brink said. At that process node, EUV will need only nine lithography steps to get the job done, he added.

Among other advances, EUV will require actinic mask inspection tools, according to van den Brink. Other speakers at the conference stressed this future requirement, while emphasizing that it is several years away in implementation.

Mask making is moving from detecting microscopic defects to an era of mesoscopic defects, according to Yalin Xiong of KLA-Tencor. Speaking during the “Mask Complexity: How to Solve the Issues?” panel discussion on Thursday, Sept. 18, Xiong said actinic mask inspection will be “available only later, and it’s going to be costly.” He predicted actinic tools will emerge by 2017 or 2018. “We think the right solution is the actinic solution,” Xiong concluded.

Peter Buck of Mentor Graphics, another panelist at the Sept. 18 session, said it was necessary to embrace mask complexity in the years to come. “Directed self-assembly has the same constraints as EUV and DUV (deep-ultraviolet),” he observed.

People in the semiconductor industry place high values on “good,” “fast,” and “cheap,” Buck noted. With the advent of EUV lithography and its accompanying challenges, one of those attributes will have to give way, he said, indicating cheapness was the likely victim.

Mask proximity correction (MPC) and Manhattanization will take on increasing importance, Buck predicted. “MPC methods can satisfy these complexities,” he said.

For all the concern about EUV and the ongoing work with that technology, the panelists looked ahead to the time when electron-beam lithography systems with multiple beams will become the litho workhorses of the future.

Mask-writing times were an issue touched upon by several panelists. Shusuke Yoshitake of NuFlare Technology reported hearing about a photomask design that took 60 hours to write. An extreme example, to be sure, but next-generation multi-beam mask writers will help on that front, he said.

Daniel Chalom of IMS Nanofabrication said that with 20nm chips, the current challenge is reduce mask-writing times to less than 15 hours.

In short, presenters at the SPIE conference were optimistic and positive about facing the many challenges in photomask design, manufacturing, inspection, metrology, and use. They are confident that the technical hurdles can be overcome in time, as they have in the past.

Blog review September 22, 2014

Monday, September 22nd, 2014

Siobhan Kenney of Applied Materials reports that The Tech Museum of Innovation announced the ten recipients of the Tech Awards. Presented by Applied Materials, this is a global program honoring innovators who use technology to benefit humanity. These incredible Laureates are addressing some of the world’s most critical problems with creativity – in naming their organizations and in designing solutions to improve the way people live.

Jean-Pierre Aubert, RF Marketing Manager, STMicroelectronics says RF-SOI is good for more than integrating RF switches.  Other key functions typically found inside RF Front-End Modules (FEM) like power amplifiers (PA), RF Energy Management, low-noise amplifiers (LNA), and passives also benefit from integration.

Phil Garrou blogs Samsung finally announced that it has started mass producing 64 GB DDR4, dual Inline memory modules (RDIMMs) that use 3D TSV technology. The new memory modules are designed for use with enterprise servers and cloud base solutions as well as with data center solutions [link]. The release is timed to match the transition from DDR3 to DDR4 throughout the server market.

Stephen Whalley, Chief Strategy Officer, MEMS Industry Group, blogs about the inaugural MIG Conference Shanghai, September 11-12th, with their local partners, the Shanghai Industrial Technology Research Institute (SITRI) and the Shanghai Institute of Microsystem and Information Technology (SIMIT).  The theme was the Internet of Things and how the MEMS and Sensors supply chain needs to evolve to address the explosive growth in China.

SEMI praised the bipartisan effort in the United States House of Representatives to pass H.R. 2996, the Revitalize American Manufacturing and Innovation (RAMI) Act.  SEMI further urged the Senate to move quickly on the legislation that would create public private partnerships to establish institutes for manufacturing innovation.

Jeff Wilson, Mentor Graphics, writes that in integrated circuit (IC) design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs that at the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.

The Week in Review: September 19, 2014

Friday, September 19th, 2014

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

North America-based manufacturers of semiconductor equipment posted $1.35 billion in orders worldwide in August 2014 (three-month average basis) and a book-to-bill ratio of 1.04, according to the August EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.04 means that $104 worth of orders were received for every $100 of product billed for the month.

Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs).

Samsung Electronics announced this week that it has begun mass producing its six gigabit (Gb) low-power double data rate 3 (LPDDR3) mobile DRAM, based on advanced 20 nanometer (nm) process technology. The new mobile memory chip will enable longer battery run-time and faster application loading on large screen mobile devices with higher resolution.

ProPlus Design Solutions, Inc. announced this week it expanded its sales operations to Europe.

Mentor Graphics this week announced the appointment of Glenn Perry to the role of vice president of the company’s Embedded Systems Division. The Mentor Graphics Embedded Systems Division enables embedded development for a variety of applications including automotive, industrial, smart energy, medical devices, and consumer electronics.

SPIE panel tackles mask complexity issues

Friday, September 19th, 2014

Photomasks that take two-and-a-half days to write. Mask data preparation that enters into Big Data territory. And what happens when extreme-ultraviolet lithography really, truly arrives?

These were among the issues addressed by eight panelists in a Thursday session at the SPIE Photomask Technology conference in Monterey, Calif. Participants in the “Mask Complexity: How to Solve the Issues?” panel discussion came from multiple segments of the photomask food chain, although only one, moderator Naoya Hayashi of Dai Nippon Printing, represented a company that actually makes masks.

The panelists were generally optimistic on prospects for resolving the various issues in question. Dong-Hoon Chung of Samsung Electronics said solutions to the thorny challenges in designing, preparing, and manufacturing masks were “not impossible.”

Bala Thumma of Synopsys said he was “going to take the optimistic view” regarding mask-making challenges. “Scaling is going to continue,” he added.

“We are not at the breaking point yet,” Thumma said. “Far from it!” Electronic design automation companies like Synopsys will continue to improve their software tools, he asserted. Mask manufacturers will also benefit from “strong partnerships” with vendors of semiconductor manufacturing equipment, and “strong support from semiconductor companies,” he said.

“There is a lot of complexity,” he acknowledged. Still, going by past experience, “this group of people has been able to work together and solve these issues,” Thumma concluded.

To resolve the issue of burgeoning data volumes in mask design and manufacture, Suichiro Ohara of Nippon Control System (NCS) proposed the solution of a unified data format – specifically MALY and OASIS.MASK software. Shusuke Yoshitake of NuFlare Technology later said, “OASIS is gaining, but GDSII still predominates.”

Several panelists took the long-term view and looked beyond the coming era of EUV lithography to when multiple-beam mask writers and actinic inspection of masks will be required. EUV and actinic technology, it was generally agreed, will arrive at the 7-nanometer process node, possibly in 2017 or 2018. Multi-beam mask writers are also several years away, it was said.

As the floor was opened to questions and comments, consultant Ken Rygler noted that commercial mask makers have “very low margins” and asked, “How does the mask maker pay for the inspection tools, the EDA, materials?” Yalin Xiong of KLA-Tencor said the mask business is in “a tough time economically.” He added, “We have to look at where the high-end business is going. Captive [mask shops] should step up.”

Blog review August 18, 2014

Monday, August 18th, 2014

Vivek Bakshi provides a deeper look at the ASML/IBM announcement on EUV progress. ASML and IBM reconfirmed the benchmarking in press and via social media. In short, 637 wafers per day throughput stands, resulting from the successful upgrade of source power by 100%, to its targeted level of ~43 W.

Dick James of Chipworks finally has his hands on Samsung’s V-NAND vertical flash. The vertical flash was first released in an enterprise solid-state drive (SSD) last year, in 960 GB and 480 GB versions. Then in May this year they announced a second-generation V-NAND SSD, with a stack of 32 cell layers.

Phil Garrou provides an overview of controlling warpage in packaging as discussed at ECTC by Hitachi Chemical, Amkor, Qualcomm, and imec.

Anand Sundaram, Senior Associate for PwC’s PRTM Management Consulting writes that software that controls and powers embedded devices is playing a key role in making possible the highly integrated, multi-functional ‘smart’ devices we take for granted in our daily lives – from the ubiquitous smart phones/tablet to ‘smart’ home appliances and wearable electronics.

Pete Singer posted an IoT infographic, courtesy of Jabil. The global IoT market is poised for explosive growth. By 2020, the market is expected to soar to $7.1 trillion. This infographic, courtesy of Jabil, gives an good overview of what will be connected (even garbage bins!).

Bob Smith, Senior Vice President of Marketing and Business Development, Uniquify blogs that these days, chip design may seem like an intricately connected jigsaw puzzle, including small, oddly shaped interlocking pieces.

3D memory for future nanoelectronic systems

Wednesday, June 18th, 2014

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By Ed Korczynski, Sr. Technical Editor

The future of 3D memory will be in application-specific packages and systems. That is how innovation continues when simple 2D scaling reaches atomic-limits, and deep work on applications is now part of what global research and development (R&D) consortium Imec does. Imec is now 30 years old, and the annual Imec Technology Forum held in the first week of June in Brussels, Belgium included fun birthday celebrations and very serious discussions of the detailed R&D needed to push nanoelectronics systems into health-care, energy, and communications markets.

3D memory will generally cost more than 2D memory, so generally a system must demand high speed or small size to mandate 3D. Communications devices and cloud servers need high speed memory. Mobile and portable personalized health monitors need low power memory. In most cases, the optimum solution does not necessarily need more bits, but perhaps faster bits or more reliable bits. This is why the Hybrid Memory Cube (HMC) provides >160Gb/sec data transfer with Through-Silicon Vias (TSV) through 3D stacked DRAM layers.

“We’re not adding 70-80% more bits like we used to per generation, or even the 40% recently,” explained Mark Durcan, chief executive officer of Micron Technology. “DRAM bits will only grow at the low to mid-20%.” With those numbers come hopes of more stability and less volatility in the DRAM business. Likewise, despite the bit growth rates of the recent past, NAND is moving to 30-40%  bit-increase per new ‘generation.’

“Moore’s Law is not over, it’s just slowing,” declared Durcan. “With NAND, we’re moving from planar to 3D, and the innovation is that there are different ways of doing 3D.” Figure 1 shows the six different options that Micron defines for 3D NAND. Micron plans for future success in the memory business to be not just about bit-growth, but about application-specific memory solutions.

Fig. 1: Different options for Vertical NAND (VNAND) Flash memory design, showing cell layouts and key specifications. (Source: Micron Technology)

E. S. Jung, executive vice president Samsung Electronics, presented an overview of how “Samsung’s Breaking the Limits of Semiconductor Technology for the Future” at the Imec forum. Samsung Semiconductor announced it’s first DRAM product in 1984, and has been improving it’s capabilities in design and manufacturing ever since. Samsung also sees the future of memory chips as part of application-specific systems, and suggests that all of the innovation in end-products we envision for the future cannot occur without semiconductor memory.

Samsung’s world leading 3D vertical-NAND (VNAND) chips are based on simultaneous innovation in three different aspects of materials and design:

1)    Material changed from floating-gate,

2)    Rotated structure from horizontal to vertical (and use Gate All Around), and

3)    Stacked layers.

To accomplish these results, partners were needed from OEM and specialty-materials suppliers during the R&D of the special new hard-mask process needed to be able to form 2.5B vias with extremely high aspect-ratios.

Rick Gottscho, executive vice president of the global products group Lam Research Corp., in an exclusive interview with SST/SemiMD, explained that with proper control of hardmask deposition and etch processes the inherent line-edge-roughness (LER) of photoresist (PR) can be reduced. This sort of integrated process module can be developed independently by an OEM like Lam Research, but proving it in a device structure with other complex materials interactions requires collaboration with other leading researchers, and so Lam Research is now part of a new ‘Supplier Hub’ relationship at Imec.

Luc Van den hove, president and chief executive officer of Imec, commented, “we have been working with equipment and materials suppliers form the beginning, but we’re upgrading into this new ‘Supplier Hub.’ In the past most of the development occurred at the suppliers’ facilities and then results moved to Imec. Last year we announced a new joint ‘patterning center’ with ASML, and they’re transferring about one hundred people from Leuven. Today we announced a major collaboration with Lam Research. This is not a new relationship, since we’ve been working with Lam for over 20 years, but we’re stepping it up to a new level.”

Commitment, competence, and compromise are all vital to functional collaboration according to Aart J. de Geus, chairman and co-chief executive officer of Synopsys. Since he has long lead a major electronic design automation (EDA) company, de Geus has seen electronics industry trends over the 30 years that Imec has been running. Today’s advanced systems designs require coordination among many different players within the electronics industry ecosystem (Figure 2), with EDA and manufacturing R&D holding the center of innovation.

Fig. 2: Semiconductor manufacturing and design drive technology innovation throughout the global electronics industry. (Source: Synopsys)

“The complexity of what is being built is so high that the guarantee that what has been built will work is a challenge,” cautioned de Geus. Complexity in systems is a multiplicative function of the number of components, not a simple summation. Consequently, design verification is the greatest challenge for complex System-on-Chips (SoC). Faster simulation has always been the way to speed up verification, and future hardware and software need co-optimization. “How do you debug this, because that is 70% of the design time today when working with SoCs containing re-used IP? This will be one of the limiters in terms of product schedules,” advised de Geus.

Whether HMC stacks of DRAM, VNAND, or newer memory technologies such as spintronics or Resistive RAM (RRAM), nanoscale electronic systems will use 3D memories to reduce volume and signal delays. “Today we’re investigating all of the technologies needed to advance IC manufacturing below 10nm,” said Van den hove. The future of 3D memories will be complex, but industry R&D collaboration is preparing the foundation to be able to build such complex structures.

DISCLAIMER:  Ed Korczynski has or had a consulting relationship with Lam Research.

Solid State Watch: May 30-June 5, 2014

Friday, June 6th, 2014
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The Week in Review: June 6, 2014

Friday, June 6th, 2014

After two years of decline, fab equipment spending for Front End facilities in 2014 is expected to increase 24 percent in 2014 (US$35.7 billion), according to the May 2014 SEMI World Fab Forecast Report released this week.

This week, the Society for Information Display (SID) unveiled the winners of its prestigious 19th annual Display Industry Awards.

The Semiconductor Industry Association (SIA) this week announced that worldwide sales of semiconductors reached $26.34 billion for the month of April 2014.

Imec announced this week that it is collaborating with Samsung Electronics to accelerate innovation and collaboration among technology companies and researchers working in the burgeoning mobile wearable field.

Synopsys, Inc. and Intel Corporation this week announced broad SoC design enablement for Intel’s 14nm Tri-Gate process technology for use by customers of Intel Custom Foundry.

Blog review June 2, 2014

Monday, June 2nd, 2014

The Internet of Things alone will surpass the PC, tablet and phone market combined by 2017, with a global internet device installed base of around 7,500,000,000 devices. Speaking at ASMC, TSMC’s John Lin said in addition to a continued push to smaller geometries and ultra-low power, the company will focus on “special” technologies such as image sensor, embedded DRAMs, high-voltage power ICs, RF, analog, and embedded flash. “All this will support all of the future Internet of Things,” he said.

Kavita Shah of Applied Materials blogs about the company’s new Volta system. She says desighed to alleviate roadblocks to copper interconnect scaling beyond the 2Xnm node through two enabling applications—a conformal cobalt liner and a selective cobalt capping layer, which together completely encapsulate the copper wiring.

In an interview, Christophe Maleville, Senior Vice President of Soitec’s Microelectronics Business Unit, talks about why FD-SOI provides a much better combination of power consumption, performance and cost than any alternative. Talking about Samsung’s move to FDSOI, he said “at 28nm, FD-SOI gets them an unprecedented combination of performance and power consumption for a cost comparable to that of standard low-power 28nm technology, making 28FD an extremely attractive alternative to any flavor of bulk CMOS at this node.”

Phil Garrou continues his analysis of presentations from the recent SEMI 2.5/3D IC forum in Singapore. In his third blog post on the topic, he reviews Nanium’s presentation “Wafer Level Fan-Out as Fine-Pitch Interposer” which focused on the premise that FO-WLP technology, eWLB, has closed the gap caused by the delay in the introduction of Si or glass interposers as mainstream high volume commodity technology.

Vivek Bakshi blogs that it takes a large infrastructure to make EUVL a manufacturing technology. So many tool suppliers, large and small, want to know when EUVL will be inserted into fabs for production and how and how much it will be used. Their business depends on these answers and some, especially smaller suppliers, are getting cold feet as delays in EUVL readiness continue. The answers to these questions mostly depend on knowing what we can expect from sources in the short- and near term, but there are many additional questions one must ask as well.

Karen Lightman of the MEMS Industry Group blogs about recent events in Japan, including the MIG Conference Japan. The focus of the conference was on navigating the challenges of the global MEMS supply chain. Several of the speakers gave their no-holds-barred view of these challenges, including the keynote from Sony Communications, Takeshi Ito, Chief Technology Officer, Head of Technology, Sony Mobile Communications.

The Week in Review: May 16, 2014

Friday, May 16th, 2014

On May 14, 2014, it was announced that STMicroelectronics and Samsung Electronics signed an agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The agreement includes ST’s fully developed process technology and design enablement ecosystem from its 300mm facility in Crolles, France. The Samsung 28nm FD-SOI process will be qualified in early 2015 for volume production.

Applied Materials announced its Applied Endura Volta CVD Cobalt system, the only tool capable of encapsulating copper interconnects in logic chips beyond the 28nm node by depositing precise, thin cobalt films.. The introduction of cobalt as a superior metal encapsulation film marks the most significant materials change to the interconnect in over 15 years.

Dow Corning introduced Dow Corning EE-3200 Low-Stress Silicone Encapsulant – the latest addition to its portfolio of advanced solutions designed to expand performance and durability of solar micro-inverters, power optimizers and other high value components.

Element Six today announced that its Gallium Nitride (GaN)-on-Diamond wafers have been proven by Raytheon Company to significantly outperform industry standard Gallium Nitride-on-Silicon Carbide (GaN-on-SiC) in RF devices.

A newly finalized Department of Defense (DoD) rule reduces the risk of counterfeit semiconductor products being used by our military by implementing needed safeguards in the procurement of semiconductors and other electronic parts.

Noel Technologies, a Silicon Valley specialty foundry offering process development and substrate fabrication, is now offering services for nanoimprint technology that reduce the costs of the nanoimprint stamps.

SEMATECH announced that researchers have reported progress which could significantly improve resist sensitivity by incorporating metal oxide nanoparticles for extreme ultraviolet (EUV) lithography, bringing the technology another step toward enabling the development of high performance resists required to enable EUV for high-volume manufacturing (HVM).

Mentor Graphics Corporation this week announced the new MicReD Industrial Power Tester 1500A for power cycling and thermal testing of electronics components to simulate and measure lifetime performance. The MicReD Industrial Power Tester 1500A tests the reliability of power electronic components that are increasingly used in industries such as automotive and transportation including hybrid and electrical vehicles and trains, power generation and converters, and renewable energy applications such as wind turbines.  It is the only commercially available thermal testing product that combines both power cycling and thermal transient measurements with structure function analysis while providing data for real-time failure-cause diagnostics.

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