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Mentor Graphics U2U Meeting April 26 in Santa Clara

Monday, April 11th, 2016

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Mentor Graphics’ User2User meeting will be held in Santa Clara on April 26, 2016. The meeting is a highly interactive, in-depth technical conference focused on real world experiences using Mentor tools to design leading-edge products.

Admission and parking for User2User is free and includes all technical sessions, lunch and a networking reception at the end of the day. Interested parties can register on-line in advance.

Wally Rhines, Chairman and CEO of Mentor Graphics, will kick things off at 9:00am with a keynote talk on “Merger Mania.“ Wally notes that in 2015, the transaction value of semiconductor mergers was at an all-time historic high.  What is much more remarkable is that the average size of the merging companies is five times as large as in the past five years, he said. This major change in the structure of the semiconductor industry suggests that there will be changes that affect everything from how we define and design products to how efficiently we develop and manufacture them. Dr. Rhines will examine the data and provide conclusions and predictions.

He will be followed by another keynote talk at 10:00 by Zach Shelby, VP of Marketing for the Internet of Things at ARM. Zach was co-founder of Sensinode, where he was CEO, CTO and Chief Nerd for the ground-breaking company before its acquisition by ARM. Before starting Sensinode, Zach led wireless networking research at the Centre for Wireless Communications and at the Technical Research Center of Finland.

After user sessions and lunch, a panel will convene at 1:00pm to address the topic “Ripple or Tidal Wave: What’s driving the next wave of innovation and semiconductor growth?” Technology innovation was once fueled by the personal computer, communications, and mobile devices. Large capital investment and startup funding was rewarded with market growth and increased silicon shipments. Things are certainly consolidating, perhaps slowing down in the semiconductor market, so what’s going to drive the next wave of growth?  What types of designs will be staffed and funded? Is it IoT?  Wearables?  Automotive?  Experts will address these and other questions and examine what is driving growth and what innovation is yet to come.

Attendees can pick from nine technical tracks focused on AMS Verification, Calibre I and II, Emulation, Functional Verification, High Speed, IC Digital Implementation, PCB Flow, and Silicon Test & Yield Solutions. You’ll hear cases studies directly from users and also updates from Mentor Graphics experts.

These user sessions will be held at 11:10-12:00am, 2:00-2:50pm and 3:10-5:00pm.

A few of the highlights:

  • Oracle’s use of advanced fill techniques for improving manufacturing yield
  • How Xilinx built a custom ESD verification methodology on the Calibre platform
  • Qualcomm used emulation for better RTL design exploration for power, leading to more accurate power analysis and sign-off at the gate level
  • Micron’s experience with emulation, a full environment for debug of SSD controller designs, plus future plans for emulation
  • Microsoft use of portable stimulus to increase productivity, automate the creation of high-quality stimulus, and increase design quality
  • Formal verification at MicroSemi to create a rigorous, pre-code check-in review process that prevents bugs from infecting the master RTL
  • A methodology for modeling, simulation of highly integrated multi-die package designs at SanDisk
  • How Samsung and nVidia use new Automatic RTL Floorplanning capabilities on their advanced SoC designs
  • Structure test at AMD: traditional ATPG and Cell-Aware ATPG flows, as well as verification flows and enhancements

Other users presenting include experts from Towerjazz, Broadcom, GLOBALFOUNDRIES, Silicon Creations, MaxLinear, Silicon Labs, Marvell, HiSilicon, Qualcomm, Soft Machines, Agilent, Samtec, Honewell, ST Microelectronics, SHLC, ViaSat, Optimum, NXP, ON Semiconductor and MCD.

The day winds up with a closing session and networking reception from 5:00-6:00pm.

Registration is from 8:00-9:00am in the morning.

EUV Resists and Stochastic Processes

Friday, March 4th, 2016

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By Ed Korczynski, Sr. Technical Editor

In an exclusive interview with Solid State Technology during SPIE-AL this year, imec Advanced Patterning Department Director Greg McIntyre said, “The big encouraging thing at the conference is the progress on EUV.” The event included a plenary presentation by TSMC Nanopatterning Technology Infrastructure Division Director and SPIE Fellow Anthony Yen on “EUV Lithography: From the Very Beginning to the Eve of Manufacturing.” TSMC is currently learning about EUVL using 10nm- and 7nm-node device test structures, with plans to deploy it for high volume manufacturing (HVM) of contact holes at the 5nm node. Intel researchers confirm that they plan to use EUVL in HVM for the 7nm node.

Recent improvements in EUV source technology— 80W source power had been shown by the end of 2014, 185W by the end of 2015, and 200W has now been shown by ASML—have been enabled by multiple laser pulses tuned to the best produce plasma from tin droplets. TSMC reports that 518 wafers per day were processed by their ASML EUV stepper, and the tool was available ~70% of the time. TSMC shows that a single EUVL process can create 46nm pitch lines/spaces using a complex 2D mask, as is needed for patterning the metal2 layer within multilevel on-chip interconnects.

To improve throughput in HVM, the resist sensitivity to the 13.54nm wavelength radiation of EUV needs to be improved, while the line-width roughness (LWR) specification must be held to low single-digit nm. With a 250W source and 25 mJ/cm2 resist sensitivity an EUV stepper should be able to process ~100 wafer-per-hour (wph), which should allow for affordable use when matched with other lithography technologies.

Researchers from Inpria—the company working on metal-oxide-based EUVL resists—looked at the absorption efficiencies of different resists, and found that the absorption of the metal oxide based resists was ≈ 4 to 5 times higher than that of the Chemically-Amplified Resist (CAR). The Figure shows that higher absorption allows for the use of proportionally thinner resist, which mitigates the issue of line collapse. Resist as thin as 18nm has been patterned over a 70nm thin Spin-On Carbon (SOC) layer without the need for another Bottom Anti-Reflective Coating (BARC). Inpria today can supply 26 mJ/cm2 resist that creates 4.6nm LWR over 140nm Depth of Focus (DoF).

To prevent pattern collapse, the thickness of resist is reduced proportionally to the minimum half-pitch (HP) of lines/spaces. (Source: JSR Micro)

JEIDEC researchers presented their summary of the trade-off between sensitivity and LWR for metal-oxide-based EUV resists:  ultra high sensitivity of 7 mJ/cm2 to pattern 17nm lines with 5.6nm LWR, or low sensitivity of 33 mJ/cm2 to pattern 23nm lines with 3.8nm LWR.

In a keynote presentation, Seong-Sue Kim of Samsung Electronics stated that, “Resist pattern defectivity remains the biggest issue. Metal-oxide resist development needs to be expedited.” The challenge is that defectivity at the nanometer-scale derives from “stochastics,” which means random processes that are not fully predictable.

Stochastics of Nanopatterning

Anna Lio, from Intel’s Portland Technology Development group, stated that the challenges of controlling resist stochastics, “could be the deal breaker.” Intel ran a 7-month test of vias made using EUVL, and found that via critical dimensions (CD), edge-placement-error (EPE), and chain resistances all showed good results compared to 193i. However, there are inherent control issues due to the random nature of phenomena involved in resist patterning:  incident “photons”, absorption, freed electrons, acid generation, acid quenching, protection groups, development processes, etc.

Stochastics for novel chemistries can only be controlled by understanding in detail the sources of variability. From first-principles, EUV resist reactions are not photon-chemistry, but are really radiation-chemistry with many different radiation paths and electrons which can be generated. If every via in an advanced logic IC must work then the failure rate must be on the order of 1 part-per-trillion (ppt), and stochastic variability from non-homogeneous chemistries must be eliminated.

Consider that for a CAR designed for 15mJ/cm2 sensitivity, there will be just:

145 photons/nm2 for 193, and

10 photons/nm2 for EUV.

To improve sensitivity and suppress failures from photon shot-noise, we need to increase resist absorption, and also re-consider chemical amplification mechanisms. “The requirements will be the same for any resist and any chemistry,” reminded Lio. “We need to evaluate all resists at the same exposure levels and at the same rules, and look at different features to show stochastics like in the tails of distributions. Resolution is important but stochastics will rule our world at the dimensions we’re dealing with.”

—E.K.

Optimism Reigns at SPIE Lithography Conference, Despite Challenges

Tuesday, February 23rd, 2016

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By Jeff Dorsch, Contributing Editor

Semiconductor manufacturing and design is growing increasingly complicated and just plain hard. Everyone knows that. The bad news is it’s only going to get worse.

Relax, there are many smart people gathered in San Jose, Calif., this week for the SPIE Advanced Lithography Symposium to discuss the challenges and figure out how to surmount them.

The changes required in lithography and related technologies to continue IC scaling promise to be painful and costly. Mitigating the pain and the cost is a common theme at the SPIE conference.

The annual SPIE Advanced Lithography conference is often dominated by discussions on the state of extreme-ultraviolet lithography (EUVL). In presentations on Sunday and Monday, the theme was generally the same as 2015 – EUV is making progress, yet it’s still not ready for high-volume semiconductor manufacturing.

Intel Fellow Mark Phillips said the technology has seen “two years of solid progress,” speaking Sunday at Nikon’s LithoVision 2016 event. He added, “There’s no change in Intel’s position: We’ll use EUV only when it’s ready.”

Anthony Yen of Taiwan Semiconductor Manufacturing covered the 30-year history of EUV development in his Monday morning presentation at the SPIE conference. Asked during the question-and-answer session following the presentation on when the world’s largest silicon foundry will use EUV, Yen stuck to the official company line of implementing EUV in production for the 7-nanometer process node, after some involvement at 10nm.

Seong-Sam Kim of Samsung Electronics also sees EUV realizing its long-aborning potential at 7nm, a node at which “argon fluoride multipatterning will hit the wall.” He touted the 80-watt power source Samsung has achieved with its NXE-3300 scanner from ASML Holding, saying it had maintained that level over more than eight months.

Intel’s Britt Turkot reported 200W source power “has been achieved recently,” and said the tin droplet generator in its ASML scanner has been significantly improved, increasing its typical lifetime by three times. EUV has demonstrated “solid progress,” she said, including ASML’s development of a membrane pellicle for EUV reticles.

While work with the ASML scanner on Intel’s 14nm pilot fab line has been “encouraging,” Turkot said, she added, “We do need to keep the momentum going.” Intel sees EUV entering into volume production with 7nm chips, according to Turkot. “It will be used when it’s ready,” she said.

EUV technology has shown “good progress” in productivity, while its availability and cost considerations have “a long way to go,” Turkot concluded, adding, “We need an actinic solution for the long term.”

An industry consensus has emerged that EUV will be used with ArF 193i immersion lithography in the near future, and this trend is likely to continue for some time, according to executives at the SPIE conference. There may also be wider adoption of directed self-assembly (DSA) and nanoimprint lithography technology, among other alternative lithography technologies.

Mark Phillips of Intel pointed to complementary implementation of EUV and 193i. “We must use EUV carefully,” he said. “We need to replace three-plus 193i masks.” Phillips added, “EUV can’t be applied everywhere affordably. 193i will continue to be used whenever possible.”

Nikon executives touted the capabilities of their new NSR-S631E ArF immersion scanner, introduced just before the SPIE conference. The new scanner can turn out 250 wafers per hour, and can be pushed to 270 wph with certain options, according to Nikon’s Ryoichi Kawaguchi.

Yuichi Shibazaki of Nikon said the company will next year introduce the S63xE scanner, improving on S631E.

For all the challenges of transitioning to 7nm and beyond, executives at SPIE remain optimistic about solving the issues of 193i multipatterning, DSA, and EUV. Harry Levinson of GlobalFoundries said in response to a question, “The ultimate resource is the human mind.”

Startup Works on Ultralow-k Materials for Chips, Displays

Monday, December 21st, 2015

By Jeff Dorsch, Contributing Editor

The very last presentation at the 12th annual 3D Advanced Semiconductor Integration and Packaging conference was given by Hash Pakbaz, president and chief executive officer of SBA Materials, a developer of nanoporous and mesoporous materials for semiconductor manufacturing and other applications.

After apologizing for his lack of expertise in chip packaging, Pakbaz laid out the case for using his Silicon Valley startup’s patented Liquid Phase Self Assembly technology for designing siloxane-based materials.

Based in San Jose, Calif., with an office in Albuquerque, N.M., SBA Materials has an impressive roster of investors – Intel Capital (through three rounds in two years), Samsung Venture Investment Corporation, Air Liquide Venture Capital, Tokyo Electron Venture Capital, Rock Hankin, William Cook (a co-founder and former CEO of the startup), Southern Cross Venture Partners, and Sun Mountain Capital. SBA Materials has not disclosed its total amount of venture funding, which extends over four rounds.

Materials with a low dielectric constant were first introduced more than a decade ago, and the semiconductor industry migration to making chips with 7-nanometer features will involve the integration of low-k materials, Pakbaz said at the 3D ASIP conference.

SBA’s goals are to “maintain existing composition” and “avoid random porosity,” Pakbaz said. With the LPSA technology, the company can offer low-k materials that are “not ordered and not random,” he added.

The films are spin-coated on a substrate, then subjected to a soft bake at 150 degrees C, according to Pakbaz. The resulting films can vary in thickness from 60 nanometers to 2 microns, he said.

“Our material is nice and sharp,” Pakbaz asserted. “Our material is quite stable.”

While SBA’s uLK advanced electronic materials are aimed at back-end-of-line and packaging applications in chip making, there are “applications beyond BEOL,” Pakbaz said at the conference.

“We see great promise for the LPSA material platform, not just in semiconductors, but also in various applications, including displays,” Dong-Su Kim, a vice president of Samsung Ventures America, said in a statement. He joined the SBA board of directors last year.

SBA has its material manufactured is Japan, Pakbaz noted, and it is working with imec in Belgium and Fraunhofer IPMS-CNT in Germany on development of its ultralow-k material.

China Bolsters its IC Gear Business with Mattson Acquisition

Thursday, December 10th, 2015

By Jeff Dorsch, Contributing Editor

Mattson Technology agreed this month to be acquired by Beijing E-Town Dragon Semiconductor Industry Investment Center, a limited partnership in China, for about $300 million in cash. The deal marks one of the first signs that the “Made in China 2025” policy will include targeting semiconductor production equipment as an element in bolstering the domestic chip business in the People’s Republic of China.

Brad Mattson, CEO

Mattson supplies dry strip, etch, millisecond anneal, and rapid thermal processing equipment for semiconductor manufacturing. The company was founded in 1988 by Brad Mattson, who earlier established Novellus Systems, acquired by Lam Research in 2012.

Mattson served as the company’s chief executive officer until 2001, and was its vice chairman until 2002. He later became a partner at VantagePoint Capital Partners and now serves as the CEO of Siva Power, a solar startup originally known as Solexant.

In 2014, Mattson Technology posted net income of $9.88 million on revenue of $178.4 million, after being unprofitable for the previous four years. Samsung Electronics accounted for about 61 percent of net revenue last year; Samsung and Taiwan Semiconductor Manufacturing were its leading customers in 2013.

China represented nearly 10 percent of Mattson’s revenue in 2014, a percentage that may rise once the acquisition transaction is completed in early 2016, pending shareholder and regulatory approval.

Mattson Technology has remained profitable this year, reporting net income of more than $2 million on revenue of $38.9 million for the third quarter ending September 27, compared with net income of $2.6 million on revenue of $43.3 million for the same quarter of 2014.

For the first nine months of 2015, the company posted net income of $10.9 million on revenue of $140.5 million, compared with net income of $4.9 million on revenue of $123.7 million in the like period of 2014.

In the dry strip market, Mattson competes with Lam Research and PSK. Its principal competitors in thermal annealing are Applied Materials, Dainippon Screen Manufacturing, and Ultratech. Etch rivals are Applied, Lam, and Tokyo Electron, according to Mattson’s 10-K annual report for 2014.

G. Dan Hutcheson, VLSI Research Inc.

“The Chinese are trying to develop their own semiconductor equipment business,” said G. Dan Hutcheson, chairman and CEO of VLSIresearch. Buying a company like Mattson is “a great way to start,” he added.

Recalling the 1980s, Hutcheson commented, “Mattson was one of the really go-go companies at the time.” There were 10 to 20 vendors in every segment, he recalled. With industry consolidation of equipment suppliers, “it’s become harder for companies like that,” he said. “You almost have to be a billion-dollar company” to stand out in the market these days, Hutcheson added.

Fusen Chen, Mattson’s president and CEO, “has been a shot in the arm, turning it around,” Hutcheson said about the company. “It’s hard to have differentiation from Applied and Lam.”

Noting the dominance of Samsung and TSMC among Mattson’s customer base, Hutcheson said, “There’s only three customers” – those two chipmakers and Intel. “Those guys can develop their own technology,” he added.

Having Mattson as an equipment supplier helps “keep the competition honest,” Hutcheson noted.

The veteran industry observer said such a deal is “good for the Chinese.” The country aspires to become a world leader in computers, networks and telecommunications, without having to import most of the semiconductors it needs. “You can’t do that without semiconductors,” Hutcheson added.

The fabless semiconductor business in China has grown tremendously in this decade. “No one’s graduating designers like China is,” Hutcheson said. “They get their PhDs in the U.S., their visas expire, and we tell them, ‘go back home.’”

China is following the example of South Korea and Taiwan in building up an electronics industry with a comprehensive supply chain, although not all Asian countries have done well in fostering semiconductor equipment vendors, according to Hutcheson.

“It’s a real classical error” to assume that semiconductor production equipment is merely hardware that is easy to design and manufacture, Hutcheson commented. “It’s not just stuff made in a machine shop,” he added, noting the need for extensive software in IC gear.

At its size, “Mattson is one of the last companies you can buy,” Hutcheson concluded.

InvenSense Developers Conference Tackles Sensor Security, New Technologies

Monday, November 23rd, 2015

By Jeff Dorsch, Contributing Editor

The second day of the InvenSense Developers Conference saw presenters get down to cases – use cases for sensors.

There were track sessions devoted to mobile technology and the Internet of Things, with the latter featuring presentations on industrial and automotive applications, smart homes and drones, smartphones and tablet computers, and wearable electronics. InvenSense partner companies had their own track on New Technologies, fitting into the conference’s “Internet of Sensors” theme.

The conference also featured two developer tracks in parallel, providing five InvenSense presentations on its FireFly hardware and software, SensorStudio, and other offerings.

One of the presentations that wrapped up the conference on Wednesday afternoon (November 18) was given by Pim Tuyls, chief executive officer of Intrinsic-ID, the Dutch company that worked with InvenSense to develop the TrustedSensor product, a secure sensor-based authentication system incorporating the FireFly system-on-a-chip device.

TrustedSensor will be shipped to alpha customers in the first quarter of 2016 and will go out to beta customers in the second quarter of next year, according to Tuyls. “This is real,” he said.

The Intrinsic-ID founder briefly reviewed the company’s history, to start. It was spun out of Royal Philips in 2008 and is an independent company with venture-capital funding, Tuyls noted.

Intrinsic-ID was founded to provide “cyber physical security based on physically unclonable function,” or PUF, Tuyls said. “We invented PUF,” he added. “It has been vetted by security labs and government agencies,” among other parties.

Taking “The Trusted Sensor” as his theme, the Intrinsic-ID CEO said, “Sensors are the first line of defense. You want to make sure you can provide a certain level of security.”

It is critical to achieve “the right balance” in designing, fabricating, and installing sensors, with security, flexibility, and low footprint among the key considerations, according to Tuyls.

While whimsically describing PUF as “a magic concept,” Tuyls noted, “Chips are physically unique,” with no two completely alike due to manufacturing processes.

PUF can “extract a crypto key from any device,” he added. “You can authenticate any device.”

Intrinsic-ID has tested the PUF technology with a wide variety of silicon foundries, Tuyls said – namely, Cypress Semiconductor, GlobalFoundries, IBM, Intel, Renesas Electronics, Samsung Electronics, Taiwan Semiconductor Manufacturing, and United Microelectronics. It has been implemented by Altera, Microsemi, NXP Semiconductors, Samsung, and Synopsys, he added, and process nodes ranging from 180 nanometers down to 14nm have been tested.

Tuyls concluded by emphasizing the importance of sensor security for the Internet of Things. “We should not wait; we should not try to save a few cents,” he said. “It is important, but it is hard.”

Earlier in the day, attendees heard from Sam Massih, InvenSense’s director of wearable sensors. “There’s a wearable solution for every part of the body,” he commented.

“Step count isn’t enough,” Massih said. “You need context for data.” He cited the example of a user who goes to the gym three times a week and spends an hour on the elliptical trainer machine for one hour on each visit.

“That’s data that can be monetized,” he said.

InvenSense announced last month that it would enter the market for automotive sensors. Amir Panush, the company’s head of automotive and IoT industrial, said in his presentation, “Sensors need to be smart enough.”

The megatrends in automotive electronics include the use of motion sensors for safety in advanced driver-assistance systems (ADAS), the smart connected car, and tough emission restrictions, according to Panush.

“We have signed a deal with a Tier One partner,” Panush said, meaning a leading automotive manufacturer, without identifying the company. “We are ramping up internal R&D in automotive.” InvenSense is presently opening design centers focusing on the $5 trillion automotive market, he added.

InvenSense was founded in 2003 and went public in 2011. The company posted revenue of $372 million in fiscal 2015 with a net loss of $1.08 million (primarily due to charging $10.55 million in interest expense against net income), after being profitable for the previous four years. InvenSense gets more than three-quarters of its revenue from mobile sensors and has a growing business in IoT sensors.

Customers in Asia accounted for 63 percent of the company’s fiscal 2015 revenue, according to InvenSense’s 10-K annual report. The company spent $90.6 million on research and development, representing about 24 percent of its net revenue.

GlobalFoundries and TSMC make nearly all of InvenSense’s wafers. Assembly packaging of its microelectromechanical system (MEMS) devices and sensors is outsourced to Advanced Semiconductor Engineering, Amkor Technology, Lingsen Precision Industries, and Siliconware Precision Industries.

The company had 644 employees as of March 29, 2015, with nearly half of them involved in R&D.

STMicroelectronics is InvenSense’s primary competitor for consumer motion sensors, the 10-K states, while the company also competes with Analog Devices, Epson Toyocom, Kionix, Knowles, Maxim Integrated Products, MEMSIC, Murata Manufacturing, Panasonic, Robert Bosch, and Sony.

Samsung Begins Mass Producing Industry First 256-Gigabit, 3D V-NAND

Tuesday, August 11th, 2015

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Samsung Electronics has begun mass producing the industry’s first 256-gigabit (Gb), three-dimensional (3D) Vertical NAND (V-NAND) flash memory based on 48 layers of 3-bit multi-level-cell (MLC) arrays for use in solid state drives (SSDs).

Samsung’s new 256Gb 3D V-NAND flash doubles the density of conventional 128Gb NAND flash chips. In addition to enabling 32 gigabytes (256 gigabits) of memory storage on a single die, the new chip will also easily double the capacity of Samsung’s existing SSD line-ups, and provide an ideal solution for multi-terabyte SSDs.

Samsung introduced its 2nd generation V-NAND (32-layer 3-bit MLC V-NAND) chips in August 2014, and launched its 3rd generation V-NAND (48-layer 3-bit MLC V-NAND) chips in just one year, in continuing to lead the 3D memory era.

In the new V-NAND chip, each cell utilizes the same 3D Charge Trap Flash (CTF) structure in which the cell arrays are stacked vertically to form a 48-storied mass that is electrically connected through some 1.8 billion channel holes punching through the arrays thanks to a special etching technology. In total, each chip contains over 85.3 billion cells. They each can store 3 bits of data, resulting 256 billion bits of data, in other words, 256Gb on a chip no larger than the tip of a finger.

A 48-layer 3-bit MLC 256Gb V-NAND flash chip delivers more than a 30 percent reduction in power compared to a 32-layer, 3-bit MLC, 128Gb V-NAND chip, when storing the same amount of data. During production, the new chip also achieves approximately 40 percent more productivity over its 32-layer predecessor, bringing much enhanced cost competitiveness to the SSD market, while mainly utilizing existing equipment.

Samsung plans to produce 3rd generation V-NAND throughout the remainder of 2015, to enable more accelerated adoption of terabyte-level SSDs. While now introducing SSDs with densities of two terabytes and above for consumers, Samsung also plans to increase its high-density SSD sales for the enterprise and data center storage markets with leading-edge PCIe NVMe and SAS interfaces.

Solid State Watch: July 31-August 6, 2015

Friday, August 7th, 2015
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Samsung to put 10nm chips into mass production by end of 2016

Friday, May 22nd, 2015

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By Jeff Dorsch, Contributing Editor

Samsung Semiconductor on Thursday announced that it will have 10-nanometer FinFET chips in volume production by the end of next year.

At an event in San Francisco, the Samsung Electronics subsidiary exhibited a 12-inch wafer with what it said were 10nm FinFET semiconductors. Over the next 18 months, Samsung will provide process design kits and multi-die wafers for the 10nm FinFET chips.

Samsung Semiconductor is also ramping up volume production of 14nm FinFET chips at its S1 wafer fabrication facility in South Korea and its S2 fab in Austin, Texas, while preparing the S3 fab in South Korea for 14nm FinFET volume production. In addition, GlobalFoundries will implement the Samsung 14nm FinFET process at its chip-making facilities in New York State.

“We are in business for 14-nanometer FinFET,” said Hong Hao, senior vice president for Samsung’s foundry business. “We have brought broad competition back into the foundry business.”

Samsung Foundry has closely matched Taiwan Semiconductor Manufacturing in providing 14nm and now 10nm chips.

Hao said Samsung will support “a broad range of applications” with chips coming out of its foundry fablines – consumer electronics, mobile devices, computing, networking, and data center infrastructure.

He also noted that Samsung is offering a 28nm fully-depleted silicon-on-insulator process, licensed from STMicroelectronics.

Samsung Semiconductor executives made brief presentations on other product areas for the chipmaker, and also reported on progress in constructing the company’s new facility in northern San Jose, Calif., which will be occupied this summer.

Proponents of EUV, immersion lithography face off at SPIE

Wednesday, February 25th, 2015

By Jeff Dorsch, contributing editor

The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium in San Jose, Calif.

Extreme-ultraviolet lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing.

On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

There are other lithography technologies being discussed at the conference, of course. They are bit players in the drama, so to speak, although there is a lot of discussion and buzz about directed self-assembly technology this week.

ASML broke big news on Tuesday morning, reporting that Taiwan Semiconductor Manufacturing was able to expose more than 1,000 wafers in one day this year with ASML’s NXE:3300B EUV system. “During a recent test run on an NXE:3300B EUV system we exposed 1,022 wafers in 24 hours with sustained power of over 90 watts,” Anthony Yen, TSMC’s director of research and development, said at SPIE.

While ASML was obviously and justifiably proud of this milestone, after achieving its 2014 goal of producing 500 wafers per day, it cautioned that more development remains for EUV technology.

“The test run at TSMC demonstrates the capability of the NXE:3300B scanner, and moves us closer to our stated target of sustained output of 1,000 wafers per day in 2015,” ASML’s Hans Meiling, vice president service and product marketing EUV, said in a statement. “We must continue to increase source power, improve system availability, and show this result at multiple customers over multiple days.”

The day before, Cymer announced the first shipment of its XLR 700ix light source, which is said to improver scanner throughput and process stability for manufacturing chips with 14-nanometer features. The company also debuted DynaPulse as an upgrade option for its OnPulse customers. The XLR 700ix and DynaPulse together are said to offer better on-wafer critical dimension uniformity and provide stable on-wafer performance.

Another revelation at SPIE is that SK Hynix has been working with the NXE:3300, too, and is pleased with the system’s capabilities. According to Chang-Moon Lim, who spoke Monday morning, SK Hynix was recently able to expose 1,670 wafers over three days, with uptime of 86.3 percent over that period.

“Progress has been significant on various aspects, which should not be overshadowed by the delay of [light] sources,” he said of ASML’s EUV systems.

The Korean chipmaker is exploring how it could work without pellicles on the EUV reticle, Lim noted. ASML has been developing a pellicle, made with polycrystalline silicon, in cooperation with Intel and others.

Nikon Precision and other Nikon subsidiaries didn’t issue any press releases at SPIE. The companies presented much information at Sunday’s LithoVision 2015 event, held at the City National Civic auditorium, across the street from the San Jose Convention Center, where SPIE Advanced Lithography is staged.

On offer at the Nikon conference was the claimed superiority of 193i immersion lithography equipment to EUV systems for the 14nm, 7nm and future process nodes. Donis Flagello, Nikon Research Corp. of America’s president, CEO, and chief operating officer, emphasized that message on Tuesday morning with an invited paper on “Evolving optical lithography without EUV.”

Nikon’s champion machine is the NSR-S630D immersion scanner, which was touted throughout the LithoVision event. The system is capable of exposing 250 wafers per hour, according to Nikon’s Yuichi Shibazaki.

Ryoichi Kawaguchi of Nikon told attendees, “EUV lithography needs more stability and improvement.” He also brought up the topic of manufacturing on 450-millimeter wafers, which has mostly gone ignored in the lithography competition. Nikon will ship a 450mm system this spring to the Global 450 Consortium in Albany, N.Y., Kawaguchi said. The bigger substrates could provide “an alternative option to reduce cost,” he added.

Erik Byers of Micron Technology observed, “EUV is not a panacea.”

Which lithography technology will prevail in high-volume manufacturing? The question may not be definitively answered for some time.

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