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Samsung Begins Mass Producing Industry First 256-Gigabit, 3D V-NAND

Tuesday, August 11th, 2015


Samsung Electronics has begun mass producing the industry’s first 256-gigabit (Gb), three-dimensional (3D) Vertical NAND (V-NAND) flash memory based on 48 layers of 3-bit multi-level-cell (MLC) arrays for use in solid state drives (SSDs).

Samsung’s new 256Gb 3D V-NAND flash doubles the density of conventional 128Gb NAND flash chips. In addition to enabling 32 gigabytes (256 gigabits) of memory storage on a single die, the new chip will also easily double the capacity of Samsung’s existing SSD line-ups, and provide an ideal solution for multi-terabyte SSDs.

Samsung introduced its 2nd generation V-NAND (32-layer 3-bit MLC V-NAND) chips in August 2014, and launched its 3rd generation V-NAND (48-layer 3-bit MLC V-NAND) chips in just one year, in continuing to lead the 3D memory era.

In the new V-NAND chip, each cell utilizes the same 3D Charge Trap Flash (CTF) structure in which the cell arrays are stacked vertically to form a 48-storied mass that is electrically connected through some 1.8 billion channel holes punching through the arrays thanks to a special etching technology. In total, each chip contains over 85.3 billion cells. They each can store 3 bits of data, resulting 256 billion bits of data, in other words, 256Gb on a chip no larger than the tip of a finger.

A 48-layer 3-bit MLC 256Gb V-NAND flash chip delivers more than a 30 percent reduction in power compared to a 32-layer, 3-bit MLC, 128Gb V-NAND chip, when storing the same amount of data. During production, the new chip also achieves approximately 40 percent more productivity over its 32-layer predecessor, bringing much enhanced cost competitiveness to the SSD market, while mainly utilizing existing equipment.

Samsung plans to produce 3rd generation V-NAND throughout the remainder of 2015, to enable more accelerated adoption of terabyte-level SSDs. While now introducing SSDs with densities of two terabytes and above for consumers, Samsung also plans to increase its high-density SSD sales for the enterprise and data center storage markets with leading-edge PCIe NVMe and SAS interfaces.

Solid State Watch: July 31-August 6, 2015

Friday, August 7th, 2015
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Samsung to put 10nm chips into mass production by end of 2016

Friday, May 22nd, 2015


By Jeff Dorsch, Contributing Editor

Samsung Semiconductor on Thursday announced that it will have 10-nanometer FinFET chips in volume production by the end of next year.

At an event in San Francisco, the Samsung Electronics subsidiary exhibited a 12-inch wafer with what it said were 10nm FinFET semiconductors. Over the next 18 months, Samsung will provide process design kits and multi-die wafers for the 10nm FinFET chips.

Samsung Semiconductor is also ramping up volume production of 14nm FinFET chips at its S1 wafer fabrication facility in South Korea and its S2 fab in Austin, Texas, while preparing the S3 fab in South Korea for 14nm FinFET volume production. In addition, GlobalFoundries will implement the Samsung 14nm FinFET process at its chip-making facilities in New York State.

“We are in business for 14-nanometer FinFET,” said Hong Hao, senior vice president for Samsung’s foundry business. “We have brought broad competition back into the foundry business.”

Samsung Foundry has closely matched Taiwan Semiconductor Manufacturing in providing 14nm and now 10nm chips.

Hao said Samsung will support “a broad range of applications” with chips coming out of its foundry fablines – consumer electronics, mobile devices, computing, networking, and data center infrastructure.

He also noted that Samsung is offering a 28nm fully-depleted silicon-on-insulator process, licensed from STMicroelectronics.

Samsung Semiconductor executives made brief presentations on other product areas for the chipmaker, and also reported on progress in constructing the company’s new facility in northern San Jose, Calif., which will be occupied this summer.

Proponents of EUV, immersion lithography face off at SPIE

Wednesday, February 25th, 2015

By Jeff Dorsch, contributing editor

The two main camps in optical lithography are arrayed for battle at the SPIE Advanced Lithography Symposium in San Jose, Calif.

Extreme-ultraviolet lithography, on one side, is represented by ASML Holding, its Cymer subsidiary, and ASML’s EUV customers, notably Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing.

On the other side is 193i immersion lithography, represented by Nikon and its customers, which also include Intel and other leading chipmakers.

There are other lithography technologies being discussed at the conference, of course. They are bit players in the drama, so to speak, although there is a lot of discussion and buzz about directed self-assembly technology this week.

ASML broke big news on Tuesday morning, reporting that Taiwan Semiconductor Manufacturing was able to expose more than 1,000 wafers in one day this year with ASML’s NXE:3300B EUV system. “During a recent test run on an NXE:3300B EUV system we exposed 1,022 wafers in 24 hours with sustained power of over 90 watts,” Anthony Yen, TSMC’s director of research and development, said at SPIE.

While ASML was obviously and justifiably proud of this milestone, after achieving its 2014 goal of producing 500 wafers per day, it cautioned that more development remains for EUV technology.

“The test run at TSMC demonstrates the capability of the NXE:3300B scanner, and moves us closer to our stated target of sustained output of 1,000 wafers per day in 2015,” ASML’s Hans Meiling, vice president service and product marketing EUV, said in a statement. “We must continue to increase source power, improve system availability, and show this result at multiple customers over multiple days.”

The day before, Cymer announced the first shipment of its XLR 700ix light source, which is said to improver scanner throughput and process stability for manufacturing chips with 14-nanometer features. The company also debuted DynaPulse as an upgrade option for its OnPulse customers. The XLR 700ix and DynaPulse together are said to offer better on-wafer critical dimension uniformity and provide stable on-wafer performance.

Another revelation at SPIE is that SK Hynix has been working with the NXE:3300, too, and is pleased with the system’s capabilities. According to Chang-Moon Lim, who spoke Monday morning, SK Hynix was recently able to expose 1,670 wafers over three days, with uptime of 86.3 percent over that period.

“Progress has been significant on various aspects, which should not be overshadowed by the delay of [light] sources,” he said of ASML’s EUV systems.

The Korean chipmaker is exploring how it could work without pellicles on the EUV reticle, Lim noted. ASML has been developing a pellicle, made with polycrystalline silicon, in cooperation with Intel and others.

Nikon Precision and other Nikon subsidiaries didn’t issue any press releases at SPIE. The companies presented much information at Sunday’s LithoVision 2015 event, held at the City National Civic auditorium, across the street from the San Jose Convention Center, where SPIE Advanced Lithography is staged.

On offer at the Nikon conference was the claimed superiority of 193i immersion lithography equipment to EUV systems for the 14nm, 7nm and future process nodes. Donis Flagello, Nikon Research Corp. of America’s president, CEO, and chief operating officer, emphasized that message on Tuesday morning with an invited paper on “Evolving optical lithography without EUV.”

Nikon’s champion machine is the NSR-S630D immersion scanner, which was touted throughout the LithoVision event. The system is capable of exposing 250 wafers per hour, according to Nikon’s Yuichi Shibazaki.

Ryoichi Kawaguchi of Nikon told attendees, “EUV lithography needs more stability and improvement.” He also brought up the topic of manufacturing on 450-millimeter wafers, which has mostly gone ignored in the lithography competition. Nikon will ship a 450mm system this spring to the Global 450 Consortium in Albany, N.Y., Kawaguchi said. The bigger substrates could provide “an alternative option to reduce cost,” he added.

Erik Byers of Micron Technology observed, “EUV is not a panacea.”

Which lithography technology will prevail in high-volume manufacturing? The question may not be definitively answered for some time.

Solid State Watch: February 13-19, 2015

Friday, February 20th, 2015
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SEMICON Show Highlights Chip Manufacturing in South Korea

Wednesday, February 4th, 2015


By Jeff Dorsch

The SEMICON Korea conference and exhibition opens Wednesday in Seoul for a three-day run. The show highlights the importance of semiconductor manufacturing in South Korea, home to two of the biggest memory chip makers in the world, Samsung Electronics and SK Hynix.

The DRAM market in 2014 posted a 34.7 percent increase in revenue, compared with 2013, as the total memory chip market grew 18.2 percent last year to $79.2 billion, according to World Semiconductor Trade Statistics. Samsung and Hynix together account for about two-thirds of the worldwide DRAM market, and South Korea holds 40 percent of the global memory output.

Semiconductor Equipment and Materials International forecasts Korean expenditures on front-end wafer fabrication equipment will be $7.8 billion in 2015, nearly 28 percent higher than 2014. Korean chipmakers will spend more than $14 billion on semiconductor equipment and materials this year, according to SEMI.

IC Insights estimates Samsung grew its semiconductor sales by 8 percent in 2014 to $37.26 billion, while Hynix boasted 22 percent growth to $15.84 billion, compared with the year before.

Samsung and Hynix (once the semiconductor arm of the Hyundai chaebol and now part of the SK Group) dominate the semiconductor scene in their home country, yet they aren’t the only chipmakers in South Korea. Dongbu HiTek is a specialty silicon foundry, emphasizing analog and mixed-signal chip fabrication. Its parent conglomerate, the Dongbu Group, has been seeking to sell its 37 percent ownership in the foundry for more than a year, without success. Samsung and Hynix haven’t been interested in Dongbu HiTek, although Samsung has a substantial foundry business, making chips for Apple and other customers. The LG Group at one point expressed interest in bidding for the Dongbu HiTek stake, but hasn’t advanced that interest.

There’s also MagnaChip Semiconductor, which designs and manufactures analog and mixed-signal chips for consumer applications. The company also provides foundry services.

SEMICON Korea is co-located with the LED Korea 2015 exhibition, featuring light-emitting diode manufacturing.

Applied Materials Introduces New Hardmask Process, Saphira

Monday, November 24th, 2014


A new hardmask material and process was introduced this month by Applied Materials. Designed for advanced logic and memories, including DRAM and vertical NAND, the hardmask is transparent, which simplifies processing. It also exhibits very high selectivity, low stress and good mechanical strength. It’s also ashable, so that it can be removed after etching is completed. Called Saphira, the process was developed in conjunction with Samsung and other customers. An Applied Materials-developed process for stripping the hardmask was licensed to Korea-based PSK.

Hardmasks are used for etching deep, high aspect ratio (HAR) features that conventional photoresists cannot withstand. Applied Materials first introduced an amorphous carbon hardmask in 2006, and now has a family of specialized films. The Advanced Patterning Films (APF) family now includes APFe, which enables deposition of thicker layers than APF (e.g., in capacitor formation and metal contacts for memory devices), and APFx, design to address patterning of metal lines and contacts at 5xnm and beyond.

The new Saphira APF process – which runs on the Applied Materials Producer XP Precision CVD chamber and works with PSK’s OMNIS Asher systems — introduces new film properties that include greater selectivity and transparency. The Saphira APF deposition and resolve major issues to improve patterning of more complex device structures at advanced technology nodes. “It’s a materials solutions,” said Terry Lee, vice president of strategy and marketing for the dielectrics systems and modules group at Applied Materials. “It’s delivered with the patterning film itself, Saphira, as well as the combination of technologies and processes, whether it’s in the CVD chamber or etch chamber, reducing process steps and simplifying process complexity.

Applied Materials isn’t saying exactly what the Saphira hardmask is composed of, but a recent patent filing describes it as boron-rich amorphous carbon layer. The patent notes that, compared to carbonaceous masking layers, boron-doped carbonaceous layers, which include between 1 wt. % and 40 wt. % boron provide even greater etch resistance.

Lee said the Saphira film “In general behaves very much like a ceramic. But unlike most ceramics, it’s ashable. It’s structurally hard like a ceramic, but it’s ashable like our standard carbon hard mask,” he said.

In general, the selectivity of Saphira is twice the conventional masking materials on the open market, Lee said.

The new process reduces process complexity and cost in a couple of different ways. Because it’s transparent, no extra step is needed to open the mask to find the alignment mark. And because the film has high selectivity, fewer masking steps are required. That all reduces the process complexity. Lee said that with conventional masks, in order to mask these high aspect ratio features, a thicker mask material is often needed. “When you have a thicker mask and you need to etch fine features, what you wind up with is a very narrow mask. In order to prevent the mask itself from collapsing or titling, you need very strong mechanical strength. With Saphira, we have that high mechanical strength and it resists the deformation,” he said.

Saphira can also reduce the need for multiple hardmasks. “Instead of having the hardmask, oxide and poly (see figure), it drops down to a one mask that’s thinner because the selectivity is higher,” Lee explained. “What we’re seeing is that we can reduce around 20 steps. When you reduce steps, you reduce cost. What we’re seeing based on our calculations is something like 35% reduction in cost of this one module. Across multiple modules, that adds up to a lot of money,” he added.

Solid State Watch: October 31-November 6, 2014

Monday, November 10th, 2014
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The Week in Review: October 10, 2014

Friday, October 10th, 2014

Samsung Electronics announced plans on Monday to invest $14.7 billion (15.6 trillion Korean won) in a new semiconductor fabrication facility in Pyeongtaek, South Korea to meet growing demand from smartphones, enterprise computing and the emerging “Internet of Things” market.

Soraa, a developer of GaN on GaN LED technology, announced today that one of its founders, Dr. Shuji Nakamura, has been awarded the 2014 Nobel Prize in Physics. Recognizing that Nakamura’s invention, the blue light emitting diode (LED), represents a critical advancement in LED lighting, the Nobel committee explained the innovation “has enabled bright and energy-saving white light sources.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, today announced that John P. Daane, President, CEO, and Chairman of the Board of Altera, has been named the 2014 recipient of SIA’s highest honor, the Robert N. Noyce Award.

The Board of Directors of United Microelectronics Corporation (UMC), a global semiconductor foundry, this week announced a joint venture company focused on 12″ wafer foundry services with Xiamen Municipal People’s Government and FuJian Electronics & Information Group.

Emergence of new wide bandgap (WBG) technologies such as SiC and GaN materials will definitely reshape part of the established power electronics industry, according to Yole Développement (Yole).

Wrap-up: SEMI’s Strategic Materials Conference

Tuesday, October 7th, 2014

SEMI’s Strategic Materials Conference was held September 30-October 1, 2014, in Santa Clara, CA at the Biltmore hotel.

By Karey Holland, Techcet Group

The 2014 Strategic Materials Conference was very well attended.  There were people from several of the leading IC makers as well as suppliers of equipment and materials to the fabs.  Unfortunately, the audio and video systems were not stellar, so we had to endure some ear shattering system noise, and any light image was not visible on the screens.  Otherwise, the venue was good.  Throughout the conference, several themes were repeated.

Focus on the stability we hope for in post 2013 times, but concern about volatility and uncertainty of the world economics, esp. the recession-like growth numbers in Europe and Japan expected for the next few years. While forecasters (Gartner, IC Insights, VLSI Research, Linx, Techcet Group and others) anticipate IC wafer starts growing at ≥6% CAGR over the next 5 years, there is concern that any number of geo political world problems could throw us back into a global recession.  Attendees had a greater concern than the presenters over the possibility of a future recession, and that the impact would be greater to IC industry now due to the entrenchment of mobile platforms.

Focus on cost of lithography as a driver for increased cost of leading edge MCUs/MPUs … with current nodes, multi-patterning requires many more expose/develop/dep/etch steps than EUV, but EUV has not yet met the requirements for manufacturing implementation.  It is likely that EUV will first be used for only a few critical layers.  DSA (directed self-assembly) may be used also for a few selected critical layers, but issues of defects will likely keep it from use in many layers.

Focus on the expected (and currently numerous options) for advanced devices and implications for materials.  This includes advanced packaging technologies.

450mm wafers may continue to slip, if the other large IC makers (e.g. TSMC, Samsung, GlobalFoundries) don’t agree with Intel on first implementation date/node. Collaboration across the entire ecosystem was stressed for 450mm to become a reality.

Below are things I found particularly interesting in the presentations and/or at the end of day panel discussions.

The key note presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm.  He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices; a perfect start to SMC 2014.  Qualcomm defines the Digital 6th Sense Era is “the augmentation of human ability”, or as Sue Davis put it “intelligent data based extension of our 5 senses ==>to a 6th“. Essentially this is where the ability of the IoT/IoE data feedback can act as our 6th sense by capturing data about one & one’s environment which results in  prediction/information being shared based on data collection and/or user selections regarding the environment around us (or about us, e.g., tele-health).”  Because the smartphone is the “most pervasive platform ever” (US Android users average 106 Apps launched/day), it can serve as a remote connection to the IoT world … be that monitoring our health, schedules, honey-do lists, and improving our understanding and enjoyment of the world around us.  For advanced logic one might expect, lithography for advanced ICs (quad patterning vs EUV) were discussed as key cost drivers.  Other required/expected advanced materials include high mobility channel materials and thin barrier metals (likely Co). Beyond CMOS, new structures and materials may be required to support sensors (bio, chemical, fluidic), nano batteries, piezo, thermal, and solar harvesters.

Mark Thirsk, Linx-Consulting, reviewed IC growth and lack thereof for past years, and observed that 2014 will be “first good year in 8 years” (since 2006), and forecast 6-8% CAGR for the next few years – strongly dependent on the success of the IoT.  IC market growth since 2010 correlates strongly to GDP since 2010, and thus regional GDP differences (e.g. the current European recession) are reflected in IC demand.  Technology challenges & opportunities in for the next 5+ years include advanced logic (3D NAND, and new memory method after 2018), numerous AL (atomic layer) processes, 3D / advanced packaging, patterning efficiency, and complexity.  The electronic materials landscape is changing: the supply chain is merging, and there are new entrants (esp. from Korea, Taiwan & China) in advanced materials such as photoresists. Interestingly, China appears to be focusing more on investing in fabless than fabs.

Duncan Meldrum, Hilltop Economics, said that the current subdued market growth (3% 2013-16) is due to more fiscal responsible people. China & Asia are growing 4 to 7.7%, US & Latin America about 2.1 to 3.1, Euro <2%, and Japan ~1.5%.  The tax increase in Japan is having a very negative impact. He expects the US to see a 5% year over year improvement (very good news) with our investments finally growing in 2nd half of 2014.  He anticipates healthy, but not stellar consumer spending through 2016.

Patrick Ho, Stifel Nicolas, initially discussed that for companies that follow Moore’s Law, that it is increasingly Fab capital intensity (Capex) with addition of FinFETs, new materials (e.g. High k), 3D NAND, and Multi-Patterning (from delayed EUV).  One can assume this will continue to be the case as CMOS devices moves from Si channel to replacement channel filled with SiGe, Ge, or III-V and memories move to new technologies such as ReRAM, STTRAM, etc.  His observation is that only Intel is pulling for 450mm, and if TSMC & Samsung don’t exert more pull, 450mm may not happen (esp. in light of the negative impact to equipment revenue per square inch of silicon).  The top 4 OEMs (ASML, KLA-T, Lam, AMAT) are large enough to push back on the top 3 IC makers, and that consolidation is continuing.  Patrick noted that all 4 top OEMs have dividends, and he anticipates that they will eventually get better valuations.  He showed a nice list of companies he thinks are acquisition candidates (CMC, Nanometrics, Nikon, Nova, Axcelis, Rudolph, Veeco, FormFactor, and Ultratech).  Other comments:  Moore’s law lives, but is under stress.  Innovation w/ or w/o EUV will bring industry back to Moore’s Law.  Changing landscape will help economics of leading players.

Ross Kozarsky, who leads Lux Research’s advanced materials team, discussed the longer range materials he investigates such as graphene, 3D printing, and Meta-materials. Graphene film sheets are of interest for transparent conductive materials (e.g. touchscreens), possibly moving to FETs & sensors.  3D printing has been around 30 yrs; today it’s used mostly for prototyping, but manufacturing use makes sense and could really increase total growth.  Multifunctional and multi-materials printers will be needed.  Autonomous cars are now a big growth opportunity, opening great opportunity for chemical and material companies to innovate.

Geraud Duboix, IBM Almaden, develops porous low k materials for interconnect passivation and their integration (esp. plasma damage).  In the 0.65 to 0.1um timeframe, interconnect RC delay was slowing devices even though the transistors were getting faster, and thus began the drive for lower k insulators.  The ITRS has been showing the need for lower k since its inception, but it also has pushed out the date of the more aggressive low ks.  Initially to achieve lower k, C and F were added to SiO2 to break-up network structure.  Today, they are driving low k down by adding porosity.  Once a big concern, Geraud said that ULK mechanical properties are now no longer a concern with UV treatment, the lowest k being integrated is 2.3-2.4, and new low k materials are emerging. Geraud is working on porous low k materials, to achieve lower k, and larger pores deliver lower k.  He discussed the various pore-sizes in evaluation, the importance of porogens (material in the low k deposition that is later removed to create pores) and methods being used to seal the created pores (especially before conformal barrier metal deposition).  Interestingly, he commented that creating and sealing the larger pores is somewhat easier, although he’s being asked to work on the smaller pores for now.  During the panel discussion Mansour Moinpour (Intel) asked why Geraud was working on smaller pores that are more difficult to fill. Geraud responded that for the designers insulators with 2.0 or 1.8 k would be too big a change and they want 2.4 and 2.2 first.

Todd Younkin, from Intel’s central research (components) novel materials group, discussed that the industry will continue CMOS Scaling through 7nm. As stated by others, lithography is a challenge and using several methods to accomplish patterning, while productivity and pattern placement (alignment) are concerns.  Intel is working on devices with channels of higher mobility materials that Si (III-V or MoS2) as well as beyond CMOS (e.g., GAA) devices.  Todd said that early in device research development, Intel works to make sure manufacturing should be capable of meeting cost expectations. These include the cost of multi-patterning versus EUV, ultra-low k interconnect materials, etc.

Angela Franklin, of TriQuint (recently renamed Qorvo) discussed the challenges of supply management (and unlike others, she projects well when talking, so we could avoid the audio system problems … thanks Angela!).  Angela educated the audience about Qorvo devices (some look more like MEMS with permanent epoxy “cavity” structures that resonate w/ the RF) which are significantly different from the leading edge logic and non-volatile most of us follow.  Unlike the device manufactures that use Si, Qorvo uses smaller substrates of III-V and GaN.  Many films are already on the substrates when purchased.  The fab process is very solvent intensive, and only 1/3 aqueous.  Unlike others, Qorvo uses significant eBeam lithography with up to 28 different resists and many negative resists, as well as metal lift-off (my first job at IBM >30 yrs ago).

Prof. Philip Wong of Stanford gave his typical dynamic and mind-stretching presentation. His discussion was focused on the single digit nodes, and the possible new channel materials for logic (III-V or 2D MoS2, MoSe2, WSe2, WTe2 or ??) and possible new devices, including carbon nanotube FET (CNFET), STTRAM, CBRAM, ReRAM (using HfOx, TaOx, TiOx).  He said that memory chips will hold 32Tbits.  He then smiled and said “none of this before the next 10 years”.  He showed some exciting interleaved memory and logic ideas using a base of 2D or 3D FETs, topped by STTRAM, then 2D or 3D FETs, and then 3D RRAM.  Because the interconnects of the bottom device are present, all processing for the others must be at low temperature (<400C).

Discussion Panel.  When asked about collaboration with materials suppliers, Intel and IBM research had significantly different responses.  Intel invests dollars and works with graduate students on advanced projects and hopefully a “lucky accident” brings advances.  IBM research mentioned that legal issues often get in the way of collaboration with suppliers.

Notes for SMC Day 2 2014 Blog

Tim Hendry, from Intel’s supply management team started off day 2.  A large concern he brought up was what he described as the widening connections between fab, material suppliers, and sub-suppliers.  He then discussed the concerns and possible ways to improve connections, as well as the importance of metrology and verification of chemical quality.  Unfortunately, some of the sub-suppliers are very big chemical companies that have difficulty getting excited about the low volume materials used to make ICs.  He finished up by saying that Intel is focused on controlling the costs of manufacturing that require close partnerships with materials suppliers. Intel is driving for unprecedented collaboration among the materials and sub tier suppliers to achieve cost, performance and defect targets.  The cost of packaging and shipping materials globally is driving investigation into new operating models to cut costs.

Dennis Hausmann of LamRC/NVLS discussed ALD/CVD in more details than others.  For Each CVD/ALD step, an average of $2-$3/wafer is added to manufacturing cost, while only about $1/wafer of this is for chemistry+power+exhaust management.  He reviewed at least 4 versions of ALD tools (furnaces to single wafer) and said that there is a “right ALD tool” for the right deposition job.  He said that single wafer tools with proper development can meet same throughput as batch furnaces.  However, if you look at the development cost, single wafer tools are much better in cost.  For depositions that improve with plasma ALD, single wafer tools also make sense.  An important observation by Dennis was that for ALD, sometimes it is the unknown contaminant that “makes it go”.  This is something that has been observed in the past of copper plating chemistries, as well as some CMP slurries.

James ONeil, CTO Entegris had an interesting title, which should fit most suppliers “Accelerating yield in a disruptive environment”.  James emphasized that suppliers need meaningful process discussions, insights & collaboration with their customers.

Adrienne Pierce of Edwards introduced SCIS collaboration to most of us.  This is a supply chain collaboration working group.  Some topics are tracing defects origins and BKMs for specific process (e.g. ALD).

There were then two parallel sessions; one on advanced memories and the other on 3D packaging.  In the memory session, Norma Sosa of IBM talked about PCRAM (phase change memory, which Micron has been shipping for a few years now), Mark Raynor, Matheson, discussed RRAM for Non-Volatile, and Suresh Upa, SanDisk, discussed packaging implications.

After the breakout, we had presentations from four materials supplier companies.  The four same very similar things.  Dave Bern of Dow Chemical discussed using the “right tool” for collaboration and the importance of making sure suppliers agree to work in areas that fit their “core competencies”.  Wayne Mitchel of Air Products noted that ICs are only 2% of GDP.  He agreed with Dave Bern that suppliers should only agree to work (partner) with customer on areas within expertise, otherwise it takes too much time and money to execute successfully. Jean Marc Girard, Air Liquide discussed the numerous risks of supply chain, from the sub-supplier, the environment (e.g. earthquakes), and materials stability (or lack thereof). Kevin O’Shea of SAFC Hitech emphasized that taking materials from a catalog of low volume and ramping to IC manufacturing needs is not trivial, and may also not be consistent with the materials manufacturer (the sub-supplier, or company that is “primary” in the materials).

The day 2 Panel discussion had more audience participation.  Some discussions I found particularly interesting are discussed below.

Tim (Intel) said the gap is getting wider between Intel, suppliers, sub-suppliers (esp. customs for IC industry). The large sub-supplier that doesn’t have an interest in moving forward – there is no motivation to increase metrology, metrics, etc.  The shrinking sub-supplier base isn’t good for our industry – reduction in cost per bit comes from shrinks and reuse of capital, not only lower cost materials..

Kurt Carlson said that sub suppliers don’t think IC fabrication is the best industry – the IC industry wants more and more, yet wants to pay less and less.  It’s not worth it to us (good sub-suppliers leave because it’s too costly for the small volumes).

Jean Marc said they don’t want to duplicate development costs, if they don’t need to; they would rather use universities and share on things like toxicology.

Dave said it costs millions of dollars to test materials, like EUV.

Mansour Moinpour asked about collaboration on liquid particle, GCMS, and similar – can we have joint & consistent measurements across the industry?  James Entegris responded that end user need to be drivers.  Jean Marc suggested that maybe SEMI standards could drive a standard of industrial analytics.

The value of roadmaps was very different to the various participants, however the idea of regulatory alignment and a roadmap related to this was generally thought to be useful.

The question of cost and logistics … there are some materials that require shipping a lot of water, which adds cost.  Intel said that they are getting into more cost sensitive mobile market and they may be driven to this rather than exact materials copy in near future.  Tim said the Intel CEO is “hell bent” that Intel will make money in the mobile market.  “Intel will pull it off.”

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