Self-Assembled Sponges
Using a novel self-assembly approach, the Johannes Gutenberg University Mainz and the Max Planck Institute for Polymer Research have created a new flexible mineral inspired by deep-sea sponges. The technology could one day enable futuristic body armor.

Researchers recreated sponge spicules using calcium carbonate and a protein of a sponge. Spicules are tiny spike-like structures found in many organisms. They deter predators because they are hard, sharp and prickly.

The nanometer size of the calcite bricks facilitates bending of the synthetic spicules. The radius of curvature upon bending is very large compared to the size of the individual particles. This prevents a fracture of the brittle mineral bricks. Source: University Mainz

Researchers devised synthetic spicules using silicatein-α, which is responsible for the biomineralization of silicates in sponges. Researchers used silicatein-α to guide the self-assembly of calcite spicules, which are similar to the spicules of a calcareous sponge.

The self-assembled spicules, 10 to 300 um in length and 5 to 10 μm in diameter, are composed of aligned calcite nanocrystals. The spicules are initially amorphous, but transform into calcite within months.

The synthetic spicules are elastic. This feature is linked to a high protein content. With nano-thermogravimetric analysis, researchers measured the organic content of a single spicule to be 10% to 16%. In addition, the spicules exhibit wave-guiding properties even when they are bent.

Phase-Change DSA
Since the 1960s, the industry has been trying to commercialize phase change memory (PCM). Sometimes called PCRAMs, PCM exploits the phase change behavior of chalcogenide materials. In theory, PCRAMs are a possible replacement for today’s solid-state memory devices.

Micron Technology and Samsung Electronics have recently shipped low-density PCM devices for limited applications. But in general, PCM is difficult to scale and expensive to manufacture.

Power consumption is another problem with PCM. The Korea Advanced Institute of Science and Technology (KAIST) has developed PCM technology at a power-consumption level below 1/20th of its present level. To accomplish this feat, KAIST has devised a novel approach using directed self-assembly (DSA).

Researchers used a block copolymer to form a thin nanostructured SiOx layer, which locally blocks the contact between a heater electrode and a phase change material. Using this approach, the writing current is decreased fivefold, as the occupying area fraction of SiOx nanostructures is increased from a fill factor of 9.1% to 63.6%.

Using DSA, researchers were able to reduce power faster than expected. “This is a very good example that self-assembled, bottom-up nanotechnology can actually enhance the performance of electronic devices. We also achieved a significant power reduction through a simple process that is compatible with conventional device structures and existing lithography tools,” said Keun-Jae Lee, a professor of KAIST, on Nanowerk’s Web site.

Dirty CD-SEMs
The scanning electron microscope (CD-SEM) has been used in the fab for decades as a means to measure the critical dimensions of complex structures.

Some believe the CD-SEM will soon run out of steam. One of the problems with the CD-SEM is contamination, which could become a showstopper for measurements at the nanometer scale.

The National Institute of Standards and Technology (NIST) is looking to prolong the life of the CD-SEM, by developing cleaning and other improvements to the existing technology.

Charged particle beam-induced contamination in the SEM is the issue. There is a buildup of carbonaceous material on the surface of the sample, where the ions or electrons are focused. This, in turn, results in characteristic dark patterns, making repeatable quantitative measurements difficult or impossible.

In the 1990s, NIST tested a prototype low-energy (20 Watt) plasma unit. The system, designed by XEI Scientific, was able to clean the CD-SEM by flooding it with oxygen plasma. Later, NIST collaborated with the IBSS Group to develop a modified plasma-cleaning device. That device works in a wider vacuum range and also has up to 99 Watts of power.

Evaporated gold-on-carbon sample imaged initially (a) and after 10 minutes of continuous imaging at twice as high magnification (b) showing excessive amount of electron beam-induced contamination. The same sample after hydrogen plasma cleaning and 10 minutes of continuous imaging at twice as high magnification (c), now without the detrimental effect of contamination. Source: NIST

New research indicates that the electron bombardment itself during extended measurements can act as a cleaning process for a variety of samples. With the research, NIST and others devised the so-called Contamination Specification. These are steps that SEM users can take to determine whether their instruments need to be cleaned and how to implement an effective cleaning process.

“We know how to get the instruments clean, and we know how to clean the samples,” said András Vladár of the Semiconductor and Dimensional Metrology Division (SDMD), on NIST’s Web site. “We learned that when you clean it, the instrument can remain contamination free for months unless a dirty sample is used.”

—Mark LaPedus

By Mark LaPedus
Apple, the world’s largest chip buyer, this year is expected to procure nearly $28 billion worth of semiconductors, up 15% from $24 billion in 2011, according to iSuppli. Apple is set to expand its lead in global chip purchasing in 2013, with growth of 12.3%.

Apple posted mixed results. “Our most recent checks confirm a lull in Apple’s iPhone production in 2Q12, down roughly 22% sequentially toward 29 million units,” said Craig Berger, an analyst with FBR. “Checks suggest Apple securing monthly iPhone 5 production capacity of 18 million to 20 million units, well ahead of Street sales estimates.”

Apple has also acquired fingerprint security company AuthenTec for $356 million.

SEMI reported that more than 60% of semiconductor equipment and materials companies say IP challenges have had an adverse impact on their companies.

GlobalFoundries is moving forward with the final construction for the extension of Module 1 at its Fab 8 campus in New York.

Rambus and GlobalFoundries disclosed the results from their collaboration on two separate memory architecture-based silicon test chips at 28nm.

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and ARM announced a multi-year agreement extending their collaboration beyond 20nm to deliver ARM processors on finFET transistors.

Rohm has taken a step in the foundry business. Under an agreement, the Japanese company will manufacture FRAMs for Ramtron.

Korean foundry vendor Dongbu HiTek has been certified to implement high-reliability ICs per the MIL-PRF-38535 standard.

Toshiba will cut production by 30% within its NAND flash memory fab in Japan amid a downturn in the sector.

Micron Technology’s recent purchase of bankrupt Japanese entity Elpida is a risk, according to iSuppli.

IC Insights forecasts the automotive IC market will grow 8% to $19.6 billion in 2012, up from $18.2 billion in 2011.

Samsung maintained its LCD TV leadership amid dismal market conditions.

Synopsys has completed the acquisition of Ciranova, a privately held electronic design automation (EDA) company.

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics. What follows are excerpts of that conversation.

SMD: Will the future be more patterning, or will we be looking at things completely differently such as DSA?
Liebmann: Directed self-assembly takes design restrictions to a whole new level. It could be ready for a node that goes into high-volume development in a couple of years. But it’s definitely one of these situations where we have to be completely out of options because it is so restrictive. I could see limited introduction of directed self-assembly for patterning that is naturally somewhat restrictive, such as the fins in the finFET. It’s unidirectional, fairly fixed grating. That’s a perfect application for directed self-assembly. Doing first-level metal with directed self-assembly is different. We’d have to be a lot more desperate than we are today, and we’d have to do a lot more development on the patterning end of directed self-assembly. As we continue to back up against the wall and EUV introduction continues to be delayed, it will make sense to use things like double-sidewall self-assembly for levels where today it doesn’t make sense.
Geronimi: Double patterning was the solution we’ve chosen for now because EUV doesn’t work, and it’s one that many other companies have chosen, as well. You need to get a lot of people to solve the problem.

SMD: Reading between the lines, it looks as if we may have lots of hybrid approaches going forward. Is that correct, and what does it mean for design and cost?
Aitken: The design perspective is interesting because as the nodes move on, the design rules are becoming increasingly incomprehensible. We had people at 40nm who claimed they could understand all the rules in the book. At 32 and 28nm they were starting to admit there were a few rules they couldn’t remember. And at 20nm, nobody admits to knowing all the rules. There are single rules that take up pages of the design-rule manual for one tool. So when you look at all these things, the complexity eventually gets to the point where it’s not clear how to meet them in the first place, and then even if you do meet the rules that it will still be manufacturable. We have this iteration between design people who want to design specific shapes and fab people who want to outlaw them. The design people look for loopholes and then the design people patch the rules. It’s past the point where you can check everything against the design rule manual. We need to do something different to be assured what we’re doing is the right thing. We’ve started talking to a lot more fab people than we used to, just to make sure that when we design something and we think it’s going to work, that it actually will.
Capodieci: There is a distinction between restrictive rules and prescriptive rules. The reality is that design rules are mostly restrictive. There’s a lot of inconsistency. You can be following the rules and violating the law, in general, because they point in different directions. The move toward prescriptive design rules could be done, and certainly the introduction of pattern-based verification systems like DRC class with pattern matching moves in that direction. Designers are much more ready to start physical design using a set of well-understood constructs. If you have the well-understood constructs and the rules combined, then you have nominal verification at the end. If you allow people to do whatever they want and give them lots of laws, then you end up with anarchy and chaos.
Aitken: If you use a handshake-type of structure that says here’s the way to build context, that works.
White: Won’t that just result in revolt from the design community? You’ve reduced the degrees of freedom to create a product.
Aitken: There are different levels of this. There isn’t just a monolithic design community. Different parts of the design community interact with different parts of the ecosystem. People who do place and route don’t see the messy contacting, for example. We deliberately try to prevent the router from knowing about a lot of these rules. A lot of the people interacting with the rules are the layout designers. They just follow the rules. We find that at advanced nodes, rules are so complicated that individual layout people have a lot of trouble with them. We’ve taken a two-pronged approach of educating the layout designers to use this pattern, and then we’ve added automation techniques so the layout is generated using automated tools. The tools follow rules better than people, and they can handle very large volumes of rules.
Liebmann: Getting back to hybrid solutions, it’s quite possible we will have directed self-assembly for one layer and image deposition on another. We may have all sorts of exotic things happen as we move forward. Hybrid solutions become a little scary when we design the world into TSMC-like and Intel-like. If they’re separate hybrid solutions to compete in those markets, then we may not have enough volume to compete and justify the cost. That’s a trend that becomes worrisome—the low-cost, high-performance and high-volume markets going in somewhat different directions.

SMD: Isn’t a 3D IC a hybrid solution?
Aitken: Yes, and that’s an excellent example. As the complexity of moving from one node to the next increases, the cost tends to go up. At some point, the cost of moving to the next node will be too high. I don’t think that’s going to happen all at once, either. At some point someone will say, ‘Even though stacked die is complicated and challenging, it still seems to be cheaper than doing it the other way.’ We’ll start to see some of that as time goes on.

SMD: What happens from the tools perspective as we look at hybrid solutions?
White: At 14nm, many different approaches are being considered for different layers of the design. Each one of those approaches may drive completely different verification and analysis and simulation engines. As an EDA vendor, we have to create solutions for all of those until the industry figures out which approach makes sense. We need to support all the solutions, including the one the industry ultimately chooses. We do try to build upon the infrastructure that’s already in place at the last node, so we can leverage some of the capabilities of double patterning at 20nm at 14nm.
Liebmann: That’s also an opportunity. Once we’re at a point where the only things we can really pattern reliably are gratings, then this whole distinction of logic and memory goes away. Everything is a grating. How you pattern that grating no longer really matters. There are a lot of design efficiency benefits from that. At Carnegie Mellon they’re working on a smart memory compiler. If your logic and memory are just gratings, then you can have some very intelligent synthesis engines that put the logic right next to the memory. You no longer have to separate anything. It’s the opposite of 3D integration, where you have a memory optimized manufacturing process and a logic optimized manufacturing process and then you glue things together. We’ll get there. It’s just a matter of when it becomes a cost-effective solution.
Lin: There are concurrent advances and progress in lots of areas. 3D-IC is a very good idea—the ‘More than Moore’ approach. But there are issues such as thermal and stress and warpage, so it will be incremental. It will go from interposer to TSV. There will be concurrent progress on chip-scale approaches as well as 3D IC.

SMD: Is ST looking at hybrid solutions, as well, or is it one or the other?
Geronimi: We are looking at hybrid solutions. At some point you need to do design partitioning. You need to optimize your system to for a specific market. At some node you may optimize each of the technologies.

SMD: Given the uncertainty of the cost of developing chips and being able to generate enough volume, what impact will that have?
Aitken: You’ve already seen quite a bit of that. As people move to new nodes, the number of people willing to take a bet and jump into that—at least initially—isn’t increasing. Some of the technologies we’ve talked about, such as directed self-assembly, have the potential to open things up to more people. But there’s also a challenge with some of the grating approaches Lars was talking about. When you move to a unidirectional approach you wind up losing something in terms of power or performance. And you may wind up with a situation where it costs more and you don’t actually get any benefit from moving to the next node. That’s definitely a big challenge if that happens.

By Mark LaPedus

MEMC rolled out FOX-Si, a silicon wafer offering designed for delivering advanced finFET technology with oxide dielectric isolation (FOX). Utilizing MEMC’s silicon-on-insulator (SOI) technology, MEMC can offer FOX-Si wafers at competitive prices.

In Taiwan, capital equipment spending is expected to reach about $9 billion in 2012, an increase from $8.5 billion spent in 2011, according to SEMI.

Worldwide photovoltaic manufacturing equipment billings declined for the third consecutive quarter, falling another 20% for the quarter and 60% from the same quarter last year, according to SEMI.

Photovoltaic polysilicon prices are forecast to drop 48% and wafer prices 56% in 2012, according to Solarbuzz. With such severe price declines, only 12 Chinese PV polysilicon manufacturers are still producing, and more than half of these companies are running at reduced utilization rates. Wafer plant utilization is forecast to average only 53% in 2012, according to the firm.

Global semiconductor sales increased in May, according to the SIA, but the industry is likely to see only modest IC growth in 2012. C.J. Muse, an analyst at Barclays, warned: “Weakening end market trends are starting to show up in the SIA data, with May semi revenue reverting back to negative. We could see semi revenues tracking flat to slightly negative for 2012, versus our official forecast of flat to up +4% Y/Y.”

Tablet shipments will surpass notebook shipments in 2016, according to NPD DisplaySearch.

In a survey, Gartner found that the main activities moving from PCs to media tablets are checking email (81% of respondents), reading the news (69%), checking the weather forecast (63%), social networking (62%) and gaming (60%).

With its planned purchase of Elpida Memory, Micron Technology will become the world’s second-largest supplier of DRAMs, according to IHS iSuppli.

The Hybrid Memory Cube Consortium (HMCC), led by Micron Technology and Samsung Electronics, has announced some new members: ARM, HP and SK Hynix.

Struggling Renesas Electronics is looking at more layoffs and fab closures.

Ramtron, a developer and supplier of nonvolatile ferroelectric random access memory (FeRAM), has rejected an unsolicited takeover offer from Cypress.

United Microelectronics Corp. has licensed IBM’s technology to expedite the development of the foundry’s next generation 20nm CMOS process with FinFET transistors. This agreement between UMC and IBM is only inclusive of IBM’s 20nm CMOS and FinFET. A spokesman for UMC said: ”UMC will continue with standard CMOS at 20nm and finFET.”

By Ed Sperling
Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics. What follows are excerpts of that conversation.

SMD: We’ve been hearing for a long time about EUV, but at this point it may not even be commercially viable at 14nm. So what do we do about that?
Liebmann: We have to keep the roadmap going, but we have to focus on performance scaling and cost per function scaling—and perhaps more so than pitch scaling. This whole idea that we’ll do double patterning and triple patterning and quadruple patterning, at some point the cost-per-function equation starts to degrade. I predict we’ll get away from these very rigorous node definitions and introduce new elements such as FinFETs to get a power/performance boost rather than focusing on 70% pitch scaling every two years because Moore’s Law says so. We have more options.

SMD: So how do we get out of this?
Aitken: That’s an excellent question, but I’m not sure there’s an equally excellent answer. The first challenge is that we have to be clear what we’re talking about. With 28nm, 22nm and 20nm, in some ways we’ve already lost touch with what those numbers actually mean. It’s similar to a size-12 shoe. It’s not 20% bigger than a size-10 shoe. It’s just somewhat bigger. In the same way, 22nm is somewhat smaller than 28nm but we’ve already lost some of the 70% pitch scaling Lars mentioned. So then we’re left with, ‘What’s actually scaling and what are the limiters?’ We’re trying to push those limiters. We need to apply more double patterning to more layers, and eventually that stops making cost-effective sense. It’s not obvious EUV will be ready even in time for 14nm, and at 10nm we’re into a lot of complexity even with EUV. There is a general issue with patterning, too. There are so many complexities associated with double patterning and so many flavors—stitching or not stitching, self-aligned or not self-aligned.
Capodieci: On double patterning, we will use it in technology development and production. It is complex and costly, but it is the only technology we have available. What’s really interesting is going beyond double patterning to triple patterning and quadruple patterning. Everybody has said at some point it will have to stop. The discussion beyond double patterning is that it makes us realize the insanity, for lack of a better word, of trying to do patterning at all. The reality is we have to stop doing patterning. That’s the wrong way to go beyond 14nm. We need to assemble and build. Patterning from the top down and creating an entire design methodology basically creates very complex systems. Then we try to create a physical design by superimposing our will onto hard matter. The hard matter pushes back. Photons don’t scale. Atoms don’t scale. And thermally, the voltage doesn’t scale. We need to discuss triple patterning, but only with the notion of destroying it.
Lin: It’s something we have to cope with at 20nm and 14nm.
White: From a tools perspective, double patterning will be necessary at 20nm. We absolutely see it, given all partners we have worked with, at 14nm. But at 14nm it will expand beyond double patterning. Whether it’s triple patterning is still a question for our customers. From an EDA perspective we perceive part of our normal business going forward. It’s an adjunct of on top of physical verification.
Capodieci: There are good solutions in place for double patterning. But in terms of design solutions as a whole, we are not there. Just because we have a signoff tool does not mean the entire ecosystem is ready. There are point solutions.
Geronimi: What is surprising is that double patterning is working quite well. This is coming from processes at other nodes where we have used design co-optimization, but this is the first time for design enablement.

SMD: Where are we with double patterning and directed self-assembly?
Liebmann: As Jean-Pierre said, we have solved the problem of double patterning for 20nm. There are no alternatives. We have rules, tools and methodologies. I would declare this problem solved.
Lin: I agree. We’re still smoothing out the kinks, but there are no major showstoppers.
Liebmann: So from here on, we can focus on the future, which involves directed self-assembly.
Aitken: There is an existence of tools at 20nm and there are various companies that have done it. But I think we’re a long way from saying these solutions have all of the kinks worked out.
Liebmann: And I would agree with that. As each new company creates a new test chip, we are having to work with them on this process, doing verification and taping out.
Aitken: One classic one we’ve been looking at recently is that when you have double-patterned metal layers you no longer have the concept of a best-case, worst-case that you had previously. You have fairly correlated situations where pattern one and pattern two get close to each other, creating a best case in one situation and a worst case in the other that migrates across the die. You have to have a method of dealing with that for timing closure. It’s not obvious how to do that with a lot of the tools today.
Capodieci: This is what I have been saying, as well. We have the solution, yes. It works, yes. But the deployment of this solution to a larger community without additional work isn’t possible, and it’s not a trivial amount of work. As engineers, we don’t just want a solution. What we want is a high-volume design to be in production. That isn’t an insurmountable problem, but it hasn’t been demonstrated yet.

Mentor Graphics and Samsung Electronics said they have developed a complete design-for-manufacturing (DFM) sign-off reference solution for Samsung’s foundry customers based on the Calibre platform.

The DFM sign-off solution is available for consumer and telecommunications designs targeting advanced process nodes. Samsung has already released the Calibre kits to their customers for 32 nm and 28 nm, and has completed evaluation for 20 nm.

The components of the Calibre DFM platform at Samsung include the Calibre LFD product for litho simulation and hot spot pattern identification, the Calibre nmDRC and Calibre PM products for pattern-based design rule and hot spot checking and fixing, and the Calibre YieldAnalyzer product, which is used in conjunction with the Samsung manufacturing analysis deck for DFM scoring and critical area analysis (CAA).

“We have used Mentor’s 32/28 nm DFM solution on several advanced SoCs to reduce late-stage problems that could lead to delayed product releases or slower-than-expected yield ramp-up. We are currently working with Mentor to expand the DFM solution to 20 nm processes as well,” said Kee Sup Kim, vice president of Samsung’s Infrastructure Design Center.

“At advanced nodes, proper incorporation of DFM techniques can create a competitive edge for both foundries and fabless designers,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon Division at Mentor Graphics. “We are pleased to be working with Samsung on the Calibre platform to provide this competitive edge to our mutual customers.”

GlobalFoundries, IBM, and Samsung Electronics will describe their technology offerings at the 2012 Common Platform Technology Forum, set for March 14 at the Santa Clara Convention Center.

Technologists from the three companies, which offer fab-compatible foundry services, will discuss their 28-, 20- and 14-nm processes, as well as innovations beyond 14nm. The event will include discussions of 450mm wafer manufacturing as well.

The forum’s Partner Pavilion, including EDA, IP, library, mask, packaging, and design services companies, will focus on the ecosystem of design enablement and implementation.

Registration is now open for the complimentary, one-day event at the Santa Clara Convention Center.

By David Lammers

Samsung Electronics researchers delivered several presentations at the 2011 International Electron Devices Meeting (IEDM) which attracted standing-room-only crowds, on topics ranging from Resistive and Phase Change RAMs (RRAMs and PCRAMs) to descriptions of their 28nm and 20nm logic platforms, among others. Samsung contributed to a reversal of a worrying trend of too-few industry papers at IEDM on real-world semiconductor technologies, as compared with contributions from universities and research consortia.

Hag-Ju Cho, of the Samsung Semiconductor R&D Center, described a bulk 20nm CMOS platform which comes in two metal pitch flavors: 80nm or 64nm pitches for the M1 layers.

The contacted poly pitch (CPP) of 80nm is the “smallest-ever reported” for a bulk planar CMOS device, and compares with the 113nm CPP for the previous-generation 32nm Samsung logic platform. One theme of the 20nm presentation is the need to overcome the substantial performance degradation effects of CPP scaling, and how to work around them.

Scaling the CPP is a “tradeoff” due to higher external resistance (Rext) seen from the tighter contact formation. The silicidation and metal fill steps were optimized to reduce the Rext, he said. Samsung came up with middle of the line (MOL) immersion lithography schemes to pattern the contacts. Later in his presentation, he said litho-etch-litho-etch (LELE) double patterning was “quite important” in the 20nm process flow.

Strain techniques tend to worsen as transistors are scaled, largely due to less room for the deposited SiGe material in the PFET. The PFET performance was enhanced by 45 percent, compared with the control, by using an in-situ eSiGe process rather than an external process. “The PFET shows significant performance enhancement,” he said, with an in-situ boron-doped eSiGe process. The close proximity of the eSiGe to the channel contributed to the 45 percent gain in performance, and the in-situ doping helps control short channel effects.

Plotting the threshold (Vt) versus gate length (Lg) for logic devices indicates the gate work function and shallow junctions are optimized in narrow devices. (Source: Samsung presentation at 2011 IEDM)

Scaling also makes it more challenging to implant the dopants, partly because the steeper angles, and shadowing from the gate, can affect the threshold voltages. The PFET Vt was tuned by halo implants which can be adjusted without shadowing. It is difficult to remove gate shadowing completely, however, leading to a slightly lower Vt for devices in the 80-100nm pitch range. “Gate height reduction could help to overcome this effect,” he said.

Samsung used a gate last high-k/metal gate flow, which increases strain in the NFET channel. Two different metals were used to set the NFET and PFET workfunctions. The nFET and pFET drive currents at 0.9V achieve 770 µA/µm (nFET) and 756 µA/µm.

Sematech announced the speakers for the 2011 International Symposia on Extreme Ultraviolet Lithography (EUVL) and Lithography Extensions.

Jia Li of Nvidia, Han-ku Cho of Samsung Electronics; and Risto Puhakka of VLSI Research, will address the conference, planned for Oct. 17-21 at Miami’s JW Marriott Marquis Hotel. The EUVL event is organized by Sematech, in cooperation with EIDEC and Imec, while the Lithography Extensions Symposium is in cooperation with Imec.

Jia Li, director of wafer foundry operations at Nvidia, leads a team evaluating 20nm and 14nm process technologies, including the readiness of EUV for and the extendability of 193nm immersion lithography to the 14nm node. His speech will address lithography challenges, including critical dimension/line-edge roughness (LER) control, defect elimination, and throughput.

Han-ku Cho, vice president and head of the photomask team at Samsung Electronics, is the keynote speaker at the 2011 International Symposium on Extreme Ultraviolet Lithography. Cho joined Samsung’s Electronics Semiconductor Business in 1995 and has served as vice president and director since 2007, in charge of production, management, and technology development of the Photomask Team at the company’s  Semiconductor R&D Center. Cho led the Korean government program in EUV lithography for nine years.

Cho’s topic, “EUV Readiness and ASML NXE: 3100 Performance,” will look at the current status and readiness of EUVL as well as the EUV mask fabrication process from the viewpoint of a device manufacturer. He will include imaging performance and issues related to the NXE: 3100, as well as achievements and prospects in EUV resist development focused on line width roughness reduction.

Risto Puhakka, president of VLSI Research, Inc., is the keynote speaker at the 2011 International Symposium on Lithography Extensions. He will explore the conditions that enable innovative lithography technologies to be introduced into mainstream semiconductor manufacturing.

Samsung Electronics has begun operations of its Line 16 memory fab, which the company said will have the world’s largest memory production capacity. Also, the company said it has started DDR3 DRAM production on 20nm-class technology.

The announcements were made during a ceremony at Samsung’s Nano City Complex in Hwaseong, Gyeonggi Province, where Line 16 is located. The line has started NAND production, the company said.

Kun-hee Lee

Samsung Electronics Chairman Kun-hee Lee said the global semiconductor industry “is in a period of fierce cyclical volatility,” adding that the new fab and the the beginning of DDR3 production “are important milestones to reinforce Samsung’s industry leadership.”

Oh-hyun Kwon

The ceremony was attended by about 500 guests including Lee; Oh-hyun Kwon, president of device solutions; Jay Y. Lee, president and chief operating officer, and others.

The new fab will constitute a total investment of 12 trillion Korean won through completion, or about $10 billion, Samsung said. Samsung began construction of Line 16 in May 2010 and completed installation of equipment for clean rooms this May. Trial production began in June and the facility was made operational for mass production in August. Housed in a 12-story building, Line 16 has a combined workspace of approximately 198,000 square meters, the company said.

“The 20nm-class solution improves productivity by 50 percent and reduces energy consumption by up to 40 percent, therein providing the greenest DDR3 solution available,” the company said. Samsung plans to develop a 4Gb-density, 20nm-class DDR3 in by the end of 2011. Samsung also said it will broaden its memory product lineup with mass production of 4 gigabyte (GB), 8GB, 16GB and 32GB DDR3 modules next year.