Posts Tagged ‘Rudolph Technologies’
Compiled and edited by Jeff Dorsch, Contributing Editor
Metrology and inspection technology is growing more complicated as device dimensions continue to shrink. Discussing crucial trends in the field are Lior Engel, vice president of the Imaging and Process Control Group at Applied Materials, and Elvino da Silveira, vice president of marketing, Rudolph Technologies.
1. What are the latest market trends in metrology and inspection?
Lior Engel, Applied Materials: The market trends we are witnessing today are influenced by the memory mix growth in wafer fab equipment and emergence of technology inflections as the industry progresses to advanced nodes and 3D device architectures. The optical inspection market is growing along with wafer fab equipment. We have seen the memory mix of wafer fab equipment grow from 23 percent in 2012 to almost 50 percent in 2015. The memory growth trend along with the transition from planar to 3D NAND changes the dynamics, as 3D NAND in general requires more metrology solutions while the foundries are maintaining high demand for optical wafer inspection. Demand for electron-beam products is increasing for all device types.
Shrinking design rules and shrinking process windows translate to systematic defects becoming a critical issue. These can hinder time to yield and affect production yields. The interaction between the design and process can fail under certain process conditions, and the resulting small defects are extremely difficult to find. Challenges such as these are fueling the need for both optical and e-beam inspection solutions in the fab. These different solutions complement each other and help the fab throughout the entire chip lifecycle. From a market perspective, the e-beam inspection market continues to grow and outperform WFE. E-beam inspection is currently focused at the R&D stage but is beginning to shift to high-volume manufacturing.
The metrology market is also growing due to multi-patterning requirements, the need for increased measurement points and tighter process window control. The advent of e-beam massive metrology tools provides a solution for process monitoring and uniformity control. Also driving the market are the ever increasing high aspect ratio (HAR) 3D NAND devices in memory and the increasing complexity in 3D FinFET metrology in foundry.
The workhorse metrology solutions include CD-SEM for multi-patterning controls and HAR memory, and optical critical-dimension (OCD) addressing spacer profile reconstruction in multi-patterning and full device characterization in FinFET.
Elvino da Silveira, Rudolph Technologies: In our experience, fan-out wafer level packaging (FOWLP) is a big trend for our customers. FOWLP does not require a substrate, so the lower cost makes it an attractive packaging technique over 2.5D or embedded interposers. There is a wide range of low- to high-end FOWLP applications, such as MCP/SiP, PoP, and 2.5D FOWLP, each requiring specific inspection/metrology techniques.
Further, we see submicron inspection as a big trend fueled by shrink. More than Moore is driving creative packaging that requires inspection of shrinking redistribution (RDL) lines. Miniaturization and multiple functions packaging, driven by the wearables and Internet of Things market, creates more emphasis on microelectromechanical system (MEMS) devices and sensors. Also, shrinking nodes in the front-end have shifted macro inspection needs to the submicron level.
With regards to front-end metrology trends, 3D is the driver. Second- and third-generation FinFET and 3D memory (both DRAM and NAND) are the key market drivers for front-end logic and memory. We are also seeing radio-frequency (RF), MEMS, and CMOS image sensors (CIS) move to adopt the latest generation of metrology as they compete to improve their processes and gain market share.
2. What are the latest technology trends in metrology/inspection?
Lior Engel, Applied Materials: Inflection challenges that are affecting M&I technology trends include:
Design rules shrinking causing denser feature imaging and the advent of smaller killer defects
3D transistors having more complex geometries, trenches and sidewalls. There is no line of sight to the killer defects and new materials are being introduced
- HAR structures introducing buried defects and new metrology challenges
- Process marginality resulting in critical systematic defects that require metrology coverage
In optical inspection, the technology trends addressing growing challenges include sensitivity improvement by enhancing the signal from key defects of interest. This can be achieved by enhancing imaging techniques and nuisance separation capabilities. In addition, leveraging design information (CAD) and optical information to optimize nuisance filtering.
For e-beam applications, which include SEM review, CD-SEM metrology and e-beam inspection, trends include:
Adding on-tool automatic classification and analysis capabilities, which result in more meaningful statistical process control (SPC) and yield control. Automation produces faster enhanced results, reducing human error and speeding up the process
Achieving 1-nanometer e-beam resolution and the availability of new imaging techniques are being utilized for finding the smaller defects in complex structures
- e-beam massive critical dimension (CD) measurements are being used for uniformity control
- e-beam voltage contrast inspection is increasingly required for embedded defects in 3D structures
- In-die on-device 3D and overlay measurements are challenging current optical metrology techniques, and trending towards new in-line solutions such as e-beam.
Elvino da Silveira, Rudolph Technologies: Increasingly complex front-end processes paired with “More than Moore” advanced packaging techniques are resulting in die-level stress. Product loss at assembly is extremely expensive since it’s one of the last steps in the process. Singulation excursions can manifest as a yield problem, but most often result as a reliability problem making them harder to detect and control. Traditional automated optical inspection (AOI) has been focused on active die areas rather than total chip area and is somewhat difficult and prone to overkill. Rudolph has developed a method to detect and monitor wafer chipping without extra investment or tool process time.
We solve the AOI inspection challenges by specifically monitoring the die seal ring while simultaneously inspecting both the active area and remaining kerf area, avoiding any throughput penalty. With our high-sensitivity/low-noise pattern-based inspection, customers can decide how close chips can occur relative to the seal ring. Judgements can be made about die quality based on certain characteristics (distance between die, die rotation, etc.). Lastly, customers can review image capture in both visible and infrared (IR).
Another inspection technology trend we see is the need for detection of non-visible/low-contrast killer defects in 3DIC flows. A 3D stacked IC flow may require a combination of through-silicon via (TSV) formation followed by die-stacking and molding. TSV interconnect formation flow will require processes such as via etch, via fill, nail reveal, copper pillar, wafer bonding, and debonding. A comprehensive process control strategy for such a complex flow requires multiple inspection and metrology approaches. Bright-field and dark-field detection is the baseline inspection technology for random and systematic defects. As the processes for TSV take on a more fab-like look, and are implemented in what is now being called the middle end, attention is turning to defects that are normally not visible. Examples of non-visible defects range from voids in TSVs to faint organic residues and incomplete etch on the bump pad. Voids can be detected using laser acoustic metrology. Laser acoustics also offer a unique solution for measuring the individual layers in a pillar bump stack to ensure tight process control and device yield. Organic residue-based defects have been tedious to detect using manual fluorescent microscopes. Now a more reliable approach to detecting organic defects is possible using automated high-speed fluorescent imaging based inspection. The strategy of combining bright-field, dark-field inspection with automated fluorescent imaging inspection, laser acoustics and software to analyze defect and metrology data has proved to be a cost effective approach to managing visible and non-visible defects in advanced assembly flows.
Advanced patterning of three-dimensional gate structures and memory cells is driving the need for advanced metrology techniques. Some of which have not been developed yet! Optical CD, X-ray, and acoustic metrologies are all at the leading edge. Optical wavelength ranges are now upwards of 20 microns to deal with thick multilayer memory stacks. Missing layer detection and the ability to measure ultrathin metal stacks with complicated interface characteristics are also challenges faced by our customers.
3. How are equipment vendors helping find defects in the nanoscale era?
Lior Engel, Applied Materials: Vendors must combine enhanced resolution, advanced imaging, and smarter applications into their offerings to meet the increasingly complex requirements from chipmakers as they transition to advanced nodes and 3D devices. E-beam and optical inspection solutions must become faster and more sensitive.
Metrology solutions are being used beyond traditional systematic process control, generating massive high-sensitivity data that is leveraged for predictive analysis.
In addition, as challenges grow, advanced applications leveraging design data and machine learning capabilities improve the overall results that the tools can deliver.
Elvino da Silveira, Rudolph Technologies: Those suppliers that can not only provide the required technology, but also provide the ability to take multiple points of data from across the fab, analyze that data, and make it actionable. True end-to-end process control that reduces time-to-ramp and improves ramp to yield—this is the value proposition that Rudolph offers its customers.
4. How is the 2016 market shaping up?
Lior Engel, Applied Materials: As was stated in Applied’s latest earnings call, our market outlook, taking into account the global economic climate, is that wafer fab equipment spending levels in 2016 will be similar to 2015. Driving industry investment are the technology inflections around 10-nanometer and the shift to 3D NAND, as well as increased spending in China.
Elvino da Silveira, Rudolph Technologies: Although Gartner is forecasting a flat 2016, Rudolph is uniquely positioned in both the front-end and true back-end semiconductor processes in a number of growth markets. Additionally, our new product pipeline is strong.
We see an opportunity to outperform our peers in 2016.
5. Is business improving, declining, or staying flat this year?
Lior Engel, Applied Materials: While the overall spending trend for WFE this year is flat, we are maintaining a positive outlook for Applied in 2016 because our customers are making strategic inflection-driven investments that play to our strengths. Our position is optimistic on wafer inspection for 2016. Our latest UVision Brightfield tool has a good position in foundry and logic. We’re the leader in e-beam review and are now taking that technology into inspection where we have significant pull from customers. So I think overall in 2016, we’re pretty optimistic about that business.
By Jeff Dorsch, Contributing Editor
The theme of this year’s 3D Architectures for Semiconductor Integration and Packading (3D ASIP) conference is “The Year of Stacked Memory,” noting how memory die stacked in one package are becoming more commonplace in 2015.
Put on by RTI International, the 3D ASIP conference is in its 12th year. Attendees and presenters are generally people involved in chip packaging, from academia and industry.
One presentation on Wednesday (December 16) was by Teruo Hirayama of Sony, which has a long history of developing CMOS image sensors, dating back to 1998 with the graphics synthesizer for the PlayStation 2 video-game console, employing embedded DRAMs.
Embedded DRAMs present a number of manufacturing challenges, such as requiring four photomasks at the time, compared with three masks for commodity DRAMs and two or so masks for “pure logic” chips, Hirayama noted.
To address the issue, Sony turned to “chip-on-chip” technology, combining the merits of system-on-a-chip devices and system-in-package technology, according to Hirayama. The chipmaker later resorted to stacked CMOS image sensors, which offer a cost advantage over conventional CMOS image sensors.
During fiscal 2014, stacked CMOS image sensors accounted for 64 percent of Sony’s CMOS image sensor shipments, with back-illuminated image sensors representing 31 percent and front-illuminated image sensors 5 percent, Hirayama reported.
For future directions in stacked image sensors, Hirayama pointed to connecting pixels to analog-to-digital converters, with a device that has memory, a microelectromechanical system device, and a radio-frequency chip on the bottom layer, topped with a logic device, the ADC, and pixels, in that order.
The conference also heard Wednesday from Bryan Black of Advanced Micro Devices, a senior AMD fellow who spearheaded development of the company’s Fiji graphics processing unit.
The project started in 2007 and took 8.5 years to complete, Black said. “The industry needed a new memory system,” he commented. “We ended up with a die-stacking solution.”
Virtual prototyping was employed along the way, according to Black.
With a silicon interposer measuring 1,011 square millimeters and an ASIC coming in at 592 square millimeters, with four high-bandwidth memories, the Fiji GPU module is a big device. “We realized the part was going to be much bigger than we expected,” Black recalled. “Then we realized this thing would be huge.”
Contour Semiconductor, Inc. announced it has been awarded three new patents to back its Diode Transistor Memory (DTM) technology, the world’s lowest production-cost, non-volatile memory technology.
Fujitsu Semiconductor America announced that Shinichi “James” Machida, who led the company from late 2008 until spring of 2011, has been named as the new president and CEO of FSA.
ProPlus Design Solutions announced Samsung Electronics has extended its partnership with ProPlus through the deployment of ProPlus’ BSIMProPlus modeling platform for its 14nm FinFET SPICE modeling.
Analog Devices, Inc. introduced the first and only MEMS gyroscope specified to withstand temperatures of up to 175 degrees Celsius commonly encountered by oil and gas drilling equipment.
GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, announced that Louis “Lou” Lupin has joined the company as senior vice president and chief legal officer.
Credo Semiconductor announced the appointment of Jeff Twombly as vice president of sales and business development.
Taiwanese chipmakers, LED manufacturers, and Outsourced Semiconductor Assembly and Test (OSAT) firms will spend firm nearly $24 billion in the next two years on equipment and materials, powering excitement for SEMICON Taiwan 2014, which opened this week in Taipei.
United Microelectronics Corporation and Fujitsu Semiconductor Limited announced an agreement for UMC to become a minority shareholder of a newly formed subsidiary of Fujitsu Semiconductor that will include its 300mm wafer manufacturing facility located in Kuwana, Mie, Japan.
Rudolph Technologies, Inc. announced that the SUNY College of Nanoscale Science and Engineering (CNSE), Albany, NY, has selected its Discover Enterprise Yield Management Software (YMS) to provide an integrated data warehouse and analytics system for the Global 450 Consortium (G450C) equipment development program.
Worldwide silicon wafer revenues declined by 13 percent in 2013 compared to 2012 according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. Worldwide silicon wafer area shipments increased 0.4 percent in 2013 when compared to 2012 area shipments.
Silicon wafer area shipments in 2013 totaled 9,067 million square inches (MSI), slightly up from the 9,031 million square inches shipped during 2012. Revenues totaled $7.5 billion down from $8.7 billion posted in 2012. “Annual semiconductor silicon shipment levels have remained essentially flat for the past three years,” said Hiroshi Sumiya, chairman of SEMI SMG and general manager of the Corporate Planning Department of Shin-Etsu Handotai Co., Ltd. ”However, industry revenues have declined significantly for the past two years.”
Rudolph Technologies, Inc. announced this week the sale of its first NSX 320 TSV Metrology System to CEA-Leti, a research organization based in Grenoble, France, which, in the frame of the Nanoelec Research Technology Institute (Nanoelec RTI) program, is developing three-dimensional integrated circuit (3DIC) technologies that use through silicon vias (TSVs) to conduct signals among vertically-stacked chips. The new NSX 320 TSV system includes integrated 3D metrology that enables specialized measurements critical to the TSV process.
Honeywell announced today that it has introduced new RadLo low alpha plating anodes based on proprietary technology to help reduce alpha particle radiation that can lead to data errors in semiconductors. The new plating anodes for semiconductor packaging wafer bumping applications expand Honeywell’s RadLo offerings and employ proprietary Honeywell metrology and refining techniques.
At this week’s International Solid State Circuits Conference (ISSCC2014), imec and Holst Centre, together with Olympus, demonstrated a low-power single channel implantable electrocardiography (ECG) acquisition chip with analog feature extraction, which enables precise monitoring of the signal activity in a selected frequency band. Leadless Pacemakers with ultra-small size and ultra-low power consumption are emerging, improving analysis and clinical research of the intra-cardiac rhythm, and as a result, improving patients’ quality of life. The new low-power ECG acquisition chip advances the state-of-the-art by consuming only 680nA when all features are active, and also provides competitive performance, such as input SNR>70dB, CMRR >90dB, PSRR >80dB without any external passive components. By equipping an ultra-low power analog feature extractor, the new chip is capable of assisting digital signal processor platforms for the implementation of low-power heartbeat detection algorithms.
SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets today announced the opening of a new office in Korea. The new SPTS Korea office is situated in Pangyo and will be the central base of operations for sales, field process and engineering staff. The new facility will also carry essential and critical spares inventory to support SPTS’ system installed base.
Fujitsu Laboratories Ltd. and imec Holst Centre this week announced that they have developed a wireless transceiver circuit for use in body area networks (BAN) for medical applications that adheres to the 400 MHz-band international standard. While the subject of high expectations for medical applications, wireless monitoring of brainwaves or other vital signs has in the past required over a dozen milliwatts (mW) of electric power. Now, however, by optimizing the architecture and circuitry, Fujitsu Laboratories and imec Holst Centre have succeeded in reducing the electric power requirements of wireless transceiver front-ends, to just 1.6 mW when receiving data and 1.8 mW when transmitting.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.