Synthetic diamond process enables quantum computing
There is a growing interest in the area of quantum computing. A quantum computer works by storing the 0s and 1s of information in quantum superposition states. They could one day solve problems that are impossible for even the fastest conventional supercomputers.

In one of the latest efforts, Element Six, Harvard University, the California Institute of Technology and Max-Planck-Institut für Quantenoptik, have devised a single-crystal synthetic diamond to enable the development of a quantum-bit memory. Using Element Six’s synthetic diamond technology and its chemical vapor deposition (CVD) process, the researchers also demonstrated a quantum bit memory that exceeds one second at room temperature.

This is said to be the first time that such long memory times have been reported for a material at room temperature, giving synthetic diamonds an advantage over rival materials and technologies, such as cryogenic cooling.

Mikhail Lukin of Harvard’s Department of Physics, said: “These findings might one day lead to novel quantum communication and computation technologies, but in the nearer term may enable a range of novel and disruptive quantum sensor technologies, such as those being targeted to image magnetic fields on the nano-scale for use in imaging chemical and biological processes.”

Element Six’s synthetic diamonds are ideal for applications that require extreme hardness and thermal conductivity. Applications include semiconductors, lasers, quantum computing, and magnetometry and bio-medical sensors.

ReRAMs take another step towards commercialization
R&D organization IMEC recently presented improvements in performance and reliability of resistive RAM (ReRAM) cells by process improvements and stack engineering. RRAM is a promising next-generation memory technology that could replace NAND flash.

IMEC demonstrated asymmetric bipolar RRAM cells with high-performance and ultra-low operation current at <500nA. A hafnium scavenging layer was proven to be key in the stack asymmetry of defect distribution and in the forming process. The state resistances were controlled by introducing aluminium oxide as insert layer, hafnium oxide was kept as a buffer material for further improving the filament resistance control, and stack thinning allowed a lower forming current.

These results were obtained in cooperation with IMEC’s key partners in its core CMOS programs, including Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Elpida, SK Hynix, Fujitsu, Toshiba/SanDisk, and Sony.

By Ed Sperling

Future memory technology inside of mobile devices will use less power and run faster at each rev of Moore’s Law, but that technology also will look different, use different materials, and will be manufactured with different equipment, processes and technologies.

While this technology will owe its heritage to research and testing of the past few decades, the differences are expected to be dramatic. A panel of vendors, their customers and researchers took a deep dive into the research that will change the memory market of the future at an IEEE International Memory Workshop held Monday in Monterey, Calif. The discussion, chaired by Raman Achutharaman, VP of strategy and marketing for Applied Materials’ silicon systems’ group, pointed to some interesting research, developments and future standards.

What’s next?
Laith Altimime, Imec’s program director for CMOS process technology, said that over the next decade memory makers will require new materials (graphene and/or carbon nanotubes, for example); new techniques, including EUV lithography, air gap insulation and 3D stacking with through-silicon vias; and new structures, including hybrid tunneling field effect transistors (TFETs), VFETs and TANOS cells.

“New materials and device architectures are the key,” said Altimime, noting that 3D stacking will “take over everything in its path.” That includes resistive RAM (RRAM), a non-volatile type of memory now in the research phase that relies on current applied to a filament; 1T-RAM, a higher-density version of RAM; and spin-transfer torque RAM, which changes the magnetization on a thin magnetic layer by running a spin-polarized current across it.

Altimime noted that scaling beyond 16nm most likely will require 3D cell architectures. He said the base material will still be CMOS, but it also will include higher-k dielectrics, metals, and stack engineering.

Fig. 1: Air gap insulation. Source: Applied Materials

NAND changes
Sung-Kye Park, of Hynix’s Memory R&D Division, noted that NAND will require a slew of changes to decrease charge loss and increase e-field retention. Those changes will include everything from air gap technology to an increased doping of the control gate. He expects new structures and new materials to start hitting the market within two years.

“3D flash is a possible candidate,” Park said, pointing to Toshiba’s pipe-shaped Bit Cost Scalable technology, Samsung’s Terabit Cell Array Transistor (TCAT), Hynix’s 3D-FG and hybrid chips. But he noted there also are potential hurdles in areas such as process integration, particularly in the areas of multistack deposition and word-line formation.

Fig. 2: 3D NAND architectures. Source: Applied Materials

DRAM shift
Joo Young Lee, strategic planning manager at Samsung, said the goal for DRAM is still a 35% cost reduction each year, but to achieve that will require moving to the next process nodes. DRAM is currently approaching 30nm, he said. He expects it to hit 25nm by 2015 and 14nm by 2020, with DDR4 hitting mainstream in 2013. EUV will be required at 14nm, he said.

Reaching those advanced nodes will require changes in some of DRAM’s basic structures—cell capacitors, cell array transistors and cell node contacts, all of which will need to be re-engineered.

Patterning issues
Yoshitaka Tsunashima, a leading researcher at Toshiba, said his company’s NAND technology already requires double patterning. At 14nm, double patterning and EUV both will be required.

EUV has its own issues, of course—light source performance, mask defect control, optical performance, mask data preparation, and resist performance. But he noted that 11 companies are now working to solve those issues as part of the EUV Infrastructure Development Engineering Center (EIDEC).

“The other way we can get there is 3D NAND,” he said, noting that either approach—lithography or stacking—or both will help reduce bit costs. He said that technology also can be extended to RRAM, organic memory and MEMS memory.

Customer view
Nokia’s Matti Floman said the ideal solution would be universal memory. But given that is an unlikely development, what’s needed from his company’s standpoint are higher bandwidth for DRAM and non-volatile memory, new package solutions, lower power consumption, higher temperature tolerance, pre-developed scalable modules, and standard solutions.

He noted that Wide I/O is seen as a strong candidate for replacing DDR2 and DDR3 in high-end products. Mass memory, meanwhile, is moving toward NAND and embedded MultiMediaCard (eMMC).

by Ed Korczynski

Resistance-change Random Access Memory (RRAM or ReRAM) devices continue to be developed at labs and fabs around the world, as seen by more than 40 papers at the spring Materials Research Society (MRS) spring meeting which was held April 25-29 in San Francisco, California. RRAMs are based on resistive switching in metal oxides, such as titantia and niobia, that show memristor properties. With single-digit nanosecond switching-speeds and 10-year non-volatile data retention, RRAMs may represent the future of solid-state memory after DRAM and Flash devices eventually reach scaling limits below 22nm half-pitch.

Technically, the other devices competing with RRAM for the future of memory are themselves based on changes in resistance. Phase-change memory (PCM) using GST material switches between low- and high-resistance states, but requires large drive currents to heat the material to effect the phase-change. Spin-transfer-torque RAM (STT-RAM) is also read as a change in resistance, but the cell size is relatively large. RRAM devices built using cross-point arrays could provide the smallest, fastest, leanest, and cheapest non-volatile memory chips.

Between oral presentations and posters, the Spring 2011 MRS Meeting showed many different groups using different switching materials for RRAMs:

8 – TiO

7 – NiO

6 – Zn0:metal

4 – SiO:Cu

3 – HfO:metal

3 – TMO:metal

3 – polymers

2 – TaO

2 – SrTiO

1 – CuO

1 – HfSiO

1 – WO

1 – solid electrolyte

42 + 11 more novel materials in session Q10

= 53 total RRAM presentations.

HP Labs RRAM Update

Stan Williams’ group at HP Labs has led the world in memristor and RRAM R&D using the titania family of materials as the switch since 2006. They claim that their champion device switches in <2ns, and has world-record endurance of >1.2E10 cycles. Stan Williams provided a keynote address to an MRS workshop last year, in which he explained how his group finally discovered that the conducting channel consists of a 1-2nm thin TiO2 tunnel barrier adjacent to a ~30nm thick “magneli-phase” Ti4O7 layer. Modulating the width of the tunnel barrier through diffusion of oxygen-vacancies controls the electrical resistance of the stack.

This year, HP Labs updated their titania work by reporting on two different electroforming mechanisms seen in the same 50nm × 50nm crossbar memristive device. A “soft” electroforming step uses <140µAmp at ~5V to create a high-resistance mode, while a “hard” electroforming step uses ~250µAmp at ~9V to create a low resistance mode. The two switching modes possessed opposite switching polarities that shared a metastable intermediate resistance state. The two modes can be explained by two switching layers at the top- and bottom-electrode interfaces:

• intermediate state, the bottom layer is ON with conducting channels made of both oxygen-vacancies and charge-traps, while the top layer consists of a tunnel gap;
• OFF state, both layers consist of tunnel gaps; and
• ON state, the top layer is ON with conducting channels made of oxygen-vacancies, while the bottom layer consists of a tunnel gap.

J. Joshua (Jianhua) Yang, provided an update on HP Labs’s RRAM work by surprisingly stating that titanium-oxides have stability issues which may limit device lifetimes, but that tantalum-oxides are free of such issue. The titania family seems to show issues getting beyond 100-1000 cycles, due to excessive heating inside the switch material due to the tendency to apply overvoltage. The two phases of titania will react with each other during heating, so the ON/OFF resistance differences are not so stable. “You need stability, and larger oxygen stability in the materials,” explained Yang. Presumably, the world-record cycling performance using titania was achieved using careful limits on overvoltage.

To improve lifetime with overvoltage margin, HP now uses a tantalum-oxide switching layer, a platinum bottom-electrode, and a tantalum top-electrode. The company claims that this system should be scalable to <5nm, the switching speed is merely 5ns, and the resistance state should be stable for 10 years. TaOx as deposited is amorphous, and even after heating steps it may retain some amorphous character.

RRAM Electroforming Avoidance

The ability to create functional RRAMs without electroforming would provide a significant cost and yield advantage in manufacturing. Though there is still debate as to the exact nature of the solid-state ion-diffusion mechanism(s) responsible for the change in resistance, it is clear that proper stacks of nano-scale oxides and sub-oxides are needed. Consequently, once trial-and-error has identified an ideal materials stack, it is likely that a wafer-scale process flow will be found to create the desired stack without the need for electroforming. For example, annealing in a reducing ambient or solid-phase gettering techniques may be used to adjust the stoichiometry of thin-films.

Using a tungsten-plug from a 90nm node DRAM process flow as one electrode, researchers from Research Center Juelich (with funding from Intel) used TiO2 thickness of 25nm and a Pt/Ti top electrode to make inherently electroforming-free RRAMs (Session Q8.4). Initially the devices were found to be in an intermediate state, and can be SET with positive bias voltage to the low resistance state (LRS). Without bias the intermediate state undergoes a RESET process to a high resistance state (HRS). Under negative voltage bias both processes can be reversed and the device returns into the intermediate state. This flipping of the SET and RESET process from positive to negative bias voltage polarity and vice versa can repeatedly be adjusted in one device. This versatile switching scenario is possible due to the use of the low-workfunction Ti and W electrodes which result in low barriers to the oxide.

The Juelich process flow is as follows:

1. Plasma etch to clean the W plug,
2. Reactive sputter TiO2 (300W, 46sccm AR, 17 sccm O2), and
3. PVD of top-electrode.

The top-electrode was 30nm Pt with an optional 5nm layer of Ti or W below. “As long as there is a Pt/TiO2 interface we need forming,” explained Rainer Bruchhaus of Juelich. However, when using either W or Ti as a barrier between the Pt and TiO2 (while maintaining W as bottom electrode) they see no need for electroforming. In all cases, the voltage range is limited to +- 1V.

RRAM scalability

Much of the global interest in RRAM structures is due to the ability of cross-point memory architectures to be shrunk far more easily than other device structures. The process flow to make cross-point arrays is particularly attractive from an overlay perspective, since the top- and bottom-electrodes are perpendicular to each other and the switching material is patterned along with the top-electrode.

The world record for the smallest resistive memory element is currently held by the National Nano Device Laboratories (NNDL) in Taiwan, which showed a 9nm half-pitch functional RRAM at IEDM last December (Paper #19.1, “9nm Half-Pitch Functional Resistive Memory Cell with <1 µA Programming Current Using Thermally Oxidized Sub-Stochiometric WO_x Film,” C. Ho et al, National Nano Device Laboratories, Taiwan/University of California at Berkeley). It features the lowest reported programming current to date of just <1µA using tungsten-oxide, compared to ~20mA for phase-change memories. The device was built using nano-injection lithography which employs a chemical reaction activated with a finely controlled electron beam to deposit a hard-mask for etching, but could have used Nano-imprint Lithography (NIL) or other patterning to form the array.

For more details on the physics of these devices, Applied Physics A, Vol.A102, No.4 is a special issue on “Memristive and Resistive Devices and Systems,” and is now available for free download as individual PDFs.