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Posts Tagged ‘RF SOI’

Tackling Parameter Extraction for 16nm and Below

Monday, June 8th, 2015


There are four reasons why parasitic parameter extraction is getting a lot harder for 16nm and below technology nodes: 1) 3D device geometries, such as the finFET, which result in more complex electrical fields around the device 2) multi-patterning, which causes increased variability; 3) a demand for 10X tighter levels of accuracy, and 4) increased levels of secrecy from foundries and designers.

With Calibre xACT, Mentor Graphics has a solution that is part equation-based and part field solver, giving high accuracy and high throughput. Customers using the Calibre xACT platform for parasitic extraction have experienced improvements in turnaround time as high as 10X, while meeting the most stringent accuracy requirements.

At DAC this week, Carey Robertson, product marketing director of Calibre xACT, will be presenting an optimized extraction flow for RF-SOI processes, based on work with STMicroelectronics, today (Monday June 8th) between 4-5 pm at the Mentor Graphics booth #1432. Register at the Mentor Graphics website:

Robertson explained the new challenges facing the industry. “We have new types of devices that are three-dimensional in nature. There is a very profound electrical field that is three dimensional in nature, and very difficult to capture with traditional techniques, such as equations or tables,” he said. In addition to the device itself, there’s going to be local interconnect, there’s going to be contacts that need to be modeled.

Parasitic electrical fields around a 3D finFET device.

Double- and multi-patterning adds to the complexity.  “In the area of parasitic extraction, double patterning essentially means that we have geometries on the same layer on different masks. As those masks shift, that will incur additional sources of parasitic variation that we have to consider,” Robertson explained.

In addition, foundries such as Samsung, TSMC and GLOBALFOUNDRIES are pushing tighter and tighter criteria. “Foundries are pushing EDA vendors to bring the accuracy of their parasitic tools to a much tighter level vs their golden reference,” Robertson said. “At 20nm, if we felt like our accuracy was within 5-10% of the golden reference, that was typically fine. What we’re seeing at 16, 14 and 10nm is that foundries are requiring that the accuracy be within 2%, many times 1% with a sigma of 2%,” Robertson said. “It’s very, very tight criteria, tighter than we’ve ever seen before.

The other challenge is that in years past, EDA vendors would get a lot of data to use to develop their tools. “We’d get a lot of structures and a lot of things to go check against. We’d get those inside Mentor Graphics and R&D could play with that and figure out the best models to accommodate them,” Robertson said. He described today’s situation as an arms race between foundries and designers, where secrecy was paramount. “It’s an arms race to see who comes up with the best process, and it’s a race amongst designers to come up with who has the best designs. They don’t let their design data go outside of their respective companies. We have to figure out how to model these with more complex interactions, tighter criteria and much less access to data,” he said.

Enter the new Calibre® xACT™ parasitic extraction platform that addresses a wide spectrum of analog and digital extraction needs, including 14nm FinFET, while minimizing guesswork and setup efforts for IC designers. The Calibre xACT platform delivers a combination of accuracy and turnaround time (TAT) by automatically optimizing its extraction techniques for the customer’s specific process node, application, design size, and extraction objectives.

Samsung has worked extensively with Mentor Graphics on the development and qualification of the Calibre xACT platform for 14nm, and used it during technology development because of the high accuracy it provides. The Calibre xACT product’s ability to employ a single rule deck for a range of extraction applications allows customers to get the accuracy and fast TAT they need without having to manually modify their rule decks or tool configuration.

“After careful benchmarking of the leading extraction products, we selected Calibre xACT to be our reference signoff extraction tool for all of our next generation designs,” said Dragomir Nikolic, CAD Director, Cypress Semiconductor. “This includes products at the 90nm and 65nm process nodes. We found Calibre xACT to have the best combination of high accuracy and fast turnaround available among extraction products targeting leading-edge nodes. We also see great value in the ability to use a single extraction tool to produce optimum results across a wide variety of applications, from transistor level to full chip digital extraction.””

Circuit designers have to wrestle with performance versus accuracy throughout the design cycle. Parasitic extraction is no different. With the leading process nodes using more complex FinFET devices, design engineers are pushing for tighter accuracy, while also needing higher performance and capacity for billion transistor designs. In fact, all process nodes are seeing growing complexity with the mix of memory, analog, standard cell, and custom digital content in modern IC’s. This complexity poses a range of different challenges for extraction tools. To meet these requirements the Calibre xACT platform uses a combination of compact model, field solver and efficient multi-CPU scaling technologies to ensure robust accuracy as well as turnaround performance needed to meet schedule deadlines.

The Calibre xACT extraction platform is integrated with the entire Calibre product line for a seamless verification flow, including the Calibre nmLVS™ product for complete transistor-level modeling, and the Calibre xACT 3D product for targeted, extreme-accuracy extraction applications. It also interoperates with third-party design environments and formats to ensure compatibility with existing design and simulation flows.

“It’s an environment that has all of the necessary integration and accuracy techniques that the custom IP designer needs, as well as the throughput, turnaround time and scalability the signoff/extraction needs,” Robertson said.

At DAC this week, Robertson will be presenting an optimized extraction flow for RF-SOI processes, based on work with STMicroelectronics, today (Monday June 8th) between 4-5 pm. Register at the Mentor Graphics website:

Robertson says to enable RF design optimization with high correlation to actual silicon, simulation of RF-SOI designs must include extraction and modeling of the silicon substrate. Conventional silicon substrate extractions are cumbersome to use or lack the accuracy and performance required to produce a full-chip post-layout netlist.

STMicroelectronics, Mentor Graphics and Coupling Wave Solutions are working on a new flow that generates silicon substrate parasitics in just a few minutes. These can be added to a conventional post-layout netlist to produce a complete and accurate parasitic model for RF SOI designs. Carey’s presentation will give an overview of RF-SOI technology, and describe how the new extraction flow delivers parasitics accuracy, performance and ease-of-use.

Mentor Graphics Technical Sessions are held at booth #1432.

SOI: Revolutionizing RF and expanding in to new frontiers

Friday, April 17th, 2015

By Peter A. Rabbeni, Director, RF Segment Marketing and Business Development, GLOBALFOUNDRIES

Faster connections and greater network capacity for wireless technologies such as LTE, WiFi, and the Internet of Things is driving the demand for more complex radio circuit designs and multi-band operation.  In addition the emergence of wirelessly connected smart wearables is not only driving localized high performance processing power but also extended battery life, two goals which are often in conflict. The predicted explosion in the IoT is shown in Figure 1.

Figure 1. More than 30 billion devices are forecast to be connected to the internet by 2018 (Source: BI Intelligence).

The rapid growth in smartphones and tablet PCs and other mobile consumer applications has created an opportunity and demand for chips based on RF-SOI technology, particularly for antenna interface and RF front end components such as RF switches and antenna tuners.  As a low cost and more flexible alternative to expensive gallium arsenide (GaAs) technologies, the vast majority of RF switches today are built on RF-SOI.

To address the highly complex, multi-band and multi-standard designs, RF front-end modules (RF FEM) require integration of multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management. Today these functions are addressed by different technologies. The RF SOI process technology enables design flexibility by integrating multiple RF functions like power amps, antenna switches, and transceivers, as well as digital processing and power management to be integrated—all on the same die. The benefit of integrated radios is they consume   less power and smaller area than traditional radios. Therefore, mobile devices that exploit radio integration using RFSOI can offer more functions with better RF performance at competitive cost.

Mobile devices that implement RF SOI for RF Front End module functions benefit from higher levels of integration that combine with improved linearity and insertion loss, which translates to better transmitter efficiency and thus longer battery life enabling longer talk times (lower power) and faster downloads (higher signal-to-noise ratio).

Emerging technologies like RF-SOI and even FD-SOI have unique properties and capabilities beneficial in enabling RF circuit innovation and integration levels never before seen in silicon-based technologies.  Device ft, gm/I, well bias control and inherent isolation of the substrate all contribute to improved system level performance over competing technology resulting in the ability to achieve higher linearity, lower power, low loss, and low cost/small size.

Innovative solutions

An innovative technology that is currently addressing the ever-increasing challenges of RF front-end design is UltraCMOS 10 (Figure 2). This customer specific process, co-developed by GLOBALFOUNDRIES and Peregrine Semiconductor, demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions. For designers, it dramatically reduces the required engineering and validation time. And, for the end-user, they benefit from longer battery life, better reception, faster data rates and wider roaming range. With the qualification process complete, UltraCMOS 10 technology is now a fully qualified technology platform.

Figure 2. UltraCMOS 10 technology demonstrates SOI’s ability to create highly integrated and reconfigurable mobile radio antenna interface solutions (Source: Peregrine Semiconductor).

High speed digital-to-analog converters (DAC) are an essential component for direct-to-RF conversion architectures. Faster converter sampling speeds and greater peak-to-peak signal fidelity hold high promise in moving mobile digital signal processing closer to the antenna. It has been demonstrated that DACs on fully depleted SOI, achieve high linearity and very low power for nyquist bandwidths as wide as 5.5GHz. The RF architecture with a high-performance DAC results in lower power dissipation while synthesizing very wideband signals (Figure 3). This further demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna.

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Figure 3. Low power RF DAC demonstrates SOI ability to move high frequency digital sampling and processing closer to the antenna [1

Agile radio architectures are another key area that can address mobile architecture challenges and cost. Today, the analog RF frontend duplicates much of the circuitry for each band. To simplify, new advancements (Figure 4) in tunable structures and filters are being made to provide a single radio for multi-band/multi-mode frequency. SOI technology offers the possibility to develop tunable/reconfigurable RF FEMs to improve RF performance at competitive cost.


Figure 4. Cutting-edge developments in tunable filters [2

Creating an Ecosystem to Extend SOI to RF

As RF FEM architectures and design challenges become more and more complex, it becomes necessary to relieve some of the increased burden at all levels of the value chain. In order to provide better RF products—from system design and RF integrated circuits down to engineered substrate design—development teams can no longer expect to design in silos and be successful. Collaboration and co-optimization are becoming much more important as a result of the changing dynamics of the design-technology landscape.

Investing in the future is critical to address certain RF challenges such as radio architecture design in multiband, multimode mobile radios and ultra-low power (ULP) wireless devices. Successful collaboration will require adherence to standards to enable interoperability, otherwise, in this fragmented market, the industry won’t see the full benefit of all of the technology innovation. To succeed, we need collaboration at different levels, from R&D to ensure we have the world’s best talent trying to solve all of these problems, all the way through to business models.

There is no doubt that demand on our networks will continue grow and there are advanced chip technology challenges the industry needs to address to enable a higher level of integration and lower power consumption for future wireless communication. GLOBALFOUNDRIES is committed to enabling an SOI portfolio and ecosystem—from process, device, and circuit through system level IP— to lower customer design barriers and complexity and introduce new RF architectures that leverage SOI-based technologies.


1. E. Olieman, A.-J. Annema and B. Nauta, “A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist,,” in VLSI Circuits Digest of Technical Papers, 2014 Symposium on , Honolulu, 2014.

2. Joeri Lechevallier, Remko Struiksma, Hani Sherry, Andreia Cathelin, Eric Klumpernik, Bram Nauta, “A Forward-Body-Bias Tuned 450MHz Gm-C 3rd-Order Low Pass Filter in 28nm UTBB FD-SOI with >1VdBVp IIP3 over a 0.7 to 1V Supply”, ISSCC, San Francisco, 2015.

Blog review September 22, 2014

Monday, September 22nd, 2014

Siobhan Kenney of Applied Materials reports that The Tech Museum of Innovation announced the ten recipients of the Tech Awards. Presented by Applied Materials, this is a global program honoring innovators who use technology to benefit humanity. These incredible Laureates are addressing some of the world’s most critical problems with creativity – in naming their organizations and in designing solutions to improve the way people live.

Jean-Pierre Aubert, RF Marketing Manager, STMicroelectronics says RF-SOI is good for more than integrating RF switches.  Other key functions typically found inside RF Front-End Modules (FEM) like power amplifiers (PA), RF Energy Management, low-noise amplifiers (LNA), and passives also benefit from integration.

Phil Garrou blogs Samsung finally announced that it has started mass producing 64 GB DDR4, dual Inline memory modules (RDIMMs) that use 3D TSV technology. The new memory modules are designed for use with enterprise servers and cloud base solutions as well as with data center solutions [link]. The release is timed to match the transition from DDR3 to DDR4 throughout the server market.

Stephen Whalley, Chief Strategy Officer, MEMS Industry Group, blogs about the inaugural MIG Conference Shanghai, September 11-12th, with their local partners, the Shanghai Industrial Technology Research Institute (SITRI) and the Shanghai Institute of Microsystem and Information Technology (SIMIT).  The theme was the Internet of Things and how the MEMS and Sensors supply chain needs to evolve to address the explosive growth in China.

SEMI praised the bipartisan effort in the United States House of Representatives to pass H.R. 2996, the Revitalize American Manufacturing and Innovation (RAMI) Act.  SEMI further urged the Senate to move quickly on the legislation that would create public private partnerships to establish institutes for manufacturing innovation.

Jeff Wilson, Mentor Graphics, writes that in integrated circuit (IC) design, we’re currently seeing the makings of a perfect storm when it comes to the growing complexity of fill. The driving factors contributing to the growth of this storm are the shrinking feature sizes and spacing requirements between fill shapes, new manufacturing processes that use fill to meet uniformity requirements, and larger design sizes that require more fill.

Zvi Or-Bach, president and CEO of MonolithIC 3D, blogs that at the upcoming 2014 IEEE S3S conference (October 6-9), MonolithIC 3D will unveil a breakthrough flow that is game-changing for 3D IC. For the first time ever monolithic 3D (“M3DI”) could be built using the existing fab and the existing transistor flow.

The Week in Review: Dec. 6, 2013

Friday, December 6th, 2013

Worldwide sales of semiconductors reached $27.06 billion for the month of October 2013, a 7.2 percent increase from the same month last year when sales were $25.24 billion, according to preliminary results by Gartner, Inc. The top 25 semiconductor vendors’ combined revenue increased 6.2 percent, a significantly better performance than the rest of the market, whose revenue growth was 2.9 percent. This was, in part, due to the concentration of memory vendors, which saw significant growth in the top ranking.

Soitec, a manufacturer semiconductor materials for the electronics and energy industries, this week announced it has reached high-volume manufacturing of its new Enhanced Signal Integrity (eSI) substrates. Soitec’s eSI products, based on Smart Cut technology, are the first “trap-rich” type of material in full production. These substrates, on which devices are manufactured, have a significant impact on the final devices’ performance. Soitec’s eSI substrates are designed by introducing an innovative material (a trap-rich layer) between the high-resistivity handle wafer and the buried oxide. This layer limits the parasitic surface conduction present in standard high-resistivity silicon-on-insulator (HR-SOI) substrates, boosting the performance of RF devices. Because this layer is built into the substrate, it reduces the number of process steps and relaxes design rules, leading to a lower cost process and possibly a smaller die area per function.

SEMI projects that worldwide sales of new semiconductor manufacturing equipment will contract 13.3 percent to $32.0 billion in 2013, according to the SEMI Year-end Forecast, released this week at the annual SEMICON Japan exposition.  In 2014, all regions except Rest of World are expected to have strong positive growth, resulting in a global increase of 23.2 percent in sales. 2015 sales are expected to continue to grow — increasing 2.4 percent with Japan, Europe, Korea, China, and Rest of World regions registering positive growth.

Micron Technology, Inc. announced that the company has named Rajan Rajgopal, vice president of Quality. Rajgopal will be responsible for overseeing all aspects of Micron’s quality systems including manufacturing, customer program management and product ramps. He brings more than 25 years of experience to Micron and most recently served as the vice president of Global Quality and Customer Enablement for GLOBALFOUNDRIES in Singapore.

SEMI’s World Fab Forecast report, published in November, predicts that fab equipment spending will decline about -9 percent (to US$32.5 billion) in 2013 (including new, used and in-house manufactured equipment).  Setting aside the used 300mm equipment GlobalFoundries acquired from Promos at the beginning of 2013 (NT$20-30 billion), fab equipment spending sinks further, to -11 percent in 2013.  The previous World Fab Forecast in August predicted an annual decline of just -1 percent (-3 percent without the used Promos 300mm equipment).

Worldwide sales of semiconductors reached $27.06 billion for the month of October 2013, a 7.2 percent increase from the same month last year when sales were $25.24 billion, and 0.8 percent higher than last month’s total, according to The Semiconductor Industry Association (SIA). “With eight straight months of growth and a new monthly sales record in October, the global semiconductor industry is on track to exceed $300 billion in annual sales for the first time ever in 2013,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “The industry is projected to maintain solid growth for the remainder of 2013 and into 2014, led largely by the Americas, which has remained well ahead of last year’s pace. Congress and the Administration can help maintain and strengthen growth by resolving fiscal uncertainty and investing in scientific research.”

RF-SOI Wafers for Wireless Applications

Thursday, December 5th, 2013

The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.

This paper explains the value of using RF-SOI substrates and what the latest generation of Soitec Wave SOI (Soitec eSI™) brings to RF IC performance while simplifying the IC manufacturing process in order to address the mainstream smart phone market.

To download this white paper, click here.

The Week In Review: Nov. 7, 2013

Friday, November 8th, 2013

Peregrine Semiconductor Corp. and GLOBALFOUNDRIES are sampling the first RF Switches built on Peregrine’s new UltraCMOS 10 RF SOI technologies. This partnership unites Peregrine’s 25 years of RF SOI experience with a tier-one foundry. In a joint development effort, GLOBALFOUNDRIES and Peregrine created a unique fabrication flow for the versatile, new, 130 nm UltraCMOS 10 technology platform. This new technology delivers a more than 50-percent performance improvement over comparable solutions. UltraCMOS 10 technology gives smartphone manufacturers unparalleled flexibility and value without compromising quality for devices ranging from 3G through LTE networks.

Peregrine Semiconductor this week celebrated two significant milestones – its 25th anniversary of pioneering RF SOI solutions and the shipment of the two-billionth chip. Peregrine reaches the two-billionth-chip milestone in an order to Murata Manufacturing Company, the supplier of RF front-end modules for the global mobile wireless marketplace.

Rubicon Technology announced the launch of the first commercial line of large diameter patterned sapphire substrates (PSS) in four-inch through eight-inch diameters.  This new product line provides LED chip manufacturers with a ready-made source of large diameter PSS to serve the needs of the rapidly growing LED general lighting industry.

Semiconductor Research Corporation and Northeastern University researchers announced advancements in radio-frequency (RF) circuit technology that promise to improve and widen the applications of mobile devices.

Imec announced that it has successfully demonstrated the first III-V compound semiconductor FinFET devices integrated epitaxially on 300mm silicon wafers, through a unique silicon fin replacement process. The achievement illustrates progress toward 300mm and future 450mm high-volume wafer manufacturing of advanced heterogeneous CMOS devices, monolithically integrating high-density compound semiconductors on silicon.

STMicroelectronics announced this week its close collaboration with Memoir Systems has made the revolutionary Algorithmic Memory Technology available for embedded memories in application-specific integrated circuits (ASICs) and Systems on Chips (SoCs) manufactured in ST’s fully-depleted silicon-on-insulator (FD-SOI) process technology.

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