Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘RC’

Air-Gaps for FinFETs Shown at IEDM

Friday, October 28th, 2016

thumbnail

By Ed Korczynski, Sr. Technical Editor

Researchers from IBM and Globalfoundries will report on the first use of “air-gaps” as part of the dielectric insulation around active gates of “10nm-node” finFETs at the upcoming International Electron Devices Meeting (IEDM) of the IEEE (ieee-iedm.org). Happening in San Francisco in early December, IEDM 2016 will again provide a forum for the world’s leading R&D teams to show off their latest-greatest devices, including 7nm-node finFETs by IBM/Globalfoundries/Samsung and by TSMC. Air-gaps reduce the dielectric capacitance that slows down ICs, so their integration into transistor structures leads to faster logic chips.

History of Airgaps – ILD and IPD

As this editor recently covered at SemiMD, in 1998, Ben Shieh—then a researcher at Stanford University and now a foundry interface for Apple Corp.—first published (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) on the use of controlled pitch design combined with CVD dielectrics to form “pinched-off keyholes” in cross-sections of inter-layer dielectrics (ILD).

In 2007, IBM researchers showed a way to use sacrificial dielectric layers as part of a subtractive process that allows air-gaps to be integrated into any existing dielectric structure. In an interview with this editor at that time, IBM Fellow Dan Edelstein explained, “we use lithography to etch a narrow channel down so it will cap off, then deliberated damage the dielectric and etch so it looks like a balloon. We get a big gap with a drop in capacitance and then a small slot that gets pinched off.

Intel presented on their integration of air-gaps into on-chip interconnects at IITC in 2010 but delayed use until the company’s 14nm-node reached production in 2014. 2D-NAND fabs have been using air-gaps as part of the inter-poly dielectric (IPD) for many years, so there is precedent for integration near the gate-stack.

Airgaps for finFETs

Now researchers from IBM and Globalfoundries will report in (IEDM Paper #17.1, “Air Spacer for 10nm FinFET CMOS and Beyond,” K. Cheng et al) on the first air-gaps used at the transistor level in logic. Figure 1 shows that for these “10nm-node” finFETs the dielectric spacing—including the air-gap and both sides of the dielectric liner—is about 10 nm. The liner needs to be ~2nm thin so that ~1nm of ultra-low-k sacrificial dielectric remains on either side of the ~5nm air-gap.

Fig.1: Schematic of partial air-gaps only above fin tops using dielectric liners to protect gate stacks during air-gap formation for 10nm finFET CMOS and beyond. (source: IEDM 2016, Paper#17.1, Fig.12)

These air-gaps reduced capacitance at the transistor level by as much as 25%, and in a ring oscillator test circuit by as much as 15%. The researchers say a partial integration scheme—where the air-gaps are formed only above the tops of fin— minimizes damage to the FinFET, as does the high-selectivity etching process used to fabricate them.

Figure 2 shows a cross-section transmission electron micrograph (TEM) of what can go wrong with etch-back air-gaps when all of the processes are not properly controlled. Because there are inherent process:design interactions needed to form repeatable air-gaps of desired shapes, this integration scheme should be extendable “beyond” the “10-nm node” to finFETs formed at tighter pitches. However, it seems likely that “5nm-node” logic FETs will use arrays of horizontal silicon nano-wires (NW), for which more complex air-gap integration schemes would seem to be needed.

Fig.2: TEM image of FinFET transistor damage—specifically, erosion of the fin and source-drain epitaxy—by improper etch-back of the air-gaps at 10nm dimensions. (source: IEDM 2016, Paper#17.1, Fig.10)

—E.K.

New Tungsten Barrier/Liner, Fill Processes Reduce Resistance and Increase Yield

Friday, June 3rd, 2016

thumbnail

By Pete Singer, Editor-in-Chief

Today’s most advanced chips pack two billion transistors on a die size of 100 mm2. Considering transistors are three terminal devices, that equates to six billion contacts to those transistors, which connect to 10-15 Layers of stacked wiring. Although the wiring is copper, the contacts at the transistor level and the so-called local interconnect level just above the contact level are made of tungsten (Figure 1). Although tungsten has slightly higher resistance than copper, the danger of copper contamination killing the transistor is such that tungsten is still used.

Figure 1. The contact (black area) is the first, smallest, most critical connection between the transistor and interconnect wiring. Source: TECHINSIGHTS

Two looming problems are that contact resistance is going up, to the point where it will soon be higher than that of the transistor (Figure 2). Yield is also at risk since just one bad contact can cause entire portions of the chip to fail. “Not only are there a lot of these contacts, they’re very challenging to make because they are so small and getting even smaller with each node,” said Jonathan Bakke, Global Product Manager, Transistor and Interconnect Group, Applied Materials.

Figure 2. At the 10nm node and beyond, contact and plug resistance is expected to rise exponentially and dominate.

Applied Materials recently launched two new products aimed at reducing contact resistance and improving yield in tungsten contacts. The Applied Endura® Volta™ CVD W product results in a new tungsten-based material that serves as both a barrier and a liner, enabling the lower resistance W fill to be three times wider than in traditional process flows. The end result is an increase of up to 90% in contact resistance. The Applied Centura® iSprint™ ALD/CVD SSW (seam-suppressed tungsten) product achieves bottom-up gap fill in tungsten contact CVD processes, reducing seams and voids, which increases yield.

The traditional process flow to from a contact has been to deposit a layer of titanium to form a silicide layer by reacting with the silicon, followed by a TiN barrier. This barrier film prevents the diffusion of fluorine into the silicon of the transistor from the tungsten hexafluoride (WF6) used to deposit the subsequent tungsten contact fill. Because tungsten doesn’t grow directly on TiN, a seed layer of W is typically deposited by ALD before the WF6 CVD bulk fill.

Two challenges associated with this approach is that the barrier and liner have not scaled – they have been made as thin as possible, but they’ve reached a limit. The TiN barrier is typically around 30-40Å and the liner film another 20Å. As a result, the volume of the overall plug made of the more desirable, lower resistance W is reduced. “The TiN and tungsten based liner are both high resistance layers. The more volume they occupy, the more they contribute to resistance,” Bakke said.

The second challenge is that, because the W CVD process results in a conformal fill, where all sides grow at the same rate, a seam is often formed in the middle of the contact. Or, even worse, the top closes before the W completely fills the contact hole, resulting in a void. Both seams and voids can be exposed or breached during the subsequent chemical mechanical planarization (CMP) step. “The contacts or local interconnects are becoming much smaller with each node and they’re getting more challenging to fill with low resistance material and without seams or voids,” Bakke said. Figure 3 shows common problems with resistance and yield.

Figure 3: Barriers and liners don't scale, leaving less room for low resistance W fill. Seams and voids can cause yield problems.

Seams and voids can lead to yield problems such as overly high contact resist or even open contacts. If even a few of the 6 billion contacts on a chip fail, there can a big impact on yield. One study (Figure 4), shows that even at the 20nm node, one defect in a billion can lead to a yield loss of 15% or more. “This tells you that you really have to have perfect gap fill. If one contact goes, it can knock out an entire portion of the device and make it inoperable,” Bakke said.

Figure 4. Source: Nvidia

Enter the Applied Endura® Volta™ CVD W and the Applied Centura® iSprint™ ALD/CVD SSW (seam-suppressed tungsten).

A process has been developed for the Endura – Applied’s platform for metal deposition, including PVD and CVD – to deposit a tungsten-based CVD film that serves as both the barrier layer and the liner layer. At around the 30Å thickness that would be typical of just the barrier, and it’s as effective a barrier as TiN. “We’re doing materials engineering to create the first new liner for tungsten plug in 10 years,” Bakke said. This means more of the volume of the contact consists of the lower resistivity W fill (Figure 5). “You can actually triple the tungsten fill width at the 15 nm node. You get a lot more low-resistance material in there. Beyond that, it’s a simpler process flow, by removing the one layer, the liner,” Bakke added.

Figure 5

Figure 6 shows how the new W-based barrier/liner compares to the standard flow. The tungsten-based film is 75% lower in resistitivity that the TiN (left). At thicknesses which are relevant for the 10nm node, an 80% reduction in total stack resistivity is seen (right).

Figure 6

Perhaps even more important is the contact resistance, as shown in Figure 7, which charts contact resistance vs critical dimension. “By the time you’re getting to the 10 and 7nm node thicknesses, you actually have a big drop in resistivity up to about 90% reduction in resistance at the 7nm node thicknesses,” Bakke explained.

Figure 7

One reason why plug resistance is becoming more important is indicated by the orange line in Fig. 7, which shows silicide contact resistance. “For a long time, the silicide was the big contributor to the transistor contact total resistance. Manufacturers spent a lot time trying to decrease that resistance as they scaled. There’s a cross-over point (blue line) where the plug starts become of higher resistance than the contact. We need to focus on bring the plug resistance back down so it’s not the major contributor to the total resistance,” Bakke said.

Figure 8 shows the end result, with a clean interface between both the tungsten and underlying tungsten layer. “The Volta W adheres very well to dielectric sidewalls. And the W fill is able to deposit on the Volta W and give good gap fill performance,” said Bakke. “It’s also able to survive all the post-processing steps, such as CMP and deposition of copper.”

Figure 8. Degas, clean and Volta W are integrated in the Endura platform.

The Applied Centura® iSprint™ ALD/CVD SSW process uses a “special treatment” after the liner (or barrier/liner in the case of Volta W) to suppress growth on the field and induce growth in a bottom-up fashion (Figure 9). This bottom-up growth eliminates seams and voids. “Because you have a more robust fill, you get an improved yield because you don’t breach the contact or local interconnect during the CMP step,” Bakke said. “This is the first bottom-up tungsten CVD in high volume manufacturing,” he added.

Figure 9. Bottom-up fill is shown in a diagram (top) and in an actual structure.

Bakke wouldn’t say what the special treatment was, but a patent search revealed a possible approach, involving activated nitrogen where the activated nitrogen is deposited preferentially on the surface regions.

Air-gaps in Copper Interconnects for Logic

Friday, October 31st, 2014

thumbnail

By Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The good people at ChipWorks have released some of the first public data on Intel’s new 14nm-node process, and the results indicate that materials limitations in on-chip electrical interconnects are adding costs. Additional levels of metal have been added, and complex “air-gap” structures have been added to the dielectric stack. Flash memory chips have already used air-gaps, and IBM has already used a subtractive variant of air-gaps with >10 levels of metal for microprocessor manufacturing, but this is the first known use of additive air-gaps for logic after Intel announced that a fully-integrated process was ready for 22nm-node chips.

Mark Bohr of Intel famously published data in 1995 (DOI:  10.1109/IEDM.1995.499187) on the inherent circuit speed limitations of interconnects, showing proportionality to the resistance (R) of the metal lines multiplied by the capacitance (C) of the dielectric insulation around the metal (Fig.1). The RC product thus should be minimized for maximum circuit speed, but the materials used for both the metal and the dielectric insulation around metal lines are at limits of affordability in manufacturing.

There are no materials that super-conduct electricity at room temperature, and only expensive and room-sized supercomputers and telecommunications base-stations can afford to use the liquid-nitrogen cooling that is needed for known superconductors to function. Carbon Nano-Tubes (CNT) and 2D atomic-layers of carbon in the form of graphene can conduct ballistically, but integration costs and electrical contact resistances limit use. Copper metal remains as the best electrical conductor for on-chip interconnects, yet as horizontal lines and vertical vias continue to shrink in cross-sectional area the current density has reached the limit of reliability. The result is the increase in the number of metal layers to 13 for 14nm-node Intel microprocessors, while IBM used 15 layers for 22nm-node Power8 chips.

Low-k Dielectrics and Pore Sizes

The dielectric constant (“k”) of silicon oxide is ~4, and ~3.5 with the addition of fluorine to the oxide (SiOF). Carbon-Doped Oxide (CDO or SiOC or SiOC:H) with k~3.0 has been integrated well into interconnect stacks. Some polymers can provide k values in the 2.0-2.7, but they cannot be integrated into most interconnects due to lack of mechanical strength, chemical resistance, and overall stability. Air has k=1, and there have been specialized chips made using metal wires floating in air, but lack of physical structure results in poor manufacturing yield and weak reliability.

A clever compromise is to use both SiOC with k~3 and air with k~1 in a stack, which results in an integrated k value weighted by the percent of the volume taken up by each phase. Porous Low-k (PLK) with 10% porosity allows for an integrated k of ~2.7 for modest improvement, but increasing porosity to just 20% for k~2.4 results in connected random pores that reduce reliability. To reliably integrate 20-30% air into SiOC, the pores cannot be random but must be engineered as discrete gaps in the structure.

In 2007, IBM announced that it would engineer air-gaps in microprocessors, but the company claimed to be using an extremely complex process for integration involving a self-assembled thin-film mask to anisotropically etch out holes between lines and then further isotropic etching to form elongated pores. Though relatively complex and expensive, this process allows for the use of any 2D layout for lines in a given metal layer.

Additive Air-gap Process-Design Integration

For fab lines that are still working with aluminum metal and additive dielectrics, air-gaps are a defect that occurs with imperfect dielectric fill. When not planned as part of the design, air-gaps formed in a lower-layer can be exposed to etchants during subsequent processing resulting in metal shorts or opens. However, Figure 2 shows that it is possible to engineer air-gaps by Chemical-Vapor Deposition (CVD) of dielectric material into line-space structures with proper process control and design layout restrictions. Twenty years ago, this editor worked for an OEM on CVD processes for dielectric fill, and the process can be tuned to be highly repeatable and relatively low-cost if a critical masking step can be avoided. In 1998, Shieh et al. from Stanford (Shieh, Saraswat & McVittie. IEEE Electron Dev. Lett., January 1998) showed proof-of-concept for this approach to lower k values.

Figure 2: CVD can be easily tuned to initially coat sidewalls (top), then pinch-off (middle), and finally form a closed pore (bottom) during one step. (Source: Ed Korczynski)

Four years ago at IEDM 2010, Intel presented details of how to engineer air-gaps using CVD. As this editor wrote at that time in an extensive analysis:

The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldnt automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional dual-damascene flow, with the option to add air-gaps.

Now we know that Intel kept air-gaps on the metaphorical shelf by skipping use at the 22nm-node. The 2014 IEDM paper from Intel will discuss details of 14nm-node air-gaps:   two levels at 80nm and 160nm minimum pitches, yielding a 17% reduction in capacitance delays.

This process requires regularly spaced 1D line arrays as a design constraint, which may also be part of the reason for additional metal layers to allow for 2D connections through vias. Due to lithography resolution advantages with 1D “gridded” layouts, other logic fabs may soon run 1D designs at which point additive air-gaps like that used by Intel will provide a relatively easy boost to IC speeds.