By Pete Singer, Editor-in-Chief
Today’s most advanced chips pack two billion transistors on a die size of 100 mm2. Considering transistors are three terminal devices, that equates to six billion contacts to those transistors, which connect to 10-15 Layers of stacked wiring. Although the wiring is copper, the contacts at the transistor level and the so-called local interconnect level just above the contact level are made of tungsten (Figure 1). Although tungsten has slightly higher resistance than copper, the danger of copper contamination killing the transistor is such that tungsten is still used.
Figure 1. The contact (black area) is the first, smallest, most critical connection between the transistor and interconnect wiring. Source: TECHINSIGHTS
Two looming problems are that contact resistance is going up, to the point where it will soon be higher than that of the transistor (Figure 2). Yield is also at risk since just one bad contact can cause entire portions of the chip to fail. “Not only are there a lot of these contacts, they’re very challenging to make because they are so small and getting even smaller with each node,” said Jonathan Bakke, Global Product Manager, Transistor and Interconnect Group, Applied Materials.
Figure 2. At the 10nm node and beyond, contact and plug resistance is expected to rise exponentially and dominate.
Applied Materials recently launched two new products aimed at reducing contact resistance and improving yield in tungsten contacts. The Applied Endura® Volta™ CVD W product results in a new tungsten-based material that serves as both a barrier and a liner, enabling the lower resistance W fill to be three times wider than in traditional process flows. The end result is an increase of up to 90% in contact resistance. The Applied Centura® iSprint™ ALD/CVD SSW (seam-suppressed tungsten) product achieves bottom-up gap fill in tungsten contact CVD processes, reducing seams and voids, which increases yield.
The traditional process flow to from a contact has been to deposit a layer of titanium to form a silicide layer by reacting with the silicon, followed by a TiN barrier. This barrier film prevents the diffusion of fluorine into the silicon of the transistor from the tungsten hexafluoride (WF6) used to deposit the subsequent tungsten contact fill. Because tungsten doesn’t grow directly on TiN, a seed layer of W is typically deposited by ALD before the WF6 CVD bulk fill.
Two challenges associated with this approach is that the barrier and liner have not scaled – they have been made as thin as possible, but they’ve reached a limit. The TiN barrier is typically around 30-40Å and the liner film another 20Å. As a result, the volume of the overall plug made of the more desirable, lower resistance W is reduced. “The TiN and tungsten based liner are both high resistance layers. The more volume they occupy, the more they contribute to resistance,” Bakke said.
The second challenge is that, because the W CVD process results in a conformal fill, where all sides grow at the same rate, a seam is often formed in the middle of the contact. Or, even worse, the top closes before the W completely fills the contact hole, resulting in a void. Both seams and voids can be exposed or breached during the subsequent chemical mechanical planarization (CMP) step. “The contacts or local interconnects are becoming much smaller with each node and they’re getting more challenging to fill with low resistance material and without seams or voids,” Bakke said. Figure 3 shows common problems with resistance and yield.
Figure 3: Barriers and liners don't scale, leaving less room for low resistance W fill. Seams and voids can cause yield problems.
Seams and voids can lead to yield problems such as overly high contact resist or even open contacts. If even a few of the 6 billion contacts on a chip fail, there can a big impact on yield. One study (Figure 4), shows that even at the 20nm node, one defect in a billion can lead to a yield loss of 15% or more. “This tells you that you really have to have perfect gap fill. If one contact goes, it can knock out an entire portion of the device and make it inoperable,” Bakke said.
Figure 4. Source: Nvidia
Enter the Applied Endura® Volta™ CVD W and the Applied Centura® iSprint™ ALD/CVD SSW (seam-suppressed tungsten).
A process has been developed for the Endura – Applied’s platform for metal deposition, including PVD and CVD – to deposit a tungsten-based CVD film that serves as both the barrier layer and the liner layer. At around the 30Å thickness that would be typical of just the barrier, and it’s as effective a barrier as TiN. “We’re doing materials engineering to create the first new liner for tungsten plug in 10 years,” Bakke said. This means more of the volume of the contact consists of the lower resistivity W fill (Figure 5). “You can actually triple the tungsten fill width at the 15 nm node. You get a lot more low-resistance material in there. Beyond that, it’s a simpler process flow, by removing the one layer, the liner,” Bakke added.
Figure 6 shows how the new W-based barrier/liner compares to the standard flow. The tungsten-based film is 75% lower in resistitivity that the TiN (left). At thicknesses which are relevant for the 10nm node, an 80% reduction in total stack resistivity is seen (right).
Perhaps even more important is the contact resistance, as shown in Figure 7, which charts contact resistance vs critical dimension. “By the time you’re getting to the 10 and 7nm node thicknesses, you actually have a big drop in resistivity up to about 90% reduction in resistance at the 7nm node thicknesses,” Bakke explained.
One reason why plug resistance is becoming more important is indicated by the orange line in Fig. 7, which shows silicide contact resistance. “For a long time, the silicide was the big contributor to the transistor contact total resistance. Manufacturers spent a lot time trying to decrease that resistance as they scaled. There’s a cross-over point (blue line) where the plug starts become of higher resistance than the contact. We need to focus on bring the plug resistance back down so it’s not the major contributor to the total resistance,” Bakke said.
Figure 8 shows the end result, with a clean interface between both the tungsten and underlying tungsten layer. “The Volta W adheres very well to dielectric sidewalls. And the W fill is able to deposit on the Volta W and give good gap fill performance,” said Bakke. “It’s also able to survive all the post-processing steps, such as CMP and deposition of copper.”
Figure 8. Degas, clean and Volta W are integrated in the Endura platform.
The Applied Centura® iSprint™ ALD/CVD SSW process uses a “special treatment” after the liner (or barrier/liner in the case of Volta W) to suppress growth on the field and induce growth in a bottom-up fashion (Figure 9). This bottom-up growth eliminates seams and voids. “Because you have a more robust fill, you get an improved yield because you don’t breach the contact or local interconnect during the CMP step,” Bakke said. “This is the first bottom-up tungsten CVD in high volume manufacturing,” he added.
Figure 9. Bottom-up fill is shown in a diagram (top) and in an actual structure.
Bakke wouldn’t say what the special treatment was, but a patent search revealed a possible approach, involving activated nitrogen where the activated nitrogen is deposited preferentially on the surface regions.