Bionic Ears
Using a 3D printer, Princeton University has devised a bionic ear. The fully functional ear is said to hear radio frequencies far beyond the range of normal human capability.

The idea behind the research is to merge electronics with tissue. The ability to devise 3D biological tissue with functional electronics could enable the creation of bionic organs, according to researchers. But current electronics are limited to 2D structures, preventing the integration of biological systems and conventional chips.

Researchers have devised a novel strategy to overcome these difficulties. In a proof of concept, Princeton used a 3D printer to devise a cell-seeded hydrogel matrix in the precise anatomic geometry of a human ear. Researchers also intertwined a conducting polymer consisting of silver nanoparticles. “This allowed for the in vitro culturing of cartilage tissue around an inductive coil antenna in the ear, which subsequently connects to cochlear-like electrodes,” according to researchers.

The printed ear exhibits enhanced auditory sensing for RF reception. “In general, there are mechanical and thermal challenges with interfacing electronic materials with biological materials,” said Michael McAlpine, an assistant professor of mechanical and aerospace engineering at Princeton, on the university’s Web site. “Previously, researchers have suggested some strategies to tailor the electronics so that this merger is less awkward. That typically happens between a 2D sheet of electronics and a surface of the tissue. However, our work suggests a new approach—to build and grow the biology up with the electronics synergistically and in a 3D interwoven format.”

Super Microscopes
Purdue University has devised a new super-resolution optical microscopy technology, thereby paving the way to view structures on the nanoscopic scale.

The imaging system, called saturated transient absorption microscopy, (STAM), is designed for use in biomedical and nanotechnology research. Researchers have taken images of graphite nanoplatelets at about 100nm wide. Researchers hope to improve the imaging system to see objects at about 10nm in diameter. This is about 30 times smaller than possible using conventional optical microscopes.

A new type of super-resolution optical microscopy takes a high-resolution image (at right) of graphite "nanoplatelets" about 100 nanometers wide. The imaging system, called saturated transient absorption microscopy, or STAM, uses a trio of laser beams and represents a practical tool for biomedical and nanotechnology research. (Weldon School of Biomedical Engineering, Purdue University)

Current far-field, super-resolution techniques rely on fluorescence as the readout. However, Purdue has demonstrated a scheme for breaking the diffraction limit in far-field imaging of non-fluorescent species. Researchers accomplished this by using spatially controlled saturation of electronic absorption.

The method is based on a pump–probe process, where a modulated pump field perturbs the charge carrier density in a sample, according to Purdue. This, in turn, modulates the transmission of a probe field, according to researchers.

A doughnut-shaped laser beam is then added to transiently saturate the electronic transition in the periphery of the focal volume. The induced modulation in the sequential probe pulse only occurs at the focal center. By raster-scanning the three collinearly aligned beams, high-speed subdiffraction-limited imaging of graphite nanoplatelets is performed.

Diamonds Are Forever
Element Six and Delft University of Technology have demonstrated the entanglement of an electron spin effect of quantum bits in two synthetic diamonds separated in space. This is a step toward achieving a diamond-based quantum network, quantum repeaters and long-distance teleportation, thereby changing the way information is processed in networks and computers.

The collaboration used two synthetic diamonds of millimeter-size that were grown by Element Six through a proprietary chemical vapor deposition (CVD) technology. The synthetic diamonds were engineered to contain a particular defect that can be manipulated using light and microwaves. The defect consists of a single nitrogen atom adjacent to a missing carbon atom—known as a nitrogen vacancy (NV) defect.

The entanglement process is what Albert Einstein called “spooky action at a distance.” This is a process where the two NV defects become strongly connected such that they are always correlated irrespective of the distance between them.

Researchers were able to make the two NV defects emit indistinguishable particles of light or photons. These photons contained the quantum information of the NV defect and further manipulation allowed the quantum mechanically entanglement of the two defects.

“By applying the invaluable knowledge gained in our research, we’re able to successfully develop and advance extreme performance solutions for our customers that capitalize on synthetic diamond’s unique combination of properties, which can subsequently be leveraged across a range of industries,” said Adrian Wilson, head of Element Six, a developer of synthetic diamonds and a member of the De Beers Group.

—Mark LaPedus

Santa’s IC Manufacturing Process?
Purdue University and Harvard University have devised a new type of 4D transistor shaped like a Christmas tree.

At this week’s 2012 IEEE International Electron Devices Meeting (IEDM) in San Francisco, the universities will jointly described a III-V gate-all-around nanowire MOSFET. Each transistor contains three nanowires based indium-gallium-arsenide. The three nanowires are progressively smaller. A tapered cross section of the device resembles a Christmas tree.

The transistor is made from tiny nanowires of a material called indium-gallium-arsenide, which could replace silicon within a decade. Source: Purdue

Researchers have demonstrated a III-V 4D transistor fabrication process using atomic layer deposition (ALD). The ION/W pitch and gm/Wpitch were 9mA/μm and 6.2mS/μm, respectively. The 4D transistors show a 4x improvement over the III-V 3D transistors.

“It’s a preview of things to come in the semiconductor industry,” said Peide Ye, a professor of electrical and computer engineering at Purdue, on the university’s site. “A one-story house can hold so many people, but more floors, more people, and it’s the same thing with transistors. Stacking them results in more current and much faster operation for high-speed computing. This adds a whole new dimension, so I call them 4-D.”

Defying Diffraction
The development of photonics on the deep sub-wavelength and nanoscale level presents a number of challenges. Once you reach the diffraction limit, it’s physically impossible to focus the light.

The California Institute of Technology has devised a metal–insulator–metal gap plasmon waveguide with a three-dimensional linear taper. The waveguide, a device that channels light, is able to defy physics and get around the diffraction limit.

The waveguide is made of amorphous silicon dioxide and is covered in a thin layer of gold. The device is built on a semiconductor chip using a standard manufacturing process.

Researchers demonstrated efficient nanofocusing of a gold–silicon dioxide-gold gap plasmon waveguide. The dimensions of the silicon dioxide layer, perpendicular to the direction of wave propagation, tapers linearly below 100nm.

Simulations suggest that the three-dimensional linear-tapering approach could focus 830nm light into a 2- × 5nm2 area with ≤3 dB loss and an intensity enhancement of 3.0 × 104. In a two-photon luminescence measurement, the device achieved an intensity enhancement of 400 within a 14 × 80nm2 area, and a transmittance of 74%.

New Twist On ALD
Atomic layer deposition (ALD) deposits conformal thin-films one atom at a time. The Missouri University of Science and Technology has put a new twist on the technology called atomic-layer electrodeposition.

One application of this new electrochemical ALD method is to deposit ultrathin layers of platinum. Platinum is used as the catalyst in membrane fuel cells and other products. ALD is usually conducted in the vapor phase. In contrast, researchers from the university demonstrated the ability to sequentially electrodeposit two-dimensional platinum layer-by-layer. In doing so, researchers simply pulsed the applied electrochemical potential in a single plating bath.

A scanning electron microscope image of the nano-focusing device. Source: CalTech

The process is fast and inexpensive. Because each layer is produced by cycling the potential rather than by exchange of reactants, electrochemical ALD could be orders of magnitude faster than vapor-phase ALD. A single layer of platinum, placed on the surface at a voltage that should create a thick deposit of the metal, creates the layer of hydrogen that limits the thickness of the platinum layer, according to researchers.

“Conventional wisdom would suggest that the best way to electrodeposit ultra-thin metal films would be to apply either an underpotential or a very small overpotential,” said Jay Switzer, professor of chemistry at Missouri S&T, on the university’s Web site.

—Mark LaPedus

SOI Prevents Dropped Calls
Tired of dropped calls or slow Internet service on cell phones?

One enabling technology is the development of more precise filter components. For example, Purdue University has devised a nanoelectromechanical resonator, based on silicon-on-insulator (SOI) technology.

Resonant nanoelectromechanical systems (NEMS) could be used in mass sensing, signal processing and field detection applications. The nanoresonators from Purdue were shown to control their vibration frequencies better than other resonators.

This image from a scanning electron microscope shows a tiny mechanical device, an electrostatically actuated nanoresonator, that might ease congestion over the airwaves to improve the performance of cell phones and other portable devices. (Purdue University image)

The key part of Purdue’s device is a silicon beam, which is attached at two ends. The beam, which vibrates in the center, has a 130nm feature size. Applying a current to the beam causes it to vibrate side-to-side or up and down. The beam can be adjusted or tuned.

These devices are made on an SOI substrate using a top-down fabrication technique. It can be integrated with CMOS transistors, enabling the development of devices with highly tunable, nonlinear frequency response characteristics.

“We are not inventing a new technology, we are making them using a process that’s amenable to large-scale fabrication, which overcomes one of the biggest obstacles to the widespread commercial use of these devices,” said Jeffrey Rhoads, an associate professor of mechanical engineering at Purdue University.

The new SOI resonators could provide higher performance than current components and MEMS systems. “It is very difficult to make a good tunable filter with transistors, inductors and other electronic components, but a simple nanomechanical resonator can do the job with much better performance and at a fraction of the power,” said Saeed Mohammadi, an associate professor of electrical and computer engineering at Purdue.

“Because the devices are tiny and the fabrication has almost a 100 percent yield, we can pack millions of these devices in a small chip if we need to,” Mohammadi said. “It’s too early to know exactly how these will find application in computing, but since we can make these tiny mechanical devices as easily as transistors, we should be able to mix and match them with each other and also with transistors in order to achieve specific functions. Not only can you put them side-by-side with standard computer and electronic chips, but they tend to work with near 100 percent reliability.”

SOI Enables Flexible Electronics
Wayne State University has developed a SOI technology for use in making flexible electronic products.

Researchers from Wayne State have fabricated CMOS circuits onto SOI wafers. They also incorporate two layers of a polymer called Parylene C. One of the layers is perforated in order to bond it to a flexible substrate.

The parylene layer is use to protect the substrate from environmental moisture. Parylene is the trade name for a variety of chemical vapor deposited poly(p-xylylene) polymers.

“The ultimate goal is to develop flexible and stretchable systems integrated with electronics, sensors, microfluidics, and power sources, which will have a profound impact on personalized medicine, telemedicine and health care delivery,” said Yong Xu, associate professor of electrical and computer engineering in the College of Engineering at Wayne State.

The technology could result in retinal prostheses. Other applications include balloon catheters, stents and other products.

Researchers Devise Twisted Lasers
The University of Liverpool has developed new technique for laser micro-machining for use in semiconductor, industrial and medical applications.

Typically, lasers have linear polarizations, where the beam is vertical. Using twisted wave-fronts to transform the electric field, Liverpool has devised a laser with radial and azimuthal polarizations. In this technology, there is a directional change of the electric field.

Researchers used a 100 femtosecond-pulse laser source and a spatial light modulator in order to change the polarization. “This technology and these new modes of polarization enabled us to achieve significant gains in processing speed and quality,” said Olivier Allegre, who is in the School of Engineering at Liverpool University.

The team used twisted wave-fronts to transform the electric field. Source: University of Liverpool.

“We will now study how this new technique could improve the processing of various materials, such as semiconductors and dielectrics. The technique is also significant for improving image detail in microscopy, and could benefit fluorescence-based imaging of biological samples,” he added.

By Mark LaPedus
The semiconductor industry is currently making a major transition from conventional planar transistors to finFETs starting at 22nm.

The question is what’s next? In the lab, IBM, Intel and others have demonstrated the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of steam, there are no less than 18 different next-generation candidates that could one day replace today’s CMOS-based finFET transistors.

But even the large companies with deep pockets don’t have the time or resources to work on all technologies. “We can’t pick 18,” said Mike Mayberry, vice president and director of components research in the Technology and Manufacturing Group at Intel Corp. “We will develop only a few of them.”

Mayberry said the eventual winners and losers in the next-generation transistor race will be determined by cost, manufacturability and functionality. “The best device is the one you can manufacture,” he said.

In fact, the IC industry is already weeding out the candidates. In 2005, the Semiconductor Research Corp. (SRC), a chip R&D consortium, launched the Nanoelectronics Research Initiative (NRI), a group that is researching futuristic devices capable of replacing the CMOS transistor in the 2020 timeframe. NRI member companies include GlobalFoundries, IBM, Intel, Micron and TI.

So far, the NRI has narrowed down and identified a handful of serious contenders: gate-all-around, silicon nanowires, tunnel field-effect transistors (TFETs), carbon nanotubes, graphene devices, and bilayer pseudo-spin field-effect transistors (BiSFETs).

It’s still too early to determine which future transistor candidate will prevail, said Steven Hillenius, executive vice president of the SRC. “There is still no consensus,” Hillenius said, “but we’ve gone from 20 or so potential devices down to less than 10.”

The finFET and beyond
For now, the industry is banking on the finFET transistor to enable IC scaling for the foreseeable future. The current thinking is that today’s finFET will likely scale at least two generations down to 10nm, said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. Then, at 7nm, the industry is looking at next-generation finFETs based on III-V or other materials to provide a mobility boost, Kengeri said. It’s too early to predict a winner, as “nothing has been settled,” he added.

Indeed, the future is cloudy at and beyond 10nm. According to the 2011 ITRS roadmap, there are a dizzying array of next-generation transistor options on the table: III-V channel replacement finFETs, carbon nanotube FETs, graphene nanoribbon FETs, nanowire FETs, tunnel FETs, spin FETs, IMOS, negative gate capacitance FETs, NEMS switches, atomic switches, MOTT FETs, spin wave devices, nanomagnetic logic, excitonic FETs, BiSFETs, spin torque majority logic gate and all spin logic.

The futuristic candidates likely will require new materials, manufacturing flows and design methodologies. At the SRC, there is one basic criterion to help narrow down the playing field: “The promising new structures are the ones you can put in the current manufacturing flow. The new materials would be used in conjunction with what we are using now,” said SRC’s Hillenius.

For that reason, one transistor candidate has emerged as the favorite in the race. “At this point, the tunnel FET looks like the best option,” said Chenming Calvin Hu, professor of microelectronics at the University of California at Berkeley. Using III-V materials for the channels, TFETs potentially could extend CMOS. Claiming eight times the performance of today’s MOSFETs, TFETs enable a steeper sub-threshold slope less than 60 mV/decade. In TFET, a tunnel barrier is created at the source- channel contact in order to increase the drive current of the transistor.

“It’s likely that the industry will stay with finFETs or tri-gates for the 22nm and 14nm nodes. The earliest introduction of III-V MOSFETs is likely is at the 10nm node. This implies that III-V TFETs will appear no sooner than the 7nm technology node,” said Suman Datta, professor of electrical engineering at Pennsylvania State University.

In the lab, Intel has shown TFETs based on III-V materials like InGaAs. “Penn St. and Notre Dame have been able to use staggered and broken gap tunnel junctions in In(Ga)As/Ga(As)Sb TFETs to demonstrate competitive on-current in experimental devices. These TFETs have all been n-channel demonstrations. Very little work has been toward p-channel TFETs and the next challenge would be the demonstration of steep switching p-channel TFET for complementary TFET logic,” Datta said.

“The biggest barrier is the introduction of III-V compound semiconductors within a state-of-the-art silicon fab. III-V islands need to be grown selectively on 300mm, or by that time on 450mm substrates, with low defect count using a high volume manufacturing technique,” Datta said.

Besides TFETs, silicon nanowires also could be classified as “an extension to the finFET,’’ said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM. Silicon nanowire field-effect transistors (FETs) are structures in which the conventional channel is replaced with tiny nanowires.

Nanowires also enable what’s considered to be the ultimate solution in the IC industry: gate-all-around (GAA) finFETs. GAA FETs can have two or more gates, which are wrapped around by a nanowire channel. In a recent paper, Harvard University and Purdue University demonstrated a gate-all-around III-V MOSFET. The device itself boasts 1, 4, 9 or 19 nanowire channels. One of the key fabrication steps is a controlled release process, which is used to form the InGaAs nanowire channels.

“We would likely see GAA devices two to three generations after tri-gate/finFET technology,” said Jiangjiang Gu, a Ph.D. candidate at the Department of Electrical and Computer Engineering at Purdue. “The biggest challenge for GAA devices with III-V channels is how to fabricate ultra-small nanowires with high mobility surfaces and low interface trap densities by a top-down technology. Other challenges include how to form low resistance contacts to these nanowires and how to reduce variations of the GAA devices.”

Carbon nanotubes and graphene
TFETs, nanowire FETs and GAA are arguably the most straightforward extensions to CMOS. Two other options, carbon nanotubes and graphene-based devices, are promising but more exotic approaches. Carbon nanotubes are grown on full wafers and aligned in one direction. They are subsequently transferred to a target substrate multiple times. IBM, for one, has demonstrated sub-10nm carbon nanotubes.

Carbon nanotube FETs (CNFETs) are “the only FET that is projected to outperform the 11nm node ITRS target,” said H. S. Philip Wong, professor of electrical engineering at Stanford University, in a recent paper. CNFETs, according to Wong, face three major challenges: aligned density; stable p- and n-type doping on the same wafer; and low resistance metal to contact at short contact lengths.

In contrast, graphene consists of one-atom-thick planar sheets, which are packed in honeycomb crystal lattice structures. The technology is expensive and difficult to put into manufacturing. And it doesn’t have a band gap, meaning it can’t be turned off in a system.

Still, there is interest in using graphene as a channel replacement material. IBM, for one, is looking at analog and RF applications for graphene FETs (GFETs). The company has demonstrated a GFET running at 155-GHz with 40nm channel lengths.

In another approach, the University of Texas at Austin has been developing the BiSFET, which is said to have 1,000 times lower power consumption than CMOS. In this device, a p- and an n-type layer of graphene are separated by a dielectric tunnel barrier. Each graphene layer has a metallic contact and is electrostatically coupled to a gate electrode.

“The device is still in an R&D phase. While we have theoretically shown that it should work, we are still struggling to demonstrate functionality in the lab. So at this point, it is premature to think of large scale production,” said Sanjay Banerjee, professor of electrical and computer engineering and director of the Microelectronics Research Center at the University of Texas at Austin.

Researchers are also looking at other technologies. For example, all spin logic (ASL) is gaining interest. ASL uses magnets to represent non-volatile binary data, while the communication between magnets is achieved using spin currents.

Despite the promising research for spin logic and other futuristic devices, the industry faces many challenges to find the right candidate. “Predicting what lies ahead is fraught with peril as our ability to see is dependent on where and how we look,” Intel’s Mayberry said.

Metamaterials, by definition, are man-made. And traditionally, they also are expensive to produce and sometimes difficult to manufacture using traditional semiconductor processes.

Researchers at Purdue University’s College of Engineering in Indiana set out to change that equation, creating a “hyperbolic” metamaterial for optics without the need to add gold or silver. They settled on aluminum-doped zinc oxide, aka AZO.

By creating a structure with 16 layers, alternating AZO and regular zinc oxide, they were able to create optical metamaterials that can actually change the behavior of light. According to the university, light passing from the zinc oxide to the AZO hits an “extreme anisotropy,” which causes the light to disperse hyperbolically.

That effect can be altered further by either varying the levels of aluminum or adding an electrical field. By increasing or decreasing the voltage, the material can be hyperbolic or non-hyperbolic, and act like metal or a dielectric material. That fits in perfectly with quantum computing, which alternates between ones and zeroes depending upon the state, voltage or current applied.

What makes this particularly interesting is that it allows light to be controlled at less than its wavelength. The university says that metamaterials can sharply reduce the refraction index. AZO, in addition, is plasmonic, because it conducts clouds of electrons.

The work is being funded by the U.S. Office of Naval Research, the National Science Foundation, the Air Force Office of Scientific Research, as well as Purdue.

—Ed Sperling