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Posts Tagged ‘photoresist’

Edge Placement Error Control in Multi-Patterning

Thursday, March 2nd, 2017

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By Ed Korczynski, Sr. Technical Editor

SPIE Advanced Lithography remains the technical conference where the leading edge of minimum resolution patterning is explored, even though photolithography is now only part of the story. Leading OEMs continue to impress the industry with more productive ArFi steppers, but the photoresist suppliers and the purveyors of vacuum deposition and etch tools now provide most of the new value-add. Tri-layer-resist (TLR) stacks, specialty hard-masks and anti-reflective coatings (ARC), and complex thin-film depositions and etches all combine to create application-specific lithography solutions tuned to each critical mask.

Multi-patterning using complementary lithography—using argon-fluoride immersion (ArFi) steppers to pattern 1D line arrays plus extreme ultra-violet (EUV) tools to do line cuts—is under development at all leading edge fabs today. Figure 1 shows that edge placement error (EPE) in lines, cut layers, and vias/contacts between two orthogonal patterned layers can result in shorts and opens. Consequently, EPE control is critical for yield within any multi-patterning process flow, including litho-etch-litho-etch (LELE), self-aligned double-patterning (SADP) and self-aligned quadruple-patterning (SAQP).

Fig.1: Plan view schematic of 10nm half-pitch vertical lines overlaid with lower horizontal lines, showing the potential for edge-placement error (EPE). (Source: Y. Borodovsky, SPIE)

Happening the day before the official start of SPIE-AL, Nikon’s LithoVision event featured a talk by Intel Fellow and director of lithography hardware solutions Mark Phillips on the big picture of how the industry may continue to pattern smaller IC device features. Regarding the timing of Intel’s planned use of EUV litho technology, Phillips re-iterated that, “It’s highly desirable for the 7nm node, but we’ll only use it when it’s ready. However, EUVL will remain expensive even at full productivity, so 193i and multi-patterning will continue to be used. In particular we’ll need continued improvement in the 193i tools to meet overlay.”

Yuichi Shibazaki— Nikon Fellow and the main architect of the current generation of Nikon steppers—explained that the current generation of 193i steppers, featuring throughputs of >200 wafers per hour, have already been optimized to the point of diminishing returns. “In order to improve a small amount of performance it requires a lot of expense. So just improving tool performance may not decrease chip costs.” Nikon’s latest productivity offering is a converted alignment station as a stand-alone tool, intended to measure every product wafer before lithography to allow for feed-forward tuning of any stepper; cost and cost-of-ownership may be disclosed after the first beta-site tool reaches a customer by the end of this year.

“The 193 immersion technology continues to make steady progress, but there are not as many new game-changing developments,” confided Michael Lercel, Director of Strategic Marketing for ASML in an exclusive interview with SemiMD. “A major theme of several SPIE papers is on EPE, which traditionally we looked at as dependent upon CD and overlay. Now we’re looking at EPE in patterning more holistically, with need to control the complexity with different error-variables. The more information we can get the more we can control.”

At LithoVision this year, John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—discussed the challenges of controlling variability in multi-layer patterning. “A key challenge is predicting and then mitigating total EPE control,” reminded Sturtevant. “We’ve always paid attention to it, but the budgets that are available today are smaller than ever. Edge-placement is very important ” At the leading edge, there are multiple steps within the basic litho flow that induce proximity/local-neighbor effects which must be accounted for in EDA:  mask making, photoresist exposure, post-exposure bake (PEB), pattern development, and CD-SEM inspection (wherein there is non-zero resist shrinkage).

Due to the inherent physics of EUV lithography, as well as the atomic-scale non-uniformities in the reflective mirrors focusing onto the wafer, EUV exposure tools show significant variation in exposure uniformities. “For any given slit position there can be significant differences between tools. In practice we have used a single model of OPC for all slit locations in all scanners in the fab, and that paradigm may have to change,” said Sturtevant. “It’s possible that because the variation across the scanner is as much as the variation across the slit, it could mean we’ll need scanner-specific cross-slit computational lithography.” More than 3nm variation has been seen across 4 EUVL steppers, and the possible need for tool-specific optical proximity correction (OPC) and source-mask optimization (SMO) would be horrible for managing masks in HVM.

Thin Films Extend Patterning Resolution

Applied Materials has led the industry in thin-film depositions and etches for decades, and the company’s production proven processing platforms are being used more and more to extend the resolution of lithography. For SADP and SAQP MP, there are tunable unit-processes established for sidewall-spacer depositions, and chemical downstream etching chambers for mandrel pull with extreme material selectivity. CVD of dielectric and metallic hard-masks when combined with highly anisotropic plasma etching allows for device-specific and mask-specific pattern transfers that can reduce the line width/edge roughness (LWR/LER) originally present in the photoresist. Figure 2 from the SPIE-AL presentation “Impact of Materials Engineering on Edge Placement Error” by Regina Freed, Ying Zhang, and Uday Mitra of Applied Materials, shows LER reduction from 3.4 to 1.3 nm is possible after etch. The company’s Sym3 chamber features very high gas conductance to prevent etch byproducts from dissociation and re-deposition on resist sidewalls.

Fig.2: 3D schematics (top) and plan view SEM images (bottom) showing that control of plasma parameters can tune the byproducts of etch processes to significantly reduce the line-width roughness (LWR) of minimally scaled lines. (Source: Applied Materials)

TEL’s new SAQP spacer-on-spacer process builds on the work shown last year, using oxide as first spacer and TiO2 as second spacer. Now TEL is exploring silicon as the mandrel, then silicon-nitride as the first spacer, and titanium-oxide as second spacer. This new flow can be tuned so that all-dry etch in a single plasma etch chamber can be used for the final mandrel pull and pattern transfer steps.

Coventor’s 3D modeling software allows companies to do process integration experiments in virtual space, allowing for estimation of yield-losses in pattern transfer due to variations in side-wall profiles and LER. A simulation of 9 SRAM cells with 54 transistors shows that photoresist sidewall taper angle determines both the size and the variability of the final fins. The final capacitance of low-k dielectric in dual-damascene copper metal interconnects can be simulated as a function of the initial photoresist profile in a SAQP flow.

—E.K.

3D-NAND Deposition and Etch Integration

Thursday, September 1st, 2016

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By Ed Korczynski, Sr. Technical Editor

3D-NAND chips are in production or pilot-line manufacturing at all major memory manufacturers, and they are expected to rapidly replace most 2D-NAND chips in most applications due to lower costs and greater reliability. Unlike 2D-NAND which was enabled by lithography, 3D-NAND is deposition and etch enabled. “With 3D-NAND you’re talking about 40nm devices, while the most advanced 2D-NAND is running out of steam due to the limited countable number of stored electrons-per-cell, and in terms of the repeatability due to parasitics between adjacent cells,” reminded Harmeet Singh, corporate vice president of Lam Research in an exclusive interview with SemiMD to discuss the company’s presentation at the Flash Memory Summit 2016.

“We’re in an era where deposition and etch uniquely define the customer roadmap,” said Singh,“and we are the leading supplier in 3D-NAND deposition and etch.” Though each NAND manufacturer has different terminology for their unique 3D variant, from a manufacturing process integration perspective they all share similar challenges in the following simplified process sequences:

1)    Deposition of 32-64 pairs of blanket “mold stack” thin-films,

2)    Word-line hole etch through all layers and selective fill of NAND cell materials, and

3)    Formation of “staircase” contacts to each cell layer.

Each of these unique process modules is needed to form the 3D arrays of NVM cells.

For the “mold stack” deposition of blanket alternating layers, it is vital for the blanket PECVD to be defect-free since any defects are mirrored and magnified in upper-layers. All layers must also be stress-free since the stress in each deposited layer accumulates as strain in the underlying silicon wafer, and with over 32 layers the additive strain can easily warp wafers so much that lithographic overlay mismatch induces significant yield loss. Controlled-stress backside thin-film depositions can also be used to balance the stress of front-side films.

Hole Etch

“The difficult etch of the hole, the materials are different so the challenges is different,” commented Singh about the different types of 3D-NAND now being manufactured by leading fabs. “During this conference, one of our customer presented that they do not see the hole diameters shrinking, so at this point it appears to us that shrinking hole diameters will not happen until after the stacking in z-dimension reaches some limit.”

Tri-Layer Resist (TLR) stacks for the hole patterning allow for the amorphous carbon hardmask material to be tuned for maximum etch resistance without having to compromise the resolution of the photo-active layer needed for patterning. Carbon mask is over 3 microns thick and carbon-etching is usually responsive to temperature, so Lam’s latest wafer-chuck for etching features >100 temperature control zones. “This is an example of where Lam is using it’s processes expertise to optimize both the hardmask etch as well as the actual hole etch,” explained Singh.

Staircase Etch

The Figure shows a simplified cross-sectional schematic of how the unique “staircase” wordline contacts are cost-effectively manufactured. The established process of record (POR) for forming the “stairs” uses a single mask exposure of thick KrF photoresist—at 248nm wavelength—to etch 8 sets of stairs controlled by a precise resist trim. The trimming step controls the location of the steps such that they align with the contact mask, and so must be tightly controlled to minimize any misalignment yield loss.

A) Simplified cross-sectional schematic of the staircase etch for 3D-NAND contacts using thick photoresist, B) which allows for controlled resist trimming to expose the next “stair” such that C) successive trimming creates 8-16 steps from a single initial photomask exposure. (Source: Ed Korczynski)

Lam is working on ways to tighten the trimming etch uniformity such that 16 sets of stairs can be repeatably etched from a single KrF mask exposure. Halving the relative rate of vertical etch to lateral etch of the KrF resist allows for the same resist thickness to be used for double the number of etches, saving lithography cost. “We see an amazing future ahead because we are just at the beginning of this technology,” commented Singh.

—E.K.

Learning to live with negative tone

Friday, February 27th, 2015

By Jeff Dorsch, contributing editor

In lithography for manufacturing semiconductors, a negative tone can be a positive attribute.

Negative-tone photoresists can be used in electron-beam, extreme-ultraviolet, and immersion lithography to improve contrast prior to the etching process. Multiple papers and posters on the topic were presented at this week’s SPIE Advanced Lithography Symposium in San Jose, Calif.

Tuesday morning at the conference saw an entire session devoted to “Negative Tone Materials.” Other papers on the subject were scattered throughout technical sessions covering EUV resists.

Negative-tone resists are especially useful in argon fluoride immersion lithography, according to George Bailey of Synopsys. Contrast loss can result in rounding off of features, and negative-tone resist can aid in keeping features sharp through etch, he noted.

“The technology has been around for a long time,” said Tom Ferry of Synopsys. “First there was negative resist, then positive resist.”

Solid State Watch: June 13-19, 2014

Friday, June 20th, 2014
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Research Alert: May 13, 2014

Tuesday, May 13th, 2014

SRC and UC Berkeley pursue a more cost effective approach to 3D integration

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

The research focuses on integrating extra layers of transistors on a vertically integrated 3D monolithic chip using printing of semiconductor “inks” as compared to the current method of chip-stacking through 3D interconnect solutions.

The new process technology could help semiconductor manufacturers develop smaller and more versatile components that are less expensive and higher performing by enabling cost-effective integration of additional capabilities such as processing, memory, sensing and display. The low-temperature process is also compatible with polymer substrates, enabling potential new applications in wearable electronics and packaging.

To fabricate such devices, new material and process methodologies are needed for depositing nanoparticles for semiconductors, dielectrics and conductors. The research is particularly focused on solution-based processing due its low temperature compatibility with CMOS metallization as well as the potential for lower cost manufacturing.

“Initial results from the Berkeley team show that reasonably high performance can be obtained from ink-jet printed devices with process temperatures that are compatible with post-CMOS metallization, thus enabling a new route to monolithic 3D integration,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

SEMATECH reports higher dose sensitivity progress in novel photoresist platforms

SEMATECH announced today that researchers have reported progress which could significantly improve resist sensitivity by incorporating metal oxide nanoparticles for extreme ultraviolet (EUV) lithography, bringing the technology another step toward enabling the development of high performance resists required to enable EUV for high-volume manufacturing (HVM).

SEMATECH engineers, in association with scientists from Cornell University, have demonstrated significantly higher dose sensitivity by incorporating metal oxide nanoparticles, with a resolution dose that is less than one fifth of that normally used with EUV scanner throughput calculations. These significant advances are critical in moving forward the infrastructure that will prepare EUV lithography for HVM at 20nm half-pitch.

“These resist platforms have the potential to significantly relax the EUV source power requirements to enable high-throughput EUV lithography—which has been the most critical barrier to enabling EUV to enter high-volume manufacturing,” said Michael Lercel, SEMATECH’s senior director of Technology. “With these disruptive photoresist platforms, SEMATECH is working toward enabling breakthrough high performance resists that move forward the infrastructure that will prepare EUV for cost-effective manufacturing.”

Taking the lead out of a promising solar cell

Northwestern University researchers are the first to develop a new solar cell with good efficiency that uses tin instead of lead perovskite as the harvester of light. The low-cost, environmentally friendly solar cell can be made easily using “bench” chemistry — no fancy equipment or hazardous materials.

“This is a breakthrough in taking the lead out of a very promising type of solar cell, called a perovskite,” said Mercouri G. Kanatzidis, an inorganic chemist with expertise in dealing with tin. “Tin is a very viable material, and we have shown the material does work as an efficient solar cell.”

Kanatzidis, who led the research, is the Charles E. and Emma H. Morrison Professor of Chemistry in the Weinberg College of Arts and Sciences.

The new solar cell uses a structure called a perovskite but with tin instead of lead as the light-absorbing material. Lead perovskite has achieved 15 percent efficiency, and tin perovskite should be able to match — and possibly surpass — that. Perovskite solar cells are being touted as the “next big thing in photovoltaics” and have reenergized the field.

Kanatzidis developed, synthesized and analyzed the material. He then turned to Northwestern collaborator and nanoscientist Robert P. H. Chang to help him engineer a solar cell that worked well.

“Our tin-based perovskite layer acts as an efficient sunlight absorber that is sandwiched between two electric charge transport layers for conducting electricity to the outside world,” said Chang, a professor of materials science and engineering at the McCormick School of Engineering and Applied Science.

Their solid-state tin solar cell has an efficiency of just below 6 percent, which is a very good starting point, Kanatzidis said. Two things make the material special: it can absorb most of the visible light spectrum, and the perovskite salt can be dissolved, and it will reform upon solvent removal without heating.

“Other scientists will see what we have done and improve on our methods,” Kanatzidis said. “There is no reason this new material can’t reach an efficiency better than 15 percent, which is what the lead perovskite solar cell offers. Tin and lead are in the same group in the periodic table, so we expect similar results.”

Perovskite solar cells have only been around — and only in the lab — since 2008. In 2012, Kanatzidis and Chang reported the new tin perovskite solar cell with promises of higher efficiency and lower fabrication costs while being environmentally safe.

“Solar energy is free and is the only energy that is sustainable forever,” Kanatzidis said. “If we know how to harvest this energy in an efficient way we can raise our standard of living and help preserve the environment.”

The solid-state tin solar cell is a sandwich of five layers, with each layer contributing something important. Being inorganic chemists, Kanatzidis and his postdoctoral fellows Feng Hao and Constantinos Stoumpos knew how to handle troublesome tin, specifically methylammonium tin iodide, which oxidizes when in contact with air.

The first layer is electrically conducting glass, which allows sunlight to enter the cell. Titanium dioxide is the next layer, deposited onto the glass. Together the two act as the electric front contact of the solar cell.

Next, the tin perovskite — the light absorbing layer — is deposited. This is done in a nitrogen glove box — the bench chemistry is done in this protected environment to avoid oxidation.

On top of that is the hole transport layer, which is essential to close the electrical circuit and obtain a functional cell. This required Kanatzidis and his colleagues to find the right chemicals so as not to destroy the tin underneath. They determined what the best chemicals were — a substituted pyridine molecule — by understanding the reactivity of the perovskite structure. This layer also is deposited in the glove box. The solar cell is then sealed and can be taken out into the air.

A thin layer of gold caps off the solar-cell sandwich. This layer is the back contact electrode of the solar cell. The entire device, with all five layers, is about one to two microns thick.

The researchers then tested the device under simulated full sunlight and recorded a power conversion efficiency of 5.73 percent.

The Week In Review: Sept. 30

Monday, September 30th, 2013

Applied Materials Inc. and Tokyo Electron Limited this week announced Applied Materials agreed to merge with Tokyo Electron in a deal valuing the Japanese semiconductor production equipment maker at $9.3 billion, creating a giant in the chip and display manufacturing-tools sector.

Micron Technology, Inc. announced that it is shipping 2GB Hybrid Memory Cube (HMC) engineering samples. Micron expects future generations of HMC to migrate to consumer applications within three to five years.

The Fraunhofer Institute for Solar Energy Systems ISE, Soitec, CEA-Leti and the Helmholtz Center Berlin jointly announced this week having achieved a new world record for the conversion of sunlight into electricity using a new solar cell structure with four solar subcells.

Fujifilm and imec have developed a new photoresist technology for organic semiconductors that enables the realization of submicron patterns.

Mentor Graphics announced the latest release of its a FloEFD concurrent computational fluid dynamics (CFD) product.