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Posts Tagged ‘photonics’

Silicon Photonics Technology Developments

Thursday, April 6th, 2017

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By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.

—E.K.

Photonics in Silicon R&D Toward Tb/s

Tuesday, January 3rd, 2017

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By Ed Korczynski, Sr. Technical Editor

The client:server computing paradigm colloquially referred to as the “Cloud” results in a need for extremely efficient Cloud server hardware, and from first principles the world can save a lot of energy resources if servers run on photonics instead of electronics. Though the potential for cost-savings is well known, the challenge of developing cost-effective integrated photonics solutions remains. Today, discrete compound-semiconductor chips function as transmitters, multiplexers (MUX), and receivers of photons, while many global organizations pursue the vision of lower-cost integrated silicon (Si) photonics circuits.

Work on photonics chips—using light as logic elements in an integrated circuit—built in silicon (Si) has accelerated recently with announcements of new collaborative research and development (R&D) projects. Leti, an institute of CEA Tech, announced the launch of a European Commission Horizon 2020 “COSMICC” project to enable mass commercialization of Si-photonics-based transceivers to meet future data-transmission requirements in data centers and super computing systems.

The Leti-coordinated COSMICC project will combine CMOS electronics and Si-photonics with innovative fiber-attachment techniques to achieve 1 Tb/s data rates. These scalable solutions will provide performance improvement an order of magnitude better than current VCSELs transceivers, and the COSMICC-developed technology will address future data-transmission needs with a target cost per bit that traditional wavelength-division multiplexing (WDM) transceivers cannot meet. The project’s 11 partners from five countries are focusing on developing mid-board optical transceivers with data rates up to 2.4 Tb/s with 200 Gb/s per fiber using 12 fibers. The devices will consume less than 2 pJ/bit. and cost approximately 0.2 Euros/Gb/s.

Figure 1: Schematic of COSMICC on-board optical transceiver at 2.4 Tb/s using 50 Gbps/wavelength, 4 CWDM wavelengths per fiber, 12 fibers for transmission and 12 fibers for reception. (Source: Leti)

A first improvement will be the introduction of a silicon-nitride (SiN) layer that will allow development of temperature-insensitive MUX/DEMUX devices for coarse WDM operation, and will serve as an intermediate wave-guiding layer for optical input/output. The partners will also evaluate capacitive modulators, slow-wave depletion modulators with 1D periodicity, and more advanced approaches. These include GeSi electro-absorption modulators with tunable Si composition and photonic crystal electro-refraction modulators to make micrometer-scale devices. In addition, a hybrid III-V on Si laser will be integrated in the SOI/SiN platform in the more advanced transmitter circuits.

Meanwhile in the United States, Coventor, Inc. is collaborating with the Massachusetts Institute of Technology (MIT) on photonics modeling. MIT is a key player in the AIM Photonics program, a federally funded, public-private partnership established to advance domestic capabilities in integrated photonic technology and strengthen high-tech U.S.-based manufacturing. Coventor will provide its SEMulator3D process modeling platform to model the effect of process variation in the development of photonic integrated components.

“Coventor’s technical expertise in predicting the manufacturability of advanced technologies is outstanding. Our joint collaboration with Coventor will help us develop new design methods for achieving high yield and high performance in integrated photonic applications,” said Professor Duane Boning of MIT. Boning is an expert at modeling non-linear effects in processing, many years after working on the semiconductor industry’s reference model for the control of chemical-mechanical planarization (CMP) processing.

—E.K.

Silicon as Disruptive Platform for IoT Applications

Monday, August 29th, 2016

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By Ed Korczynski, Sr. Technical Editor

Marie Semeria, chief executive officer of CEA-Leti (http://www.leti.fr/en), sat down with SemiMD during SEMICON West to discuss how the French R&D and pilot manufacturing campus—located at the foot of the beautiful French alps near Grenoble—is expanding the scope of it’s activities to develop systems solutions for the Internet-of-Things (IoT). Part-1 on hardware/software co-development was published last month.

Korczynski: Regarding ‘IoT’ applications, we expect that chips must be very low cost to be successful, and at the same time the ultimately winning solutions will be those that combine the best functionalities from different technology spaces each in a ‘sweet spot’ of cost to performance. It seems that being able to do it on SOI wafers could produce the right volumes.

Semeria: Yes. It could be enough.

Korczynski: Do you have any feel in advance for how much area of silicon is needed? Some small ADC, an 8-bit micro-controller, and RF components may be done in different processes and then integrated. Is it possible that the total area of silicon needed could be less than a square millimeter?

Semeria: Yes.

Korczynski: Well, if they are that small then we have to remember how many units we’d get from just a single wafer, and there are 24 wafers in a batch…

Semeria: One batch can be enough for one market, depending upon the application.

Korczynski: If this is the case, then even though the concept of purely-additive roll-to-roll processes are attractive, oddly they may be too efficient and produce more units than the world can absorb. If we can do all that we need to do with established silicon wafer fab technology creating ICs smaller than a square millimeter then it will be very cost-effective.

Semeria: Leti’s strategy is to keep the performance of solid-state devices, so not to go to organic electronics. Use silicon as the differentiator to lower the cost, add more functions, and then miniaturize all that can be miniaturized. In this way we are achieving integration of MEMS with small electronics in arrays as small as one millimeter square. When you deal with such small die you can put them inside of flexible materials, inside of a t-shirt and it’s no problem. So that’s our strategy to keep small silicon and put it in clothes, in shoes, in windows, in glasses, and all sorts of flexible materials. When you are thinning substrates for bonding, then the thinned silicon is very flexible.

Korczynski: In 1999 I worked for one of the first companies selling through-silicon via technology, and it was all about backside thinning so I’ve played with flexible wafers.

Semeria: So you know what I mean.

Korczynski: Around 50 microns and below as long as you etch away any grinding defects from the backside it is very strong and very flexible (Fig. 1). At 50 microns the chip is still thick enough to be easily picked-and-placed, but it’s flexible. Below 10 microns the wafer is difficult to handle.

FIGURE 1: 50 micron thin silicon wafers can be strong and very flexible. (Source: Virginia Semiconductor)

Semeria: To maintain the advantage of cost for different applications spaces, we are developing the ‘chiplet’ approach which means a network of chips. It starts with a digital platform, then you add an active interposer to connect different dice. For example you could have 28nm-node on the bottom and a 14nm-node chip on top for some specific function. Then you can put embedded memory and RF connected through the interposer, and it’s the approach that we promote for the first generation of multi-functional integration on digital. Very flexible, cost-effective.

Korczynski: This is using some sort of bus to move information?

Semeria: Yes, this will be an electronic bus for the first generation, as we recently announced. Then a photonics interposer could be used for higher-speed data rate in a future generation. We have a full roadmap with different types of integration schemes. So it’s a way to combine all with silicon. Everything is intended to be integrated into existing 300mm silicon facilities. Some weeks ago we presented the first results showing silicon quantum bits built on 300mm substrates, and fully compatible with CMOS processing. So it’s the way we are going, taking a very disruptive approach using the foundation of proven 300mm silicon processing.

Korczynski: Interesting.

Semeria: For example, regarding driving assistance applications we have to consider fusion integration of different sensors, and complete coverage of the environment with low power-consumption. For computing capacity we developed a completely disruptive approach, very different from Intel and very different from nVidia which use consumer products as the basis for automotive application products. Specifically for automotive we developed a new probabilistic methodology to avoid all of the calculations based on floating-point. In this way we can divide the computing needs of the device by 100, so it’s another example of developing just the right device for the right application adapted for the right environment. So the approach is very different in development for IoT instead of mainstream CMOS.

Korczynski: For automotive there’s such a requirement for reliability, with billions of dollars at stake in product recalls and potential lawsuits, the auto industry is very risk-averse for very good reasons. So historically they’ve always used trailing-edge nodes, and if you want to supply to them you have to commit to 10 or maybe 20 years of manufacturing, and yet we still want to add in advance functionalities. The impression I’ve gotten is that the 28nm FD-SOI platform is fairly ideal here.

Semeria: FD-SOI is very reliable and very efficient. That’s why when we showed our demonstrator at the recent DAC it’s based on the STMicroelectronics micro-controller. It’s very reliable and adaptable for automotive applications.

Korczynski: Is it at 28nm?

Semeria: No, about 40nm now. The latest generation is not needed, because we changed the algorithms so we didn’t need so much capacity in computing. In IoT there is space to use 40nm or 32nm down to 28nm. It’s a great space to use ‘old technologies’ and optimize them with the right algorithms, the right signal-processing, and the right security. So it’s very exciting for Leti because we have all of the key competencies to be able to handle the IoT challenge, and there is a great ability to make various integration schemes depending upon the application. There is a very large space to demonstrate, and to develop new materials.

Korczynski: Does this relate to some recent work I’ve seen from Leti with micro-cantilevers?

Semeria: Yes, this is the work we are doing with CalTech on micro-resonators (Fig. 2).

FIGURE 2: MEMS/NEMS silicon cantilever resonator capable of detecting individual adhered molecules, for integration with digital CMOS in a complete IoT sensing system. (Source: Leti)

Korczynski: Thank you very much for taking the time to discuss these important trends.

Semeria: It is a pleasure.

—E.K.

CMOS-Photonics Technology Challenges

Friday, July 8th, 2016

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By Ed Korczynski, Sr. Technical Editor

Fig 1

While it is very easy to talk about the potential advantages of CMOS-photonic integration, the design and manufacturing of commercially competitive products has been extraordinarily difficult. It has been well-known that the cost efficiencies of silicon wafers and CMOS fab processes could theoretically be leveraged to create low-cost photonic circuitry. However, the physics of optics is quite different from the physics of electronics, and so there have been unexpected challenges in moving R&D experiments to HVM products. During the Imec Technology Forum in Brussels held this May, Joris Van Campenhout, imec program director for Optical I/O (Fig. 1) sat down with Solid State Technology to discuss recent progress and future plans.

Data centers—also known as “The Cloud”—continue to grow along with associated power-consumptions, so there are strong motivations to find cost-effective ways to replace more of the electrical switches with lower-power optical circuits. Optical connections in modern data centers do not all have the same specifications, with a clear hierarchy based on the 3D grid-like layout of rows of rack-mounted Printed Circuit Boards (PCB). The table shows the basic differences in physical scale and switching speeds required at different levels within the hierarchy.

Data centers—also known as “The Cloud”—continue to grow along with associated power-consumptions, so there are strong motivations to find cost-effective ways to replace more of the electrical switches with lower-power optical circuits. Optical connections in modern data centers do not all have the same specifications, with a clear hierarchy based on the 3D grid-like layout of rows of rack-mounted Printed Circuit Boards (PCB). The table shows the basic differences in physical scale and switching speeds required at different levels within the hierarchy.

ESTIMATED DATA CENTER REQUIREMENTS FOR OPTICAL I/O  (Source: imec)
OPTICAL CONNECTION RACK BACKPLANE PCB CHIP
DISTANCE 5-500m 0.5-3m 5-50cm 1-50mm
RELATIVE COST $$$$ $$$ $$ $
POWER/Gbps 5mW 1mW 0.5mW 0.1mW

Rack fiberoptic lines connecting the rows of rack-mounted printed-circuit boards (PCB) in data centers represent a major portion of the total investments for capital equipment, so there is a roadmap to keep the same fibers in place while upgrading the speeds of photonic transmit and receive components over time:

40GHz was standard through 2015,

100GHz upgrades in 2016,

400GHz planned by 2019, and

1THz estimated by 2022.

Some companies have tried to develop multi-mode fiber solutions, but imec is working on single-mode. The telecommunications standard for single-mode optical fiber diameter is 9 microns, while multimode today can be up to 50 microns diameter. “Fundamentally single-mode will be the most integrate-able way to try to get that fiber on to a chip,” explained Van Campenhout. “It is difficult enough to get nine micron diameter fibers to couple to sub-micron waveguides on chip.”

Backplane is the PCB-to-PCB connection within one rack, that today uses copper connections running at up to 50 GHz. Imec sees backplane applications as a possible insertion point for CMOS-Photonics, because there are approximately 10X the number of connections compared to rack applications and because the relative cost target calls for new technologies. Imec’s approach uses 56G silicon ring-modulators to shift wavelengths by 0.1% at very low power, knowingly taking on control issues with non-linearity, and high temperature sensitivity. “We’re confident that it can be done,” stated Van Campenhout, “but the question remains if the overhead can be reduced so that the costs are competitive.” The overhead includes the possible need for on-chip thin-film heaters/coolers to be able to control the temperature.

PCB level connections are being pushed by the Consortium for On-Board Optics (COBO), an industry group working to develop a series of specifications to permit the use of board-mounted optical modules in the manufacturing of networked equipment (i.e. switches, servers, etc.). The organization plans to reference industry specifications where possible and develop specifications where required with attention to electrical interfaces, pin-outs, connectors, thermals, etc. for the development of interchangeable and interoperable optical modules that can be mounted onto motherboards and daughtercards.

Luxtera is the commercial market leader for CMOS-Photonic chips used at the Rack level today, and uses ‘active alignment’ meaning that the fiber has to be lit with the laser and then aligning to the waveguides during test and during assembly. Luxtera is fabless and uses Freescale as foundry to build the chip in an established CMOS SOI process flow originally established for high performance microprocessors. The company produces 10G chips today for advanced Ethernet connections, and through a partnership with Molex ships 40G Active Optical Cables.

Chip level optical connections require breakthrough technologies such as indium-phosphide epitaxy on silicon to be able to grow the most efficient electrically-controlled optical switches, instead of having to pick-and-place discrete components aligned with waveguides. Alignment of components is a huge issue for manufacturing and test that adds inherent costs. “The main issue is getting the coupling from the chip to the fiber with low losses, since sub-micron alignment is needed to avoid a 1 dB loss,” summarized Van Campenhout.

Figure 2 shows a simplified functional schematic of a high-capacity optical communications links employing Dense Wavelength Division Multiplexing (DWDM) to combine modulated laser beams of different colors on a single-mode fiber. Luxtera is working on DWDM for increased bandwidth as is imec.

FIGURE 2: Dense Wavelength Division Multiplexing (DWDM) scheme allows multiplication of the total single-mode fiber (SMF) bandwidth by the number of laser colors used. (Source: imec)

Difficult Design

“If you have just a 1 nm variation in the waveguide width, that device’s spectral response will be proportional as a rule of thumb,” explained Van Campenhout. “We can tune for that with a heating element, but then we lose the low-power advantage.” This results in a need for different design-for-manufacturing approaches.

“When we do photonics design we have to have round features or the light will scatter. So when we do mask making we have to use different rules, and we need to educate all of our partners that we are doing photonics,” reminded Van Campenhout. “However there are EDA companies that are becoming aware of these aspect, so things are developing nicely to create a whole ecosystem to be able to build these. We have the first version of a PDK that we use for multi-product-wafer runs, so we can deliver custom chips to partners.”

Mentor Graphics is an imec partner, and the company’s Tom Daspit, marketing manager for Pyxis Design Tools, spoke with Solid State Technology about the special challenges of EDA for photonics. “You’ve now jumped off the cliff of the orthogonal design environment. Light doesn’t bend at 45° let alone 90°. On an IC it’s all orthogonal, while if it’s photonic we have to modify the interconnect so that the final design is a nice curved one.” To produce a smooth curve the EDA tools must fracture it into a small grid for the photomask, so a seemingly simple set of curves can require gigabytes in a final GDSII file.

It was about 4 years ago that some customers began asking Mentor to modify tools to be able to support photonics, and today there are customers large and small, and some are in full volume production for communications applications. “Remember when they building the old Cray supercomputers and they had to account for all wire lengths to handle signal delays, well now with photonics we need to account for waveguide lengths,” commented Daspit.

In full volume products today are likely communications chips. Customers do not typically share product plans, so not sure of applications spaces. Everybody wants to get rid of the Cu in the backpane to eliminate power consumption, but:

“The big application is photonics for sensor integration, with universities leading the way. Medical is a huge new market,” explained Daspit. “The CMOS die could be 130- down to 65nm or maybe 28nm-nm for some digital.” So there are a wide variety of future applications for CMOS-Photonics, and despite the known manufacturing challenges there are already commercial applications in communications.

—E.K.

Technologies for Advanced Systems Shown at IMEC Tech Forum USA

Tuesday, July 14th, 2015

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By Ed Korczynski, Sr. Technical Editor

Luc Van den hove, president and CEO, imec opened the Imec Technology Forum – USA in San Francisco on July 13 by reminding us of the grand vision and motivation behind the work of our industry to empower individuals with micro- and nano-technologies in his talk, “From the happy few to the happy many.” While the imec consortium continues to lead the world in pure materials engineering and device exploration, they now work on systems-integration complexities with over 100 applications partners from agriculture, energy, healthcare, and transportation industries.

We are now living in an era where new chip technologies require trade-offs between power, performance, and bandwidth, and such trade-offs must be carefully explored for different applications spaces such as cloud clusters or sensor nodes. An Steegen, senior vice president process technology, imec, discussed the details of new CMOS chip extensions as well as post-CMOS device possibilities for different applications spaces in her presentation on “Technology innovation: an IoT era.” EUV lithography technology continues to be developed, targeting a single-exposure using 0.33 Numerical Aperture (NA) reflective lenses to pattern features as small as 18nm half-pitch, which would meet the Metal1 density specifications for the industry’s so-called “7nm node.” Patterning below 12nm half-pitch would seem to need higher-NA which is not an automatic extension of current EUV technology.

So while there is now some clarity regarding the pre-competitive process-technologies that will be needed to fabricate next-generation device, there is less clarity regarding which new device structures will best serve the needs of different electronics applications. CMOS finFETs using strained silicon-doped-with-Germanium Si(Ge) will eventually be replaced by gate-all-around (GAA) nano-wires (NW) using alternate-channel materials (ACM) with higher mobilities such as Ge and indium-gallium-arsenide (InGaAs). While many measures of CMOS performance improve with scaling to smaller dimensions, eventually leakage current and parasitic capacitances will impede further progress.

Figure 1 shows a summary of energy-vs.-delay analyses by imec for all manner of devices which could be used as switches in logic arrays. Spin-wave devices such as spin-transfer-torque RAM (STT-RAM) can run at low power consumption but are inherently slower than CMOS devices. Tunnel-FET (TFET) devices can be as fast or faster than CMOS while running at lower operating power due to reduced electrostatics, leading to promising R&D work.

Fig.1: Energy vs. delay for various logic switches. (Source: imec)

In an exclusive interview, Steegen explained how the consortium balances the needs of all partners in R&D, “When you try to predict future roadmaps you prefer to start from the mainstream. Trying to find the mainstream, so that customers can build derivatives from that, is what imec does. We’re getting closer to systems, and systems are reaching down to technology,” said Steegen. “We reach out to each other, while we continue to be experts in our own domains. If I’m inserting future memory into servers, the system architecture needs to change so we need to talk to the systems people. It’s a natural trend that has evolved.”

Network effects from “the cloud” and from future smart IoT nets require high-bandwidth and so improved electrical and optical connections at multiple levels are being explored at imec. Joris Van Campenhout, program director optical I/O, imec, discussed “Scaling the cloud using silicon photonics.” The challenge is how to build a 100Gb/s bandwidth in the near term, and then scale to 400G and then 1.6T though parallelism of wavelength division multiplexing; the best results to date for a transmitter and receiver reach 50Gb/s. By leveraging the existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Supported by EDA tools including those from Mentor Graphics, there have been 7 tape-outs of devices in the last year using a Process Design Kit (PDK). When combined with laser sources and a 40nm node foundry CMOS chip, a complete integrated solution exists. Arrays of 50Gb/s structures can allow for 400Gb/s solutions by next year, and optical backplanes for server farms in another few years. However, to bring photonics closer to the chip in an optical interposer will require radical new new approaches to reduce costs, including integration of more efficient laser arrays.

Alexander Mityashin, project manager thin film electronics, imec, explained why we need, “thin film electronics for smart applications.” There are billions of items in our world that could be made smarter with electronics, provided we can use additive thin-film processes to make ultra-low-cost thin-film transistors (TFT) that fit different market demands. Using amorphous indium-gallium-zinc-oxide (a-IGZO) deposited at low-temperature as the active layer on a plastic substrate, imec has been able to produce >10k TFTs/cm2 using just 4-5 lithography masks. Figure 2 shows these TFT integrated into a near-field communications (NFC) chip as first disclosed at ISSCC earlier this year in the paper, “IGZO thin-film transistor based flexible NFC tags powered by commercial USB reader device at 13.56MHz.” Working with Panasonic in 2013, imec showed a flexible organic light-emitting diode (OLED) display of just 0.15mm thickness that can be processed at 180°C. In collaboration with the Holst Center, they have worked on disposable flexible sensors that can adhere to human skin.

Fig.2: Thin-Film Transistors (TFT) fabricated on plastic using Flat Panel Display (FPD) manufacturing tools. (Source: imec/Holst Center)

Jim O’Neill, Chief Technology Officer of Entegris, expanded on the systems-level theme of the forum in his presentation on “Putting the pieces together – Materials innovation in a disruptive environment.” With so many additional materials being integrated into new device structures, there are inherently new yield-limiting defect mechanisms that will have to be controlled. With demand for chips now being driven primarily by high-volume consumer applications, the time between first commercial sample and HVM has compressed such that greater coordination is needed between device, equipment, and materials companies. For example, instead of developing a wet chemical formulation on a tool and then optimizing it with the right filter or dispense technology, the Process Engineer can start envisioning a “bottle-to-nozzle wetted surface solution.” By considering not just the intended reactions on the wafer but the unintended reactions that can occur up-steam and down-stream of the process chamber, full solutions to the semiconductor industry’s most challenging yield problems can be more quickly found.

—E.K.

Research Alert: February 17, 2015

Thursday, February 19th, 2015

A new spin on spintronics

A team of researchers from the University of Michigan and Western Michigan University is exploring new materials that could yield higher computational speeds and lower power consumption, even in harsh environments.

Most modern electronic circuitry relies on controlling electronic charge within a circuit, but this control can easily be disrupted in the presence of radiation, interrupting information processing. Electronics that use spin-based logic, or spintronics, may offer an alternative that is robust even in radiation-filled environments.

Making a radiation-resistant spintronic device requires a material relevant for spintronic applications that can maintain its spin-dependence after it has been irradiated. In a paper published in the journal Applied Physics Letters, from AIP Publishing, the Michigan research team presents their results using bulk Si-doped n-GaAs exposed to proton radiation.

How Does Spintronics Work?

Modern electronic devices use charges to transmit and store information, primarily based upon how many electrons are in one place or another. When a lot of them are at a given terminal, you can call that ‘on.’ If you have very few of them at the same terminal, you can call that ‘off,’ just like a light switch. This allows for binary logic depending on whether the terminal is ‘on’ or ‘off.’ Spintronics, at its simplest, uses the ‘on/off’ idea, but instead of counting the electrons, their spin is measured.

“You can think of the spin of an electron as a tiny bar magnet with an arrow painted on it. If the arrow points up, we call that ‘spin-up.’ If it points down, we call that ‘spin-down.’ By using light, electric, or magnetic fields, we can manipulate, and measure, the spin direction,” said researcher Brennan Pursley, who is the first author of the new study.

While spintronics holds promise for faster and more efficient computation, researchers also want to know whether it would be useful in harsh environments. Currently, radioactivity is a major problem for electronic circuitry because it can scramble information and in the long term degrade electronic properties. For the short term effects, spintronics should be superior: radioactivity can change the quantity of charge in a circuit, but should not affect spin-polarized carriers.

Studying spintronic materials required that the research team combine two well established fields: the study of spin dynamics and the study of radiation damage. Both tool sets are quite robust and have been around for decades but combining the two required sifting through the wealth of radiation damage research. “That was the most difficult aspect,” explains Pursley. “It was an entirely new field for us with a variety of established techniques and terminology to learn. The key was to tackle it like any new project: ask a lot of questions, find a few good books or papers, and follow the citations.”

Technically, what the Michigan team did was to measure the spin properties of n-GaAs as a function of radiation fluence using time-resolved Kerr rotation and photoluminescence spectroscopy. Results show that the spin lifetime and g-factor of bulk n-GaAs is largely unaffected by proton irradiation making it a candidate for further study for radiation-resistant spintronic devices. The team plans to study other spintronic materials and prototype devices after irradiation since the hybrid field of irradiated spintronics is wide open with plenty of questions to tackle.

Long term, knowledge of radiation effects on spintronic devices will aid in their engineering. A practical implementation would be processing on a communications satellite where without the protection of Earth’s atmosphere, electronics can be damaged by harsh solar radiation. The theoretically achievable computation speeds and low power consumption could be combined with compact designs and relatively light shielding. This could make communications systems faster, longer-lived and cheaper to implement.

Novel solid-state nanomaterial platform enables terahertz photonics

Compact, sensitive and fast nanodetectors are considered to be somewhat of a “Holy Grail” sought by many researchers around the world. And now a team of scientists in Italy and France has been inspired by nanomaterials and has created a novel solid-state technology platform that opens the door to the use of terahertz (THz) photonics in a wide range of applications.

During the past decade, materials research has played an essential role in filling the THz gap, beginning with the development of THz quantum cascade lasers, which rely heavily on semiconductor heterostructured artificial nanomaterials. The development of THz spectroscopy, nanospectroscopy and THz imaging expanded the range of powerful tools for the characterization of a broad range of materials — including one-dimensional or two-dimensional semiconductors, biomolecules and graphene.

The missing piece? A complementary detection technology capable of fulfilling THz application-oriented needs in fields such as biomedical diagnostics, security, cultural heritage, quality and process controls, and high data-rate wireless communications that require ad hoc integrated generation and detection systems.

As the scientists report in the journal APL Materials, from AIP publishing, by using an approach that exploits the excitation of plasma waves in the channel of field-effect transistors (FET), they were able to create the first FET detectors based on semiconductor nanowires, designed in a plethora of architectures — including tapers, heterostructures and metamaterial-antenna coupled. While they were at it, they also developed the first THz detectors made of mono- or bi-layer graphene.

“Our work shows that nanowire FET technology is versatile enough to enable ‘design’ via lithography of the detector’s parameters and its main functionalities,” explained Miriam Serena Vitiello, lead author of the paper as well as research scientist and group leader of Terahertz Photonics Group in the Nanoscience Institute at CNR and Scuola Normale Superiore in Pisa, Italy.

What’s the nanowire detector capable of? It offers “a concrete perspective of application-oriented use, since it operates at room temperature — reaching detection frequencies greater than 3 THz, with maximum modulation speed in the MHz range, and noise equivalent powers that are already competitive with the best commercially available technologies,” Vitiello said.

In terms of applications, because the nanodetectors can be tapped for large-area fast imaging across both the THz and the sub-terahertz spectral ranges, don’t be surprised to see them commercialized in the near future for a variety of spectroscopic and real-time imaging applications — possibly even in the form of fast multi-pixel THz cameras.

Next, the scientists’ goals are to “push the device’s performance in the ultrafast detection realm, explore the feasibility of single photon detection by using novel architectures and material choices, develop compact focal plane arrays, and to integrate on-chip the nanowire detectors with THz quantum cascade microlasers,” noted Vitiello. “This will allow us to take THz photonics to a whole new level of ‘compactness’ and versatility, where it can finally begin to address many killer applications.”

Novel crumpling method takes flat graphene from 2-D to 3-D

Researchers at the University of Illinois at Urbana-Champaign have developed a unique single-step process to achieve three-dimensional (3D) texturing of graphene and graphite. Using a commercially available thermally activated shape-memory polymer substrate, this 3D texturing, or “crumpling,” allows for increased surface area and opens the doors to expanded capabilities for electronics and biomaterials.

“Fundamentally, intrinsic strains on crumpled graphene could allow modulation of electrical and optical properties of graphene,” explained SungWoo Nam, an assistant professor of mechanical science and engineering at Illinois. “We believe that the crumpled graphene surfaces can be used as higher surface area electrodes for battery and supercapacitor applications. As a coating layer, 3D textured/crumpled nano-topographies could allow omniphobic/anti-bacterial surfaces for advanced coating applications.”

Graphene–a single atomic layer of sp2-bonded carbon atoms–has been a material of intensive research and interest over recent years. A combination of exceptional mechanical properties, high carrier mobility, thermal conductivity, and chemical inertness, make graphene a prime candidate material for next generation optoelectronic, electromechanical, and biomedical applications.

“In this study, we developed a novel method for controlled crumpling of graphene and graphite via heat-induced contractile deformation of the underlying substrate,” explained Michael Cai Wang, a graduate student and first author of the paper, “Heterogeneous, Three-Dimensional Texturing of Graphene,” which appeared in the journal Nano Letters. “While graphene intrinsically exhibits tiny ripples in ambient conditions, we created large and tunable crumpled textures in a tailored and scalable fashion.”

“As a simpler, more scalable, and spatially selective method, this texturing of graphene and graphite exploits the thermally induced transformation of shape-memory thermoplastics, which has been previously applied to microfluidic device fabrication, metallic film patterning, nanowire assembly, and robotic self-assembly applications,” added Nam, whose group has filed a patent for their novel strategy. “The thermoplastic nature of the polymeric substrate also allows for the crumpled graphene morphology to be arbitrarily re-flattened at the same elevated temperature for the crumpling process.”

“Due to the extremely low cost and ease of processing of our approach, we believe that this will be a new way to manufacture nanoscale topographies for graphene and many other 2D and thin-film materials.”

The researchers are also investigating the textured graphene surfaces for 3D sensor applications.

“Enhanced surface area will allow even more sensitive and intimate interactions with biological systems, leading to high sensitivity devices,” Nam said.

Research Alert: August 27, 2014

Wednesday, August 27th, 2014

Scientists craft a semiconductor only three atoms thick

Scientists have developed what they believe is the thinnest-possible semiconductor, a new class of nanoscale materials made in sheets only three atoms thick.

As seen under an optical microscope, the heterostructures have a triangular shape. The two different monolayer semiconductors can be recognized through their different colors.

The University of Washington researchers have demonstrated that two of these single-layer semiconductor materials can be connected in an atomically seamless fashion known as a heterojunction. This result could be the basis for next-generation flexible and transparent computing, better light-emitting diodes, or LEDs, and solar technologies.

“Heterojunctions are fundamental elements of electronic and photonic devices,” said senior author Xiaodong Xu, a UW assistant professor of materials science and engineering and of physics. “Our experimental demonstration of such junctions between two-dimensional materials should enable new kinds of transistors, LEDs, nanolasers, and solar cells to be developed for highly integrated electronic and optical circuits within a single atomic plane.”

The research was published online this week in Nature Materials.

The researchers discovered that two flat semiconductor materials can be connected edge-to-edge with crystalline perfection. They worked with two single-layer, or monolayer, materials – molybdenum diselenide and tungsten diselenide – that have very similar structures, which was key to creating the composite two-dimensional semiconductor.

Collaborators from the electron microscopy center at the University of Warwick in England found that all the atoms in both materials formed a single honeycomb lattice structure, without any distortions or discontinuities. This provides the strongest possible link between two single-layer materials, necessary for flexible devices. Within the same family of materials it is feasible that researchers could bond other pairs together in the same way.

The researchers created the junctions in a small furnace at the UW. First, they inserted a powder mixture of the two materials into a chamber heated to 900 degrees Celsius (1,652 F). Hydrogen gas was then passed through the chamber and the evaporated atoms from one of the materials were carried toward a cooler region of the tube and deposited as single-layer crystals in the shape of triangles.

After a while, evaporated atoms from the second material then attached to the edges of the triangle to create a seamless semiconducting heterojunction.

“This is a scalable technique,” said Sanfeng Wu, a UW doctoral student in physics and one of the lead authors. “Because the materials have different properties, they evaporate and separate at different times automatically. The second material forms around the first triangle that just previously formed. That’s why these lattices are so beautifully connected.”

With a larger furnace, it would be possible to mass-produce sheets of these semiconductor heterostructures, the researchers said. On a small scale, it takes about five minutes to grow the crystals, with up to two hours of heating and cooling time.

A breakthrough in imaging gold nanoparticles to atomic resolution by electron microscopy

Nanometer-scale gold particles are intensively investigated for application as catalysts, sensors, drug delivery devices, biological contrast agents and components in photonics and molecular electronics. Gaining knowledge of their atomic-scale structures, fundamental for understanding physical and chemical properties, has been challenging. Now, researchers at Stanford University, USA, have demonstrated that high-resolution electron microscopy can be used to reveal a three-dimensional structure in which all gold atoms are observed. The results are in close agreement with a structure predicted at the University of Jyväskylä, Finland, on the basis of theoretical modelling and infrared spectroscopy. The research was published in Science on 22 August 2014.

The revealed gold nanoparticle is 1.1 nm in diameter and contains 68 gold atoms organised in a crystalline fashion at the center of the particle. The result was supported by small-angle X-ray scattering done in Lawrence Berkeley National Laboratory, USA, and by mass spectrometry done at Hokkaido University, Japan.

Electron microscopy is similar in principle to conventional light microscopy, with the exception that the wavelength of the electron beam used for imaging is close to the spacing of atoms in solid matter, about a tenth of a nanometer, in contrast with the wavelength of visible light, which is hundreds of nanometres. A crucial aspect of the new work is the irradiation of the nanoparticle with very few electrons to avoid perturbing the structure of the nanoparticle. The success of this approach opens the way to the determination of many more nanoparticle structures and to both fundamental understanding and practical applications.

The researchers involved in the work are Maia Azubel, Ai Leen Koh, David Bushnell and Roger D. Kornberg from Stanford University, Sami Malola, Jaakko Koivisto, Mika Pettersson and Hannu Häkkinen from the University of Jyväskylä, Greg L. Hura from Lawrence Berkeley National Laboratory, and Tatsuya Tsukuda and Hironori Tsunoyama from Hokkaido University. The work at the University of Jyväskylä was supported by the Academy of Finland. The computational work in Hannu Häkkinen’s group was done at the HLRS-GAUSS centre in Stuttgart as part of the PRACE project “Nano-gold at the bio-interface”.