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XPoint NVM Array Process Engineering

Wednesday, October 18th, 2017

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By Ed Korczynski, Sr. Technical Editor

Now that TECHINSIGHTS has published a teardown of a 3D XPoint array, we have seen cross-section transmission electron micrographs (TEM) of the device. From first principles of process engineering, we can make educated guesses as to the process flows and challenges in creating this type of non-volatile memory (NVM) integrated circuit (IC). Evolution of device technology over more than fifteen years has resulted in cross-point arrays connecting precise stacks of chalcogenide materials. Intel with “Optane” and Micron with “QuantX” branded ICs can now claim success in commercializing what has always looked good in R&D but was notoriously difficult to make in high-volume manufacturing (HVM).

Figure 1 shows the TEM cross-section, parallel to the wordline direction, of a XPoint memory cell array taken from an Intel Optane product. There are two levels of cross-point cell-stacks, connected in the middle by bitlines (orthogonal to the wordlines). The upper- and lower-wordlines have been analyzed as tungsten (W) metal with tungsten-nitride (WN) barriers. The memory cell material is a variant on a germanium-antimony-teluride (GeSbTe or “GST”) chalcogenide glass, while the selector material is made with arsenic-silicon-germanium-selenide.

Fig. 1: Cross-section TEM of Intel XPoint NVM array in the wordline direction, showing two levels of memory cell stacks separated by bitline arrays. (Source: greyscale image by TechInsights, color commentary by Ed Korczynski)

Details about the device architecture and memory circuitry are included in the Solid State Technology online blog post by TechInsights’ senior technical fellow Dr. Jeongdong Choe, “Comparing XPoint memory architecture with NAND and DRAM products”. In his presentation at the 2017 Flash Memory Summit, Choe disclosed that the composition of the memory material is Ge0.12Sb0.29Te0.54:Si0.05 and the selector material is As0.29Si0.17Ge0.10Se0.44 while there have been no public mentions yet of what materials are used as buffers to electrodes.

As explained in the Ed’s Threads blog post on June 22nd of this year under the title “PCM + ReRAM = OUM as XPoint,” there has been confusion regarding used of Phase-Change Memory (PCM) material in a device that has a completely different architecture, different switching mechanism, and different performance than what are now known as standard PCM ICs. In standard PCM chips, high current-flow through a bit cell heats up a small mass of material until it changes phase (from crystalline to amorphous or vice-versa). In XPoint arrays, a small current-flow through a bit cell causes ions and atoms to re-arrange following voltage potentials until it changes resistivity, while it is not yet public knowledge how much change happens in material phase. Intel has said that the resistance change is not due to conductive “filament” formation in the GeSbTe:Si but due to some change in the “bulk” of the material.

Processing Speculations

From a HVM perspective, all cross-bar memory architectures share similar constraints and opportunities to design for relatively low-cost and high-yield:

1)     Use PVD blanket layers of complex material stacks as memory and selector and buffers,

2)     Use lithography to mask memory cells in a regular two-dimensional array,

3)     Use ion-beam or chemically-neutral plasma to etch pillars of complex material stacks,

4)     Use ALD/CVD and spin-on-dielectrics to gap-fill electrical isolation around pillars, and

5)     Use dielectric CMP to prepare for metal deposition.

Physical Vapor Deposition (PVD) or “sputtering” processing is based on sublimating a solid material “target” inside a vacuum chamber, which provides a relatively fast and inexpensive way to coat surfaces. Thickness uniformity is typically excellent wafer-to-wafer, while within-wafer uniformity is controlled by process chamber and target geometries. The major concern with PVD using multi-component targets—such as the four element GeSbTe:Si—is that different elements sublimate at different rates such that targets “age” and experience slight predictable composition changes over time. PVD target aging can be compensated for by cleverly varying the ratio of the different elements through the thickness of the target.

When integrating PCM materials into NVM devices, the ability to use a blanket 2D PVD deposition is an inherent advantage over ALD into nano-scale 3D features:  faster, cheaper, and potentially more repeatable if target aging can be managed. Patterning of the memory cell stack requires excellent control over ion directionality to prevent sidewall erosion within the material stack. As can be seen in Figure 1, the sidewalls of the GST:Si are slightly recessed from the thin dark layers directly above and below, indicating a well-controlled process with relatively higher removal rate during etching/milling.

Dielectric gap-fill into what appears to be ~10:1 aspect-ratio features is certainly one of the integration challenges of this process flow. The cross-section shows at least one conformal barrier layer is used in the dielectric isolation between array elements and between bitlines. Dielectric ALD is likely used for barrier formation, while spin-on dielectric (SOD) technology likely provides the gap-filling capability. If the metal interconnects for the CMOS circuitry below the array are built using copper, then a 400°C upper limit on process temperatures would be required for all array fabrication.

Future R&D

Milind Weling, expert in materials/device innovation and senior vice president of programs and operations for Intermolecular, presented at the 2017 Flash Memory Summit on the company’s ability to accelerate the pace of R&D experimentation for the complex materials stacks needed in XPoint memory arrays. In an exclusive interview with SemiMD, Weling discussed the inherent challenges of finding the ideal material within a multi-element compositional space.

“We’ve been working on selectors, and a single-element material is almost useless. What you need is at least a binary, maybe a quaternary, and some people experiment with targets composed of up to seven elements! Once we find a composition that is interesting in our R&D tool, our customers create large targets for their HVM tools.” Figure 2 shows a wafer with 28 isolated circular regions within which different PVD compositions can be independent controlled in a custom R&D tool made by Intermolecular. This tool allows a complete design-of-experiments within a ternary compositional space to be run on a single 300mm-diameter silicon wafer.

Fig. 2: Site-isolated circular regions on a 300-mm silicon wafer A) can each have a different composition within B) a ternary phase diagram when deposited in a special PVD R&D tool. Chalcogenide alloys explored as memory and selector materials in cross-bar NVM arrays may have more than three elements. (Source: Intermolecular)

The materials stack is necessarily complex to be able to form chalcogenide-based NVM cells, and even more complex when buffers are added to allow for integration with CMOS-compatible materials. “Each memory cell is two electrodes sandwiching a GST-type of material, and the selector is two electrodes with one ‘magic’ layer,” explained Weling. “Except for the novel ‘magic’ selector, most of the other materials used in the stack have precedent as unit-process steps in HVM of DRAM or NAND. The difficulty is in tuning the compositions of all layers simultaneously.”

—E.K.

[DISCLOSURE:  Ed Korczynski has no ongoing business relationship with nor owns any equity in Intermolecular.]

Silicon Photonics Technology Developments

Thursday, April 6th, 2017

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By Ed Korczynski, Sr. Technical Editor

With rapidly increasing use of “Cloud” client:server computing there is motivation to find cost-savings in the Cloud hardware, which leads to R&D of improved photonics chips. Silicon photonics chips could reduce hardware costs compared to existing solutions based on indium-phosphide (InP) compound semiconductors, but only with improved devices and integration schemes. Now MIT researchers working within the US AIM Photonics program have shown important new silicon photonics properties. Meanwhile, GlobalFoundries has found a way to allow for automated passive alignment of optical fibers to silicon chips, and makes chips on 300mm silicon wafers for improved performance at lower cost.

In a recent issue of Nature Photonics, MIT researchers present “Electric field-induced second-order nonlinear optical effects in silicon waveguides.” They also report prototypes of two different silicon devices that exploit those nonlinearities: a modulator, which encodes data onto an optical beam, and a frequency doubler, a component vital to the development of lasers that can be precisely tuned to a range of different frequencies.

This work happened within the American Institute for Manufacturing Integrated Photonics (AIM Photonics) program, which brought government, industry, and academia together in R&D of photonics to better position the U.S. relative to global competition. Federal funding of $110 million was combined with some $500 million from AIM Photonics’ consortium of state and local governments, manufacturing firms, universities, community colleges, and nonprofit organizations across the country. Michael Watts, an associate professor of electrical engineering and computer science at MIT, has led the technological innovation in silicon photonics.

“Now you can build a phase modulator that is not dependent on the free-carrier effect in silicon,” says Michael Watts in an online interview. “The benefit there is that the free-carrier effect in silicon always has a phase and amplitude coupling. So whenever you change the carrier concentration, you’re changing both the phase and the amplitude of the wave that’s passing through it. With second-order nonlinearity, you break that coupling, so you can have a pure phase modulator. That’s important for a lot of applications.”

The first author on the new paper is Erman Timurdogan, who completed his PhD at MIT last year and is now at the silicon-photonics company Analog Photonics. The frequency doubler uses regions of p- and n-doped silicon arranged in regularly spaced bands perpendicular to an undoped silicon waveguide. The space between bands is tuned to a specific wavelength of light, such that a voltage across them doubles the frequency of the optical signal passing. Frequency doublers can be used as precise on-chip optical clocks and amplifiers, and as terahertz radiation sources for security applications.

GlobalFoundries’ Packaging Prowess

At the start of the AIM Photonics program in 2015, MIT researchers had demonstrated light detectors built from efficient ring resonators that they could reduce the energy cost of transmitting a bit of information down to about a picojoule, or one-tenth of what all-electronic chips require. Jagdeep Shah, a researcher at the U.S. Department of Defense’s Institute for Defense Analyses who initiated the program that sponsored the work said, “I think that the GlobalFoundries process was an industry-standard 45-nanometer design-rule process.”

The Figure shows that researchers at IBM developed an automated method to assemble twelve optical fibers to a
silicon chip while the fibers are dark, and GlobalFoundries chips can now be paired with this assembly technology. Because the micron-scale fibers must be aligned with nanometer precision, default industry standard has been to expensively align actively lit fibers. Leveraging the company’s work for Micro-Electro-Mechanical Sensors (MEMS) customers, GlobalFoundries uses an automated pick-and-place tool to push ribbons of multiple fibers into MEMS groves for the alignment. Ted Letavic, Global Foundries’ senior fellow, said the edge coupling process was in production for a telecommunications application. Silicon photonics may find first applications for very high bandwidth, mid- to long-distance transmission (30 meters to 80 kilometers), where spectral efficiency is the key driver according to Letavic.

FIGURE: GlobalFoundries chips can be combined with IBM’s automated method to assemble 12 optical fibers to a silicon photonics chip. (Source: IBM, Tymon Barwicz et al.)

GobalFoundries has now transferred its monolithic process from 200mm to 300mm-diameter silicon wafers, to achieve both cost-reduction and improved device performance. The 300mm fab lines feature higher-N.A. immersion lithography tools which provide better overlay and line width roughness (LWR). Because the of the extreme sensitivity of optical coupling to the physical geometry of light-guides, improving the patterning fidelity by nanometers can reduce transmission losses by 3X.

—E.K.

Amkor and Cadence to Develop Packaging Assembly Design Kits for Amkor’s SLIM and SWIFT Packaging Technologies

Thursday, May 5th, 2016

Amkor Technology, Inc., a outsourced semiconductor packaging and test service provider, today announced the expansion of its collaboration with Cadence Design Systems, Inc. to streamline semiconductor package verification with the joint development of a package assembly design kit (PADK) for Amkor’s SLIM and SWIFT advanced fan-out package technologies. As a leader in electronic design automation, Cadence will provide Amkor with PADK development support based on the Cadence Physical Verification System (PVS) software tool. This integrated solution allows Amkor’s customers to shorten the SLIM and SWIFT design and verification cycles.

“We’re at a critical juncture in the semiconductor industry with increased dependence on packaging solutions for delivery of next-generation products,” said Ron Huemoeller, Amkor’s corporate vice president, research and development. “The development of these PADKs, the latest outcome of our lengthy collaboration with Cadence, addresses a critical gap forming between foundry and back-end-of-line, as fan-out packaging solutions blur the lines between these processes. Based on our vast experience with advanced package design methodologies, Amkor is well positioned to lead the industry with our unique fan-out packaging technologies.”

By jointly developing Cadence PVS-based PADKs for SLIM and SWIFT technologies, Amkor and Cadence are filling the gap between semiconductor die design and package design, while refining design methodologies for advanced IC packaging fan-out technologies. Amkor’s PADKs will enable designers to meet the design requirements needed to ensure complete package-level sign-off verification for SLIM and SWIFT technologies and provide more seamless collaboration with their customers.

“To keep up with the industry’s faster-performing, lower-power and smaller form-factor device requirements, fan-out processing is now an essential part of advanced IC packaging,” said Steve Durrill, senior product engineering group director of the PCB Group at Cadence Design Systems. “Our partnership with Amkor fills a void when it comes to complete sign-off verification for this advanced IC packaging technology, helping to accelerate the adoption of SLIM and SWIFT technologies in this fast growing market segment.”

Roll-to-Roll Coating Technology: It’s a Different Ball of Wax

Monday, April 18th, 2016

Compiled and edited by Jeff Dorsch, Contributing Editor

Manufacturing flexible electronics and coatings for a variety of products has some similarities to semiconductor manufacturing and some substantial differences, principally roll-to-roll fabrication, as opposed to making chips on silicon wafers and other rigid substrates. This interview is with Neil Morrison, senior manager, Roll-to-Roll Coating Products Division, Applied Materials.

1. What are the leading market trends in roll-to-roll coating systems?

Neil Morrison: Several market trends are driving innovations in roll-to-roll technology and barrier films.  One is the flexible electronics market where we see the increasing use of film-based components within displays for portable electronic devices such as smartwatches, smartphones, tablets and laptops.

The majority of these passive applications are for anti-reflection films, optical polarizers and hard coat protected cover glass films.

Examples of active device applications include touch sensors. Roll-to-roll vacuum processing dominates this segment through the use of low-temperature deposited, optically matched layer stacks based on indium tin oxide (ITO). Roll-to-roll deposition of barrier film is also increasing with the emergence of quantum dot-enhanced LCD displays and the utilization of barrier films in organic light-emitting diode (OLED) lighting.

In addition to the electronics industry, roll-to-roll technology is used for food packaging and industrial coatings. What’s new today for food packaging is consumers want to be able to view the freshness of the food inside the packaging. Given this, the use of both aluminum foil and traditional roll-to-roll evaporated aluminum layers is slowly being phased into vacuum-deposited aluminum oxide (AlOx) coated packaging.

Within the industrial coatings market segment, significant growth is being driven by the use of Fabry-Perot color shift systems for “holographic” security applications, such as those used to protect printed currency from counterfeiting. This requires the use of electron-beam evaporation tooling to deposit highly uniform, optical quality dielectric materials sandwiched between two metallic reflector layers.

2. What are the leading technology trends in roll-to-roll coating systems?

Neil Morrison: Roll-to-roll coating is being extended to the display industry through the use of higher optical performance substrates with enhanced transmission, optical clarity and color neutrality. These materials are typically more difficult to handle than traditional polyethylene terephthalate (PET) substrates due to inherent properties and the properties of the primer and/or hard coat layers used to treat or protect their surface.

The majority of displays used in mobile applications are moving to thinner substrates, to reduce the “real estate” within the display and enable thinner form factor products and more space for larger batteries.

At the technology level, roll-to-roll sputter tooling dominates the touch panel industry with continual improvements in substrate handling, pre-treatment and inline process monitoring and control. Roll-to-roll chemical vapor deposition (CVD) equipment has also entered the marketplace to address high barrier requirements and to reduce cost compared with traditional sputter-based solutions. Roll-to-roll CVD technology is still in its infancy but is expected to become more prevalent in the near future within the barrier and hard coat market segments.

In the display industry, defect requirements are becoming more and more stringent and are moving towards metrics previously unseen in the roll-to-roll industry.

3. How would you best and briefly describe the Applied SmartWeb, Applied TopBeam, and Applied TopMet systems?

Neil Morrison: The Applied SmartWeb roll-to-roll modular sputtering or physical vapor deposition tool is used to deposit metals, dielectrics and transparent conductive oxides on polymeric substrates for the touch panel and optical coating industry. Its high-precision substrate conveyance system permits winding of polymeric substrates down to thickness levels of ~23 microns at speeds of up to 20 meters/minute depending upon the application. Up to six process compartments with separate gas flow control and pumping allow the deposition of complex layer stacks within a single pass.

Our Applied TopBeam system is a roll-to-roll e-beam evaporation tool used to deposit dielectrics on substrate thicknesses as low as 12 micron and at speeds up to approximately 10 meters/second.  Key to the tool is Applied’s unique electron-beam steering and control system, which provides excellent layer deposition and uniformity at exceptionally high processing speeds by permitting uniform and stable heating of the evaporant material  over the entire width of the substrate.

The Applied TopMet is a high-productivity roll-to-roll thermal evaporation platform available for depositing Al and AlOx layers on substrates down to 12 microns in thickness and is used primarily for food and industrial packaging.

Applied SmartWeb (Source: Applied Materials)

4. Who are Applied’s leading competitors in this market?

Neil Morrison: Other companies in the roll-to-roll market include Von Ardenne, Leybold Optics (Buehler), Schmid, Ulvac and Kobelco.

5. How big is the worldwide market on annual basis?

Neil Morrison: It is difficult to accurately size the entire roll-to-roll market because of the wide variety of applications across multiple industries from flexible electronics to food packaging. Just estimating the size of the market within the flexible electronics category alone is tough because there are three areas that combine to make up the current flexible electronics market – OLEDs for flexible displays, flexible printed circuit boards, and flexible touch panels for phones and tablets. And with applications continuing to grow, it is difficult to provide a specific market size.

Mentor Graphics Adds Support for Integrated Fan-Out (InFO) Packaging Technology at TSMC

Monday, March 14th, 2016

Mentor Graphics Corporation (NASDAQ: MENT) today announced a design, layout, and verification solution to support design applications for TSMC’s Integrated Fan-Out (InFO) wafer-level packaging technology. The solution comprises the Calibre® nmDRC physical verification product, the Calibre RVE™ results viewing platform, and the Xpedition® Package Integrator flow. It enables mutual customers to deploy the unique fan-out layer structures and interconnects in the TSMC InFO technology, targeting cost-sensitive applications such as mobile and consumer products.

The interplay between today’s advanced system-on-chip (SoC) technologies and packaging requirements is driving the need for co-validation between integrated circuit (IC) and package design environments. The Xpedition Package Integrator flow will be Mentor’s platform to support TSMC’s unique TSMC InFO design requirements, including integration with other Mentor solutions—the first being Calibre nmDRC and Calibre RVE.

The Mentor® solution allows IC and package designers to view and cross-probe results from the Calibre nmDRC tool directly inside the Xpedition Package Integrator flow for verification of TSMC InFO interconnect structures. Because this flow is based on proven integration via the Calibre RVE tool, it results in automated sign-off verification and easier correction of any issues highlighted by the Calibre nmDRC product. It also streamlines the addition of future features and capabilities.

IC designers have widely adopted the Calibre nmDRC tool as their sign-off solution for multiple process node generations. Through the integration with Xpedition Package Integrator, they now share a common view with package developers when performing co-verification.

“We are focused on making our solutions easier for customers to adopt by providing a design methodology that leverages proven EDA design tools,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Mentor and TSMC have established this InFO methodology through an integration of the Calibre and Xpedition platforms, and will continue to collaborate on enhancing that solution.”

“Integrating Calibre nmDRC technology with the Xpedition Package Integrator flow is a solid first step in Mentor’s support of TSMC’s InFO technology,” stated Joe Sawicki, vice president and general manager of Mentor Graphics Design to Silicon Division. “We continue to work with TSMC and its ecosystem to expand beyond this initial step by establishing a roadmap for additional capabilities to further accelerate time-to-market for users of TSMC’s InFO offering.”

3D ASIP Conference Hears from EDA, IC Gear Companies

Friday, December 18th, 2015

By Jeff Dorsch, Contributing Editor

John Ferguson of Mentor Graphics provided the electronic design automation perspective on packaging technology at the 12th annual 3D ASIP conference in Redwood City, Calif.

“There’s a lot of interest and a lot of excitement about fan-out wafer-level packaging,” the director of marketing for Mentor’s Calibre DRC product line said, presenting “opportunities and challenges.”

The process of “bringing IC design and package design close together” presents many questions, Ferguson observed. Package design software usually runs on Windows, while EDA tools are on Linux, he noted. “It’s not so easy to mix and match them,” he said.

What manufacturing output to employ? GDSII, Gerber, or OBD++?

“Not all these things have answers yet,” Ferguson acknowledged. “The pieces are not all there yet. We’re partnering with several companies.”

Ferguson touted Mentor’s Xpedition Package Integrator suite for dealing with fan-out wafer-level packaging design. “It brings you across all the domains,” he said. The Mentor software will enable designers to “visualize it and optimize it,” he added.

The conference also heard from executives of three semiconductor equipment companies.

Markus Wimplinger, corporate technology development and intellectual property director at EV Group, spoke about temporary and permanent bonding in chip packaging, comparing chip-to-chip, chip-to-wafer, and wafer-to-wafer bonding.

Chip-to-chip and chip-to-wafer “are more flexible,” while wafer-to-wafer “has great promise,” he said.

David Butler, vice president of product management and marketing at SPTS Technologies, may have taken the prize for longest presentation title with “More Die, Stronger Die. Smaller, Thinner Packages Drives Die Singulation by Plasma Etch.”

“Saws damage die,” he said. “Plasma dicing is better.”

SPTS partnered with DISCO to develop effective die singulation through plasma dicing, according to Butler. “Plasma dicing provides about two times [improvement] in die strength for small die, thin die,” he said.

Rajiv Roy, vice president of business development and director of marketing for Rudolph Technologies, spoke about lithography and inspection requirements for fan-out wafer-level packaging, while touting the company’s experience in those areas.

Wafer and panel warpage can be a concern in FO-WLP manufacturing, he noted. “JetStep successfully measured and corrected for die placement errors,” Roy said, referring to Rudolph’s JetStep Advanced Packaging Lithography Systems, which can accommodate round or square/rectangular substrates.

Solid State Watch: December 12-19, 2014

Saturday, December 20th, 2014
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The Week in Review: September 19, 2014

Friday, September 19th, 2014

Extreme-ultraviolet lithography systems will be available to pattern critical layers of semiconductors at the 10-nanometer process node, and EUV will completely take over from 193nm immersion lithography equipment at 7nm, according to Martin van den Brink, president and chief technology officer of ASML Holding.

North America-based manufacturers of semiconductor equipment posted $1.35 billion in orders worldwide in August 2014 (three-month average basis) and a book-to-bill ratio of 1.04, according to the August EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.04 means that $104 worth of orders were received for every $100 of product billed for the month.

Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs).

Samsung Electronics announced this week that it has begun mass producing its six gigabit (Gb) low-power double data rate 3 (LPDDR3) mobile DRAM, based on advanced 20 nanometer (nm) process technology. The new mobile memory chip will enable longer battery run-time and faster application loading on large screen mobile devices with higher resolution.

ProPlus Design Solutions, Inc. announced this week it expanded its sales operations to Europe.

Mentor Graphics this week announced the appointment of Glenn Perry to the role of vice president of the company’s Embedded Systems Division. The Mentor Graphics Embedded Systems Division enables embedded development for a variety of applications including automotive, industrial, smart energy, medical devices, and consumer electronics.

Intel Announces “New Interconnect” for 14nm

Tuesday, September 2nd, 2014

By Dr. Phil Garrou, Contributing Editor, Solid State Technology

Intel has just announced that Embedded Multi-die Interconnect Bridge (“EMIB”) packaging technology will be available to 14nm foundry customers. Claiming it is a “…lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package.” [link]

Intel released the following description “Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate. EMIB eliminates the need for TSVs and specialized interposer silicon that add complexity and cost.”

It is highly likely that this is tied to the issuance of patent application publication US 2014/0070380 A1 published March 13 2014.

In simplified form interconnect bridges (“silicon glass or ceramic”) are embedded in a laminate substrate and connected with flip chip as shown below.

Bridge Interconnect as described in recent Intel patent.

A cross section of the package is more revealing showing connections through the laminate and connections through the bridge substrate (316) which would be TSV in the case of a silicon bridge substrate. The underside of the bridge substrate (314) may be connected to another bridge substrate for further interconnect routing as shown below.

While there is no silicon interposer, there do appear to be TSV in the embedded interconnect substrate as shown below. While removing complexity from the IC fabrication by eliminating TSV from the foundry process, the packaging operation becomes much more complex.

Since the 2.5D interposer has been reduced in size to the interconnect bridges this may reduce cost, but will increase signal length vs a true 3D stack or a silicon interposer 2.5D.

Further details will be discussed in a future IFTLE blog.

Intel EMIB Module in Cross Section

The Week in Review: August 22, 2014

Friday, August 22nd, 2014

Himax Technologies, Inc., a supplier and fabless manufacturer of display drivers and other semiconductor products, and Lumus, a producer of Augmented Reality glasses, announced another joint initiative to continue developing the next-generation of smart glasses that will set new technological standards in image quality and performance.

North America-based manufacturers of semiconductor equipment posted $1.41 billion in orders worldwide in July 2014 (three-month average basis) and a book-to-bill ratio of 1.07, according to the July EMDS Book-to-Bill Report published this week by SEMI.   A book-to-bill of 1.07 means that $107 worth of orders were received for every $100 of product billed for the month.

Intel Corporation and Unity Technologies this week announced a strategic collaboration to advance the development of Android-based applications on Intel architecture. The agreement accelerates Intel’s mobility push as millions of developers using the Unity development platform can now bring native Android games and other apps to Intel-based mobile devices. Unity adds support for Android across all of Intel’s current and future processors including both the Intel Core and Intel Atom processor families.

MediaTek this week announced the establishment of a new research and development facility in Bengaluru, India. The new R&D facility will focus on developing innovative and inclusive solutions for wireless communications and establish MediaTek’s presence in other core segments such as connectivity and home entertainment devices.

Amkor Technology, Inc. announced that David Watson has been appointed as a new member of the Company’s Board of Directors. With this appointment, Amkor’s Board has been expanded to nine members. Mr. Watson is currently serving as Executive Vice President and Chief Operating Officer for Comcast Cable. In this role Mr. Watson oversees the teams responsible for day-to-day operations of the cable division, including sales and marketing of cable video, high-speed Internet and voice services, as well as oversight of the three operating divisions and Comcast Spotlight, the advertising sales unit.

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced this week that it has shipped over 100 million semiconductor packages with the company’s fcCuBE technology, advanced flip chip packaging with fine pitch copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and enhanced assembly processes.

Intersil Corporation, a provider of power management and precision analog solutions, announced the ISL98611 display power and LED driver for smartphones. The ISL98611 is the first power management IC that integrates the display power and backlight LED driver functions in a single chip. It significantly improves efficiency of both functions to increase smartphone battery life by an hour or more.

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