By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis at Tessera; and Sashi Movva, strategic sourcing specialist at Qualcomm. What follows are excerpts of that conversation.

SMD: Are we starting to blur the lines between what’s a packaging house and what’s a fab with stacked die?
Woychik: Yes, and the blending of the IC fab and the packaging house is absolutely necessary to pull this off. The major fabs are bringing the two together. The foundries are bringing in the packaging guys because they need the packaging discipline to do assembly. How do you assemble it with other materials to make sure you get high yield? That’s going to drive cost. At the same time, you have to make sure the reliability requirements are met.
Movva: That’s not a novel concept. It’s been done in the industry, and it gives flexibility to the fabless companies where you can mix and match different suppliers and different applications. What’s interesting about 2.5D is that it takes it to the next level. Now the foundries and SATs (semiconductor assembly and test companies) are working more closely together. Characterization needs to be done up front. Standards need to be developed so both entities understand what the outputs and inputs are. One a conceptual level this exists. It just needs to be elevated to the next level.

SMD: As we start bridging what were previous silos, we will also need to start bridging the tools used by each. How far along are we?
Movva: It depends on the business model and where the partnering is happening. If there are certain processes done by the fabs, they can do the same process for 2.5D and 3D, like micropillar bumping and stacking. That isn’t new. But if there are certain aspects used specifically by the fabs, then those technologies will need to be developed by the OSATs. It depends on the business model and where the handover happens.
Woychik: The design tool guys already are working with the packaging house. This is where the packaging guys develops test vehicles, and that information is used in the next generation of EDA tools, which is then used in the fab. That’s a classic case of the need for integration. We’re doing the packaging, but that has a key driver on these design guidelines, and it has an effect on EDA tools used by the fabs to develop 3D solutions.
DeLaCruz: The EDA tools are close to where they need to be, but they can’t quite handle it as they currently exist. For example, if you’re doing physical design you generally can only load in one design rule set. If you’re going to design in 40G, you also can’t bring in a 130nm design rule set at the same time for a different chip. If they’re all the same technology, the tools can work with some minor modifications. If you bring in different technologies, they choke. That’s one problem. For simulation, there are no good models available for a TSV. There are so many different flavors of TSVs—you have small tungsten-filled ones, long copper-filled ones, conformal-coded ones where they’re not fully filled with copper—and they all have different electrical properties. Once we have a standard, these tools vendors will modify their tools to include that. We’re not there, and they’re waiting for someone to emerge as a clear leader so they can figure out where to best spend their time.
Baldwin: Today if you have a 40 million-gate device, which could be a processor or some sort of complex ASIC device, you’re going to get a 1,000-page or 2,000-page data sheet. People are going to come through and say, ‘Here’s the product and here’s the data sheet, go implement this device.’ And you have three months. You can’t even read it. And you have to go through and integrate it. And you have board work around it, and you have to model it and simulate it. With 3D we have the potential to bring in processors and memory and analog. Does that bring in an era where we can get rid of these data sheets and build completely integrated systems that can be integrated into a larger system in a useful amount of time? There are issues with integration of cost and power, but the big one is schedule.

SMD: Are the test tools integrated with other tools?
Pateras: They’re separate worlds, other than for things like Verilog netlists and RTL and constraints. Aside from those, they’re really separate flows. The issue with test is you need to have control of all the various parts. If you don’t, that’s where standards come in because we don’t have a solution.

SMD: How do we deal with proximity effects like leakage, noise, electrostatic discharge and electromigration?
Movva: 3D proximity effects could be mechanical, electrical and thermal. There are areas where you could characterize and create tools. It’s not possible to characterize all combinations and features, so you’ll have to use simulation to create certain rules based on what is permissible.
DeLaCruz: From an ESD standpoint, the interconnects that are designed to be solely from chip to chip don’t need ESD interconnects. But that assumes you know how that chip will be used in every possible situation. That makes it very difficult. If there is an interconnect that goes chip to chip in one format, it might be lead system in another version. So now you need to raise it above the core voltage and put ESD protection on it. This is all going to waste power and you will lose a lot of the benefit of the 3D architecture. As long as you know well ahead of time that these banks of I/O are not going to do anything but talk to another chip in my 3D and 2.5D architecture then they don’t need higher voltage, buffers or ESD protection. From an electromigration standpoint in the TSV, that’s really going to come down to the reliability of the oxide or whatever else is put into the via layer. Right now most papers are related to a certain thickness of oxide, but we all know it’s pretty brittle and it could give us leakage problems. It’s not well understood this point, and that’s part of the risk.

SMD: How about in test? Is there any focus on physical effects yet?
Pateras: We’re right now addressing it as if the defects we will have to deal with will be the same as in 2D. We’re just looking at accessibility and observability of the various components such as TSVs. Whether or not there are defect mechanisms that we would see with general interconnects is unknown.

SMD: And from a packaging side, the goal has always been the cheapest package. Will that change?
Woychik: When anyone hears packaging they still require low cost. That will still be the case with stacked die. That’s also why it’s so important to address these packaging issues right now. A lot of people have focused at the fab level. There needs to be more focus on the packaging level to address assembly and yield and also reliability. There are no showstoppers. It’s just a refinement of the technology. This is an extension of the work we’re already doing in packaging to drive a lot of these models. When you start building these structures and do the detailed metric measurements, this produces good information for EDA tools.

SMD: How about an exchange of data between vendors in other areas?
DeLaCruz: Outside of memory, there is very little activity going on with die-to-die information standards. There’s no reason to have multiplex signals raise the voltage as you go from chip to chip. But there’s no I/O interface standard for chip-to-chip.
Woychik: But there are cases where it’s working and other cases where it’s not working. What you’re seeing is OEM drivers helping to develop the infrastructure. For example, Xilinx got together with TSMC, Ibiden and Amkor to pull off this solution. These OEMs are driving it, and you’ll see more and more of that happening. That’s the early stage of larger-scale integration that will have to happen to make this a reality.
Pateras: We definitely need some information to be provided if the various die are coming from multiple sources. If you look at a memory stack on logic, if you’re going to test that memory die with self-test on the logic die, you need to know the memory’s address space, its physical scrambling, redundancy and how it’s architected. In 2D, that kind of information is being provided by the memory vendors. In a 3D world, these frequently are different vendors. They’re not involved in that kind of information exchange right now. That will have to change.

SMD: Will the supply chain get bigger because of stacking or will it shrink?
Movva: There won’t be a change in the supply base. What will change is the partition between the different players, where one takes over from the other.
DeLaCruz: I disagree. No matter what, you have at least one more link in the supply chain—someone stepping in to provide tiles. If you’re vertically integrated, that’s not a big deal. But if you’re trying to source a PLL, voltage regulator or SerDes from all these different players, who’s is in charge of taping out these tiles? Who’s going to inventory them and make sure they’re all test-compatible with each other? That’s a link in the supply chain that doesn’t exist today. Right now no one is the world leader in that role.
Woychik: There’s a battle brewing between who’s going to take ownership for these parts, and it’s not clearly defined. The packaging house will certainly take on a bigger responsibility than it has in the past.
DeLaCruz: I’m not so sure the packaging houses will have the appetite for taking on ownership and inventory. They’re going to want to see it come ready for assembly. What they will grow into is more assembly practices.
Woychik: The classic case is the PoP module, which is well-defined with the logic on the bottom and the memory on the top. With a 3D TSV, who takes this on? There’s a business risk.
Baldwin: If you think about PCB design and then you take this concept forward into 3D design, maybe you’ll have a die that’s a PLL or a SerDes or a logic block or memory block. You can imagine a Lego build in 3D. But if there’s too much complexity in packaging, assembly and test, what we will need are larger constructs. So what is the optimal process for any function? With 3D there will be an analog wafer, and that analog wafer will probably be 0.13 (microns). There will be a digital die at a lower geometry for integration. And then you can think about how these functions will be pushed up and down through this die stack. The conclusion is that you will have vertical-specific subsystems. You’ll have to. If someone is providing analog subystems, they’ll have to say, ‘This is the analog subsystem of a cell phone or a tablet or a WiFi system.’ And they’re going to have to provide these. Only after they’ve been integrated can we start dealing with the inefficiencies of aligning TSVs and making sure the modeling is correct so you can integrate it into a 3D stack. That’s going to force aggregation around function.
Woychik: That’s where 2.5D can play a very nice role, and why it will play an important role. That’s a likely interim solution. Then way when you go to 3D, you’ll be more prepared to deal with the business issues of who does what.
Movva: The business model is one of the biggest issues. Who owns the logic and who owns the memory? Those are the kinds of questions the industry has to address. That may be the biggest hurdle for the adoption of 3D.

By Ed Sperling
Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis at Tessera; and Sashi Movva, strategic sourcing specialist at Qualcomm. What follows are excerpts of that conversation.

SMD: What’s driving the push toward 3D stacking?
Baldwin: The customers have a function they need to get to market. They’re integrating for power. They’re integrating for area. They’re also integrating for cost. They come to us with a problem and say, ‘Help us get this solution to market.’ Part of our solution is going to be standard design services. Part of it could be in the form of a die library, which is a menu of tiles. Die libraries have a lot of promise. You have building block functions that are captured at the die level with industry-standard TSV spacing, test methodologies—all the things that allow us to make a Lego building-block stack out of disparately sourced devices. This is a good idea. It’s difficult with today’s technology.

SMD: That brings up an interesting point, which is exactly what we mean when we refer to stacking. We have memory, memory on logic, and 2.5D stacks in a package. For each the problems are different. Where do we start?
DeLaCruz: Those are different solutions to different problems. A 3D stack is going to be very small and compact. Putting lots of large die together in a 3D stack is not going to make a lot of sense. There will be a lot of reasons for 2.5D, though. If you do the math, it may be less expensive to do a 2.5D solution than to make one large monolithic solution. From an NRE risk standpoint, re-using tiles that are proven and well-known will reduce the risk. The only reason that people go to 28nm or 22nm is they have one or two IP blocks on there that require going to that smaller node, whether it’s memory or the processor. Once it’s done and proven out, it’s likely that everything else can be done at a lower-cost node. Being able to put things together in a larger area space is where 2.5D will have its sweet spot. It will be a lot less expensive. But the 3D arena is more of a space-constrained environment. Having very high-powered devices in a 3D environment is not going to work out too well. It works very well in the mobile market where space is important and low power is the key.
Movva: From a technical aspect, 2.5D addresses the mechanical reliability and thermal aspects. You don’t have to directly characterize the effects of the vias on the node due to the interposer.
Baldwin: The idea of an interposer sounds very evolutionary from today. Just like we’re using package substrates for multichip modules, we can use an interposer inside the package and gain greater density. But now your tools can’t fully model the electromagnetic effects of a through-silicon via. How you’re going to handle that is to space off at first so there’s a do-not-use zone around each via. But you have an interposer, which doesn’t have a ground plane, so now you need coaxial-type TSV structures going down into the interposer and asserting some sort of electrical level. And now you have a large area that’s do-not-use, and you ask all your providers of these die libraries who is willing to make their die less optimal so it gains this potential of use in a 2.5D or 3D package? Who will increase their unit cost to support this potential function?
Woychik: Talking with the users, everyone agrees 3D is the way this is going to go. But getting there will be non-trivial. It’s a big job because you have to look at ‘keep off’ zones. How do you come up with a design tool to lay out the TSV. This is where the 2.5D silicon interposer plays a good role because it provides a useful means to get there and it’s a good learning tool. The classic case we’ve all been hearing about is the Xilinx Virtex 7. The main driver for that is how you get a large die that yields sufficiently. They’re able to yield smaller pieces that integrate on silicon substrate. That gave them about 95% of the performance. That was a major enabler. At the same time, it helped drive the interposer technology. To do that in a 2.5D device is non-trivial. You take baby steps before you take the big one, and that will help drive the total 3D solution. Meanwhile, we see 2.5D won’t go away.

SMD: Is there any standardized way for testing 2.5D chips?
Pateras: You can apply some of the 3D approaches. Typically you don’t need them in 2.5D. With 3D, Imec has developed a test elevator concept because there’s no accessibility to the die that are stacked. You have access to the bottom and top die, but there’s no access anywhere else. So you have to use TSVs to get from one die to the next. With 2.5D, very often the die you’re placing on an interposer have access to the outside world. There’s less of a need to create a complex infrastructure for access test resources like built-in self-test and scan chains.

SMD: This industry has had mixed results with standards. The dueling power formats are a case in point. Will we able to move with standards in a stacked die world and have we really learned any lessons.
Movva: There is a lot of momentum that started several years ago in standards for design, manufacturing and even handling. The handling is going to be critical when there are multiple companies involved. But all of that is needed to enable the 3D supply chain. We would like to see that momentum continue.
Pateris: I’m optimistic, particularly in test. If you look at history, we’ve tended to narrow in on some well-adopted standards for test. Going back 20 years, we combined various chips at a board level and developed IEEE 1149.1 and the JTAG (Joint Test Action Group) standards. There are only a couple standards being developed for 3D and there are contributions from all the major players. My feeling is they will be successful.

SMD: How good or bad will the effect of disaggregation be on stacking?
DeLaCruz: The various different standards for test and wafer handling are moving. But there is nothing dealing with the interconnects. You didn’t really have to worry about those before because everyone could handle their own stuff as long as they could fit it into a package. But to design one of these tiles to go into a 3D tile is not the same as you would design the interconnect to go into a 2.5D structure. In 2.5D you don’t have your signals on all four sides because it would require using too many layers of an interposer to route them all over. Dropping the cost of the interposer by reducing the number of layers is very important. The number of layers in an interposer is a big cost savings. Planning out these tiles ahead of time is important. But will the design of a tile be for the 3D space, where interconnects are over the entire area, or with 2.5D where the interconnects are mostly on one or two adjacent edges. That’s where I don’t see any standards.
Baldwin: If you look at the foundries and their business model, 3D is a clear inflection point. They have to maintain enablement. People that want to bring them business have to be able to do that. We can’t ask all the customers to take on 3D chip design. It’s something where people will need a concrete definition of what the chip needs to do and then a way to get it developed. That exists today in the digital realm. They can go to partners and get that implemented. Those two worlds are going to meet. We’re going to have companies whose role is to take the solution from the customers and take the enablement models that come out of the foundries and put the two together. So there will be a huge push from the ecosystem to make that happen. That will require standards and modeling. Currently they’re all working on drilling and filling, but there’s a lot more to come.
Woychik: This gets into the integration. It can’t work in a disaggregated environment. It has to be fully integrated. That’s where the packaging house can play a very important role. That’s where it can all come together. You’ll get into standards for design, test, how to lay out the die. And who’s going to make it? The packaging house. The package will drive the solution to get to the end customer. That’s why you’re seeing a close alliance between the packaging house and the IC fabs today. They both need each other.

By Mark LaPedus, SemiMD senior editor

For some time, DRAM makers have been developing 3D memory chips, but commercial products still are not due out for some time because of technical and cost issues.

But the advent of the 3D DRAM era could be near the turning point, as two memory rivals have separately moved to bring their respective technologies closer to production. In one move, Micron Technology Inc. has disclosed the manufacturing flow for its recently announced Hybrid Memory Cube (HMC) technology, a 3D DRAM scheme geared for high-end servers and networking systems. Under the plan, IBM will manufacture the controller logic portions of the HMC within its own fab. Micron will make the memory portions, as well as assemble and test, the HMC devices within its own operations.

On another and more surprising front, Japanese DRAM maker Elpida Memory apparently has beat its larger rivals to the punch by announcing the industry’s first commercial Wide I/O DRAMs. The first device from Elpida, dubbed Wide IO Mobile RAM, is a 4 Gbit device based on a 30nm process technology and a 3D structure using through-silicon vias (TSVs). Elpida plans to sample its first Wide I/O DRAM devices this month. The devices are geared for next-generation smartphones and tablets.

Samsung Electronics Co. Ltd. and Hynix Semiconductor Inc. are also separately developing 3D DRAMs. The idea behind a 3D device is to stack existing die and connect them using TSVs, thereby lowering the resistivity and boosting the bandwidths. But the problems with 3D devices based on TSVs involve cost, technical issues and supply-chain headaches.

“There is a lot of attention and engineering resources being thrown at 3D right now by all DRAM developers, including Samsung, Micron, Elpida, and Hynix,” said Mike Howard, senior principal analyst for DRAM and memory at IHS iSuppli. “Wide I/O has yet to really reach a cost level that makes it competitive and we are likely still a few years away from mass adoption. Elpida may very well have a functioning part in the lab and may be able to produce test samples, but I think we’re still a few years away from this being used in anything but the most premium markets.”

Sherry Garber, an analyst with Convergent Semiconductors LLC, had another viewpoint about Elpida’s announcement. “The demand for wide I/O has the attention of the DRAM manufacturers. It is one of the memory alternatives for the rapidly expanding mobile DRAM market. Soft demand for the PC has increased the importance of mobile consumer products such as tablet, smartphone and eReader to memory manufacturers. It is significant that Elpida is dedicated to the mobile DRAM market and will have samples this year of this emerging product. This is a new DRAM market that will develop with the availability of proven product, production availability and volume pricing,” she said.

Hank Lai, product planning for memory marketing at Samsung Semiconductor Inc., said Wide I/O DRAMs are not expected to gain traction until sometime in 2013. At present, smart phones and tablets are using plain-vanilla, low-power DDR3 DRAMs or mobile DRAMs based on the LPDDR2 interface standard. Before Wide I/O, the mobile market will move from LPDDR2 to the next-generation LPDDR3 interface standard, Lai said.

LPDDR2 has a maximum throughput of 8.5 Gbytes/second. LPDDR3 has a peak throughput of 12.8 Gbytes/second. Samsung claims its new LPDDR3 devices consume 20% less power than LPDDR2.

Elpida’s Wide IO Mobile RAM has 512 I/O pins. The device is said to achieve a data transfer rate of 12.8 Gbytes/second, roughly similar to LPDDR3. But Elpida’s Wide IO Mobile RAM has a height of 1.0mm, compared to 1.4mm with existing mobile DRAMs based on today’s package-on-package (PoP) technology.

Elpida acknowledged that the Wide I/O market will take time to evolve. The 4 Gbit Wide I/O DRAM will sample next month, but production “will take place sometime in the second half of 2012,” according to officials from Elpida. “For volume production, it will be sometime in 2013.”

In March of 2012, Elpida plans to sample a 16-Gbit DRAM, which is based on stacking four 4-Gbit Wide IO Mobile RAM chips. Mass production is due sometime after 2013, according to Elpida.

Meanwhile, on the other end of the spectrum, Micron and Samsung are moving full speed ahead with HMC. “This is a slightly different product than Elpida’s and is targeted at server customers. The specs are very promising, but again, this is still a few years from hitting the big time—2013 at the soonest,” iSuppli’s Howard said. “Samsung is also a part of the HMC group, lending weight to the product’s chances.”

In October, Samsung and Micron announced the creation of a consortium to develop an open interface specification for HMC. Micron is the actual designer of the HMC technology. Micron and Samsung, as well as Open-Silicon, Altera and Xilinx, are the founding members of the Hybrid Memory Cube Consortium (HMCC).

HMC will incorporate DRAM arrays stacked on a logic chip. The device is connected with 2,000 to 3,000 TSVs. HMC prototypes are said to clock in with bandwidth of 128 Gbytes/second.

It is not a widely known fact, but fabless ASIC house Open-Silicon is developing the controller IP for HMC. Colin Baldwin, director of marketing and business development for Open-Silicon, said the HMC controller will be based on the company’s Interlaken controller IP. Interlaken is a high-speed, chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2. The Interlaken controller will serve as the interface between the memory and physical layer to help “boost the bandwidth” in the device, Baldwin said.

On the manufacturing front, the HMC device itself will go through a two-step process. The controller logic portion of HMC will be manufactured at IBM’s semiconductor fab in East Fishkill, N.Y., using the company’s 32nm, high-k metal gate process technology. IBM also will handle the TSV creation process based on Micron’s specifications.

Micron will develop and make the DRAM arrays in-house based on a 3xnm process within its own fabs, said Mike Black, a technology strategist at Micron. Micron will take the logic controller from IBM—and the in-house made memory arrays—and then will assemble and test the entire HMC device within Micron’s R&D production line in Boise, Ida, Black said.

Micron is in the qualification stage with the device. “We are feeling pretty good about it,” he said. “Most of the learning is done.”