The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore’s law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. This paper focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based.

To view this white paper, click here.

Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various solutions, including:

• DP design methodologies, current DP conflict feedback mechanisms, and how they can help designers identify and resolve conflicts.
• Effects on place and route (P&R) and new reqirements for physical design.
• Why LELE DP cuts and overlaps are critical to optical process correction (OPC).
• Mask misalignment and image rounding as new verification considerations.

To download this white paper, click here.

By Mark LaPedus
For years, electron-beam tools have been struggling to keep up with photomask complexity, causing an alarming increase in write times and mask production costs.

Intel and others recently warned that e-beams soon could reach their fundamental limits, thereby requiring the need for new solutions. And in the multiple patterning era, mask makers could see their capital costs soar, as they may end up buying twice as many e-beam tools than before.

E-beams, which pattern the most advanced layers in a photomask, are based on a vector-shape beam (VSB) technology. “VSB architectures may not be adequate beyond 10nm,” said Mahesh Chandramouli, a photomask technologist who recently gave a paper on behalf of Intel. “We think new alternatives must be considered.”

Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks, framed the challenges in a different light. “If we continue to push out next-generation lithography, will we be able to meet the challenges with the existing technology? And if we do multi-patterning at 14nm, 10nm, and maybe 7nm, what does that mean for the mask writer? The real answer is that we’re going to have a big gap. We are not going to meet write time demands. By 2018, we will be in a tough state if we don’t do something different,” Kalk warned.

One solution to the problem is faster e-beams from the two main tool vendors-JEOL and NuFlare Technology. Other solutions include better shot count techniques, new data preparation methods and newfangled layout schemes.

The ultimate solution is a fast, multi-beam mask writer. And for some time, the spotlight has centered on IMS Nanofabrication, an Austrian-based company that has been working on a multi-beam mask writer that could speed up write times and lower photomask costs. Other companies, including KLA-Tencor and Mapper Lithography, are developing multi-beam tools for another application, namely direct-write maskless lithography.

It could be several years before multi-beam tools enter the commercial market. There are some major technical hurdles and a perceived funding gap associated with e-beam technology in general. The big question is whether the industry is willing to make the necessary investments to commercialize multi-beam. And does the industry have the patience to wait. “It’s an investment issue more than anything else,” said Aki Fujimura, chairman and chief executive of D2S. “If there was more funding, (e-beam technology) would be much more successful.”

End of the vacation
The photomask industry is changing on several fronts. Until the mid-1990s the industry enjoyed what was commonly called the “mask makers’ holiday.” Chip feature sizes were larger than lithography wavelengths, making photomask production a straightforward process.

The vacation abruptly ended in the late-1990s, when the industry was forced to extend 248nm wavelength lithography amid delays with 193nm technology. IC features became smaller than lithography wavelengths, prompting the need for resolution enhancement techniques (RETs).

Today, the industry is not counting on another vacation. IC makers are pushing 193nm lithography far beyond what was once possible, thereby adding more RETs and multiple patterning to the mix. Extreme ultraviolet (EUV) lithography was supposed to provide some relief, because it brings patterning back to single exposure. EUV is late due to an assortment of problems.

Perhaps the only silver lining is that mask costs are not increasing as fast as some had predicted. Mask costs are increasing on a linear curve, but clearly, there are new and complex challenges ahead. “At the 90nm node, there was a need for mild optical proximity correction (OPC),” said Amitabh Sabharwal, general manager for mask etch products at Applied Materials. “At 45nm, there was moderate OPC. Moving down to 22nm, there is aggressive OPC. Where we are headed right now is what I call crazy OPC. The sub‐resolution assist features (SRAFs) are extremely small, and, on top of that, there are a lot of them on the mask itself.”

Going forward, verification costs and OPC run times are expected to soar at 10nm and beyond. “The total run times scales in accordance with the number of patterning steps,” said Yuri Granik, chief scientist within the Design to Silicon Division at Mentor Graphics. “Double patterning alone and SRAFs will increase OPC run times by 1.3x to 2x.”

Mask complexity is increasing in other respects. In total, the average layers in a mask set jumped from 25 at the 180nm node, to 45 to 50 at 28/32nm. At 20nm, a mask set could have 75 layers. And in multi-patterning, the number of layers escalates. For example, in double-patterning, a single mask layer becomes two layers.

The trouble is that e-beams are not keeping up with the extensive use of OPC and other RETs, causing write times and costs to jump. From 2001 to 2005, e-beam write times were constant, averaging 8 hours per mask set, Toppan’s Kalk said. Then, from 2007 to 2012, the average write times rose to about 10 hours per mask set, he said.

“The average write time for a high-end mask is around 10 to 12 hours right now. Twelve hours doesn’t sound like much, but thrown into that are some 5 hour write times and some that are 40 hours,” he said. “Based on the predictions we have, it looks like we’ll see a lot more of the 40 hour variety and a lot less of the 5 hour variety in the next few years.”

Multiple patterning is also causing a change in the mask production flow. Typically, mask makers process a mask set using one e-beam. In double patterning, which involves two separate masks, photomask makers could write the critical layers in sequential steps using one e-beam tool.

In a more likely scenario, a mask maker would simultaneously utilize two e-beams to process each mask to speed up the process. That means a photomask vendor must procure more e-beams, thereby increasing their capital costs. In total, an e-beam sells from $20 million to $50 million each, depending on the configuration.

The solutions
To keep capital spending and mask costs at bay, Kalk listed three possible solutions: shot count optimization, one-dimensional layouts, and multi-beam mask writers. “We need all of them,” he said.

Responding to the demands, JEOL and NuFlare separately have been shipping faster e-beams. “There are always people who say e-beams will only go for one more node,” said Russell Cinque, an applications manager for the Electron Beam Lithography Products Division at JEOL. “Then, e-beams are able to extend for another two or three nodes. Looking into the future, we need to make some improvements, but we are confident we can meet spec.”

But at 20nm and beyond, the SRAFs and related features are projected to be 80nm in width or smaller, making mask accuracy and yield difficult to maintain. The number of e-beam shots required to create these complex features is expected to cause mask write times to soar.

To help their causes, e-beam vendors are reaching out to the EDA industry for help. For example, Aselta has tuned its preparation software that promises to streamline the data flow for NuFlare’s EBM-8000 e-beam. In a separate effort, D2S recently rolled out TrueMask MDP, a model‐based mask data preparation (MB‐MDP) technology. TrueMask MDP reduces e-beam shot count to cut mask write times by 20% to 30%.

In addition, the industry is looking at one-dimensional layouts based on gridded design rules. In this approach there are two lithography steps—grating and line cuts—to pattern designs. Using this complementary lithography technique, the mask is supposedly less complex, thereby reducing mask write times.

Still, there is an urgent need for one solution: multi-beam mask writers. This technology makes use of multiple beams to speed up write times. “There is a consensus that the industrial needs can only be met by adopting multi-beam mask writing techniques,” said Elmar Platzgummer, chief executive of IMS.

Nevetheless, multi-beam vendors are making slow progress after years of R&D. There are daunting challenges in herding multiple beams in a system at tight resolutions and accuracies. In part, vendors blame the sluggish progress on the lack of industry funding, as compared to what the cash-flush EUV community has garnered.

The industry is finally stepping up to the plate. For example, DNP, Intel, Photronics and TSMC have joined IMS’ multi-beam development collaboration effort. In addition, IMS has recently completed a proof-of-concept technology, dubbed the electron multi-beam Mask Exposure Tool (eMET).

Using 262,144 programmable beams with 20nm beam sizes, the 50-keV tool has demonstrated a half-pitch resolution capability of 24nm, Platzgummer said. IMS is looking to bring out its tools for “the 11nm half-pitch node,” he said. The goal is to have an alpha tool in 2014, beta machines by 2015, and a high-volume mask writer by 2016.

For a different application, namely maskless lithography, KLA-Tencor recently reported progress for its technology, dubbed Reflective Electron Beam Lithography (REBL). Recently, KLA-Tenor installed a CMOS-based digital pattern generator module on its system. This enables more than 1 million beams at full current, said Regina Freed, process development marketing manager for the REBL program.

“Multibeam is a disruptive writing technology,” noted Toppan’s Kalk. “If we don’t get something like that by 2018, it’s going to be a tough business model for everybody.”

As the technology advances, OPC run time turns to be a big concern, and a great deal of our effort is directed toward speeding up the litho operations. In addition, the OPC simulation consistency sometimes deteriorates, which is a critical issue—especially for anchor features. On the other hand, full-chip designs usually comprise large arrays of basic cells, used by OPC engineers to tune OPC recipes, which is evident for instance for memory design and processor chips. The model-based OPC technique is not necessary for such designs, provided that the equivalent mask shapes for one cell of these arrays are already known.

In this work, we introduce a combined approach using model- and pattern-based OPC. Pattern matching is used to extract regions from full chips that match the basic designs stored in pre-created libraries. When matching occurs, the OPC solution stored in these libraries is used and populated across matched areas. Special treatment for large array boundaries is applied due to proximity effects. Model-based OPC is used for the rest of the chip. This approach has two main advantages. First, simulation consistency is greatly improved because the OPC solution for standard cells is known. And second, pattern matching is a DRC-based tool, and thus it is very fast compared to litho operations and hence TAT is further enhanced.

To download this white paper, click here.

By David Lammers

D2S, Inc. has introduced a mask-wafer double simulation tool which employs the graphical acceleration capabilities delivered by GPU-enhanced workstations.

Aki Fujimura

Introduced at the Bacus mask technology conference going on this week in California, the TrueMask DS tool is aimed at mask shops, engineers implementing optical proximity correction (OPC) features, and IC designers, said CEO Aki Fujimura.

Sub-resolution assist features (SRAFs), used to boost the energy received at the wafer level, are become more curvilinear and thus harder for the variable-shaped beam (VSB) e-beam mask writers to handle. “For a long time, e-beam writing has been so accurate. Engineers could assume that what you ask the mask writer to do will be what is on the mask. That is no longer the case when shapes are less than 80nm and more curvilinear,” said Fujimura.

At the 20 nm node, and even at the 28nm node, design teams need to evaluate the mask features at the wafer plane, and mask shops need to understand wafer-level effects as well. Previous efforts to do that involved lithography simulation with estimations (corner rounding) of the impact at the wafer level. That bundled model is running out of steam, he said.

Mask shapes have to be simulated to understand what is going to happen on the wafer. First, the curvilinear mask shapes are simulated. As the simulated light source projects the shape on to the wafer surface, TrueMask DS creates an energy intensity map received by the wafer.

“As (SRAF) features become smaller than 80nm, engineers must understand what is going to print on the wafer. They must simulate what is on the mask, then simulate at the wafer level. The industry started with the bundled model, and now goes to a separated model with double simulation tools,” he said.

The D2S team built graphical acceleration into the TrueMask DS tool. Nvidia Inc. supports engineering applications, and modern graphics processing units (GPUs) are essential for interactive simulations. Fujimura said the what would take hours of compute time with conventional approaches can be reduced to tens of seconds with TruMask DS running on a graphics workstation.

Mask shapes are becoming more complicated at 20nm. (Source: IBM)

“The user experience is totally different,” he said. “The amount of space the designers can explore is much different. If you try to give a curvilinear shape in a conventional simulation program for a 5µm by 5µm area on the wafer, it will take hours and hours. With our GPU accelerated simulation engines we can do this in tens of seconds. There is a big difference from an engineer’s perspective. It provides an interactive space in which the engineer can explore in interactive time.”

Engineers can change the shapes in an exploratory manner, which he said can make a major difference in the “amount of completeness or thoroughness the engineer can explore.”

A slightly different shape, with perhaps a one shot increase on the mask, can make a major difference at the wafer level. With a double simulation tool, engineers can explore the tradeoffs of what is happening on the mask and what is happening on the wafer, he said.

Source: Handel Jones, IBS, Inc.

TrueMask DS arrives as mask complexity is exploding. Double patterning at critical layers is required in order to accommodate the SRAF features, which involve increasingly complex shapes. Some companies have publicly discussed the need for quintuple (5x) patterning. With SRAF complexity in some case going up by five times, and as many as five masks required to write one layer on the wafer, mask complexity can increase by 5X to 25X.

D2S started nine years ago with direct write lithography as its main market. Fujimura, who earlier worked in technical roles at Cadence Design, said the underlying physics of the VSB e-beam machines is the same for both direct write e-beam lithography and for mask writing. The D2S engineering team spent about three years on TrueMask DS, he said, and has a number of already-granted patents.

Because mask dimension are four times what appears on the wafer, he said the direct-write lithography community faced the accuracy challenge much earlier than the mask-writing sector. That gave D2S a head start on solving the simulation problems now faced at the mask level, including corrective technologies.

“Two generations later, the same problems we see in direct write we see on the masks. We prepared for this a long time ago,” he said.

Franklin Kalk, chief technology officer at Toppan Photomasks in Round Rock, Texas, said the TrueMask software offers features not seen to date. “In a small 5 by 5 micron area, you can change the size of the assist features and see how that works as a printed feature on the wafer. We have not seen that in the past, and it is pretty neat,” Kalk said. The tool is also helpful in identifying hot spots in local areas, he added.

by Ed Korczynski

Many presentations at SPIE Advanced Lithography this year focused on the need to shift from 2D to essentially 1D layouts in masks as double-patterning is pushed to ever smaller geometries. For the third year in a row Valery Axelrad of Sequoia Design Systems and Michael Smayling of Tela Innovations presented results from collaborations. Canon has been working with both companies for some time now. The update this year was a combined presentation from all three companies entitled, “Optical lithography applied to 20nm CMOS logic and SRAM” [7973-39].

Patterning 20nm node chips with 193nm lithography is difficult even with immersion technology, since the Metal-1 (M1) pitch will be ~64nm, which is well below the 80nm limit for single exposure. Pushing the limits is possible with double-patterning (DP) when each pattern to essentially a 1D layout: Gridded Design Rules (GDR) to make uniform arrays, followed by a “cut” pattern of selectively placed orthogonal line segments. The cut layer thus becomes the most critical in terms of lithographic parameters, with similarities to the hole patterns used in contact layers. For both critical layers, density variations arise due to differences between logic and memory areas.

With Optical Proximity Correction (OPC) now at the limit, source-mask optimization (SMO) improves margins at the resolution limit, but can only make major improvements to small cells or repetitive designs like memory. OPC has been used for full-chip manufacturability improvements at previous technology nodes, but will not converge these days. “Convergence problems always arise when you have near neighbors and correlations between them,” explained Axelrad.

The authors also considered fundamental lithographic manufacturability parameters such as Depth of Focus (DOF), Normalized Illumination Log Slope (NILS), and Mask Error Enhancement Factor (MEEF) before and after SMO. Working with Canon steppers, realistic lens distortions using experimentally obtained Jones-Zernike expansions as well as realistic entrance pupil illumination were obtained as inputs to models.

Co-Optimization of Layout and Lithography

Simultaneous optimization of layout patterns and lithography settings is made possible by the uniformity and repeatability of the lines/cuts patterns. Optimization variables for the cut layer include the cut geometry (width, height, serifs), illumination of the scanner lens entrance pupil, and grouping cuts in similar optical environments to allow for local OPC. The optimization was for the CD error across all cuts, which also reduces variation among cuts by getting all CDs close to the same target value. This reduction of variation substantially simplifies the layout and OPC and produces manufacturable designs including both SRAM and logic.

There are many ways to formalize GDR+cut DP litho, but Tela and partners propose the following 1D rules :

• Highly uniform 1D GDR layouts with sparse identical cuts,
• critical layers are cuts,
• all cuts identical to each other and tripled to ensure yield,
• cuts also on a fixed grid (avoiding difficult neighborhoods),
• interactions between cuts sufficiently small for local iterative OPC to converge using SMO, and
• Use of a M0 layer to reduce the number of cuts and improve uniformity of cut density.

An algorithm was developed to resolve OPC and SMO for critical cut and hole layers:

STEP1: SMO (a.k.a. “co-optimization”) to find optimal cut shape and size, and illumination of the scanner lens entrance pupil (source), using a small representative sample portion of the layout.

STEP2: Local layout correction (pseudo-OPC) using information from Step1 to create the ideal size for the rectangles at each location, some a little smaller and some a little larger. Typically only 3-5 iterations are needed reach <1 nm RMS CD for a 42 nm target CD, which takes 30-60 seconds on a quad-core CPU, for a total simulation time of ~2 hours on a single CPU for ~120 windows.

The test chip is a 100k MOSFET including 50 different standard cells for SRAM and logic, in 50 x 60 microns area, using a 3 x 3 microns SMO sample window. The optimal illumination is a horizontal dipole. Axelrad claimed that after this extensive Source-Mask Optimization (SMO) the critical dimension (CD) error could be <1 nm at best focus conditions for both logic and SRAM cells at the 20nm node.

by Ed Korczynski

Lithography is where design meets manufacturing, and so the SPIE Advanced Lithography (AL) conference this year was where Applied Materials and Magma Design Automation chose to launch their new collaborative solution to the problem of managing yield data when ramping the most complex ICs in high-volume manufacturing (HVM). As device features continue to shrink ever smaller than the 193nm of ArF steppers, process windows continue to shrink to reveal complex interdependent yield loss mechanisms. Add in new materials and evolving device structures, and the industry must be able to learn quickly about new yield-loss mechanisms and then efficiently pass that learning back to designers.

In an exclusive meeting with SemiMD during SPIE, representatives of the two companies explained that this new effort is not directed toward solving random yield defects—due to particles for example—but systematic defects due to intrinsic process-design interactions. With ever smaller process windows and interdependencies, maintaining past yields with established design-rule check (DRC) software, “isn’t possible without new methodology,” explained Erez Paran, Applied Materials’ Integrated Solutions Manager, Process Diagnostics and Control. “This solution is intended to enable manufacturing below the 20nm node.”

The companies report seeing a growing gap between simulation and actual manufacturing data. Even with the best optical-proximity correction (OPC) and other reticle-enhancement techniques (RET), masks still have yield-loss “hot spots” when printed into resist in real fabs. Consequently, unlike the traditional way of doing pre-tapeout simulation, this simulation is post-tapeout to be closer to real fab results. GlobalFoundries has reportedly been working with this for over a year now.

Yield management in deep-sub-micron IC fabs only gets more challenging. The traditional method of “binning” yield loss mechanisms starts to fail when the number of bins explodes, and just because a bin appears more frequently does not mean it will be the most critical. As an almost trivial example, post-OPC masks today include “dummy structures” that can short together without loosing any yield. Not all functional paths can be considered to be critical paths, and sorting the critical from the non-critical is one of the key filters to manage the data volume. The software dashboard provides automated visualization tools to overlay inspection data on design information (figure).

Applied and Magma use the Knights Data Base (KGD) as the foundation for managing yield in 20nm node and beyond ICs (source: Applied Materials)

The inspection data shows geometries where there are particular process window limits. Since the limit is systematic and the process is necessarily inflexible, the only possible fix must come from the design using something like additional OPC. With proper data management, the information can be fed further backward within the EDA flow to modify the library level for additional designs. “So it’s sort of short-loop for immediate work, and helps designs go faster for future products in the same process node,” explained Paran.

Knights Data Base (KDB)—part of Magma since the 2006 acquisition of Knights Technology—is the foundation of this new yield management solution. “It’s not only a depository, but a well mined and well correlated data base at the bottom of it all,” said Ankush Oberai, general manager and vice president of Magma’s Fab Analysis Business Unit, “and that’s what makes our solution unique. There’s a lot of input from Applied Materials to this, it’s not just cobbling the two companies’ stuff together.”

The smallest pixel in the inspection tool is ~100nm today, and since some fabs are engaged with 20nm node pilot work, Erez explained that, “if you look at the number of structures you have today there can be five. So it becomes a matter of image processing, algorithms, search-engines, correlation-engines.”

The data base can compare inspection information to more than just a GDSII mask layout, including netlist levels. “Today, there is no single-pattern that can reflect the whole design, so it’s becoming more and more difficult,” said Oberai. “We can overlay the defect map on the layout map, and the layout map is now hierarchical and enriched with critcal path information.”

New fabless business models

When is a design closed? It used to be that passing DRC for a given process-design kit (PDK) meant that a chip should yield. Now the industry faces a time of complexities when designs to be modeled rely on multi-variate simulations based on statistics with varying degrees of confidence.

If following the PDK is necessary but not sufficient, then how can a small team of fabless designers get their chip to yield in a fab? “You can see a new market emerging of small and medium sized companies taking new designs and mediating or cleaning them for manufacturing,” explained Oberai. “You see many more starts ups at the chip level, the entry barrier is becoming lower.” However, the cost to get a lithography mask-set written for advanced IC manufacturing is still probably a million dollars.

Once all these changes have been absorbed, it will invariably be time for yet additional methodology innovation to manage ever increasing yield complexity. “Geometries are not going to stop shrinking, says Oberai, and expects only more data streams to be managed since, “Insitu sensor technologies will take a greater role so we can have predictive data.”