Part of the  

Solid State Technology

  and   

The Confab

  Network

About  |  Contact

Posts Tagged ‘OEM’

Edge Placement Error Control in Multi-Patterning

Thursday, March 2nd, 2017

thumbnail

By Ed Korczynski, Sr. Technical Editor

SPIE Advanced Lithography remains the technical conference where the leading edge of minimum resolution patterning is explored, even though photolithography is now only part of the story. Leading OEMs continue to impress the industry with more productive ArFi steppers, but the photoresist suppliers and the purveyors of vacuum deposition and etch tools now provide most of the new value-add. Tri-layer-resist (TLR) stacks, specialty hard-masks and anti-reflective coatings (ARC), and complex thin-film depositions and etches all combine to create application-specific lithography solutions tuned to each critical mask.

Multi-patterning using complementary lithography—using argon-fluoride immersion (ArFi) steppers to pattern 1D line arrays plus extreme ultra-violet (EUV) tools to do line cuts—is under development at all leading edge fabs today. Figure 1 shows that edge placement error (EPE) in lines, cut layers, and vias/contacts between two orthogonal patterned layers can result in shorts and opens. Consequently, EPE control is critical for yield within any multi-patterning process flow, including litho-etch-litho-etch (LELE), self-aligned double-patterning (SADP) and self-aligned quadruple-patterning (SAQP).

Fig.1: Plan view schematic of 10nm half-pitch vertical lines overlaid with lower horizontal lines, showing the potential for edge-placement error (EPE). (Source: Y. Borodovsky, SPIE)

Happening the day before the official start of SPIE-AL, Nikon’s LithoVision event featured a talk by Intel Fellow and director of lithography hardware solutions Mark Phillips on the big picture of how the industry may continue to pattern smaller IC device features. Regarding the timing of Intel’s planned use of EUV litho technology, Phillips re-iterated that, “It’s highly desirable for the 7nm node, but we’ll only use it when it’s ready. However, EUVL will remain expensive even at full productivity, so 193i and multi-patterning will continue to be used. In particular we’ll need continued improvement in the 193i tools to meet overlay.”

Yuichi Shibazaki— Nikon Fellow and the main architect of the current generation of Nikon steppers—explained that the current generation of 193i steppers, featuring throughputs of >200 wafers per hour, have already been optimized to the point of diminishing returns. “In order to improve a small amount of performance it requires a lot of expense. So just improving tool performance may not decrease chip costs.” Nikon’s latest productivity offering is a converted alignment station as a stand-alone tool, intended to measure every product wafer before lithography to allow for feed-forward tuning of any stepper; cost and cost-of-ownership may be disclosed after the first beta-site tool reaches a customer by the end of this year.

“The 193 immersion technology continues to make steady progress, but there are not as many new game-changing developments,” confided Michael Lercel, Director of Strategic Marketing for ASML in an exclusive interview with SemiMD. “A major theme of several SPIE papers is on EPE, which traditionally we looked at as dependent upon CD and overlay. Now we’re looking at EPE in patterning more holistically, with need to control the complexity with different error-variables. The more information we can get the more we can control.”

At LithoVision this year, John Sturtevant—SPIE Fellow, and director of RET product development in the Design to Silicon Division at Mentor Graphics—discussed the challenges of controlling variability in multi-layer patterning. “A key challenge is predicting and then mitigating total EPE control,” reminded Sturtevant. “We’ve always paid attention to it, but the budgets that are available today are smaller than ever. Edge-placement is very important ” At the leading edge, there are multiple steps within the basic litho flow that induce proximity/local-neighbor effects which must be accounted for in EDA:  mask making, photoresist exposure, post-exposure bake (PEB), pattern development, and CD-SEM inspection (wherein there is non-zero resist shrinkage).

Due to the inherent physics of EUV lithography, as well as the atomic-scale non-uniformities in the reflective mirrors focusing onto the wafer, EUV exposure tools show significant variation in exposure uniformities. “For any given slit position there can be significant differences between tools. In practice we have used a single model of OPC for all slit locations in all scanners in the fab, and that paradigm may have to change,” said Sturtevant. “It’s possible that because the variation across the scanner is as much as the variation across the slit, it could mean we’ll need scanner-specific cross-slit computational lithography.” More than 3nm variation has been seen across 4 EUVL steppers, and the possible need for tool-specific optical proximity correction (OPC) and source-mask optimization (SMO) would be horrible for managing masks in HVM.

Thin Films Extend Patterning Resolution

Applied Materials has led the industry in thin-film depositions and etches for decades, and the company’s production proven processing platforms are being used more and more to extend the resolution of lithography. For SADP and SAQP MP, there are tunable unit-processes established for sidewall-spacer depositions, and chemical downstream etching chambers for mandrel pull with extreme material selectivity. CVD of dielectric and metallic hard-masks when combined with highly anisotropic plasma etching allows for device-specific and mask-specific pattern transfers that can reduce the line width/edge roughness (LWR/LER) originally present in the photoresist. Figure 2 from the SPIE-AL presentation “Impact of Materials Engineering on Edge Placement Error” by Regina Freed, Ying Zhang, and Uday Mitra of Applied Materials, shows LER reduction from 3.4 to 1.3 nm is possible after etch. The company’s Sym3 chamber features very high gas conductance to prevent etch byproducts from dissociation and re-deposition on resist sidewalls.

Fig.2: 3D schematics (top) and plan view SEM images (bottom) showing that control of plasma parameters can tune the byproducts of etch processes to significantly reduce the line-width roughness (LWR) of minimally scaled lines. (Source: Applied Materials)

TEL’s new SAQP spacer-on-spacer process builds on the work shown last year, using oxide as first spacer and TiO2 as second spacer. Now TEL is exploring silicon as the mandrel, then silicon-nitride as the first spacer, and titanium-oxide as second spacer. This new flow can be tuned so that all-dry etch in a single plasma etch chamber can be used for the final mandrel pull and pattern transfer steps.

Coventor’s 3D modeling software allows companies to do process integration experiments in virtual space, allowing for estimation of yield-losses in pattern transfer due to variations in side-wall profiles and LER. A simulation of 9 SRAM cells with 54 transistors shows that photoresist sidewall taper angle determines both the size and the variability of the final fins. The final capacitance of low-k dielectric in dual-damascene copper metal interconnects can be simulated as a function of the initial photoresist profile in a SAQP flow.

—E.K.

3D memory for future nanoelectronic systems

Wednesday, June 18th, 2014

thumbnail

By Ed Korczynski, Sr. Technical Editor

The future of 3D memory will be in application-specific packages and systems. That is how innovation continues when simple 2D scaling reaches atomic-limits, and deep work on applications is now part of what global research and development (R&D) consortium Imec does. Imec is now 30 years old, and the annual Imec Technology Forum held in the first week of June in Brussels, Belgium included fun birthday celebrations and very serious discussions of the detailed R&D needed to push nanoelectronics systems into health-care, energy, and communications markets.

3D memory will generally cost more than 2D memory, so generally a system must demand high speed or small size to mandate 3D. Communications devices and cloud servers need high speed memory. Mobile and portable personalized health monitors need low power memory. In most cases, the optimum solution does not necessarily need more bits, but perhaps faster bits or more reliable bits. This is why the Hybrid Memory Cube (HMC) provides >160Gb/sec data transfer with Through-Silicon Vias (TSV) through 3D stacked DRAM layers.

“We’re not adding 70-80% more bits like we used to per generation, or even the 40% recently,” explained Mark Durcan, chief executive officer of Micron Technology. “DRAM bits will only grow at the low to mid-20%.” With those numbers come hopes of more stability and less volatility in the DRAM business. Likewise, despite the bit growth rates of the recent past, NAND is moving to 30-40%  bit-increase per new ‘generation.’

“Moore’s Law is not over, it’s just slowing,” declared Durcan. “With NAND, we’re moving from planar to 3D, and the innovation is that there are different ways of doing 3D.” Figure 1 shows the six different options that Micron defines for 3D NAND. Micron plans for future success in the memory business to be not just about bit-growth, but about application-specific memory solutions.

Fig. 1: Different options for Vertical NAND (VNAND) Flash memory design, showing cell layouts and key specifications. (Source: Micron Technology)

E. S. Jung, executive vice president Samsung Electronics, presented an overview of how “Samsung’s Breaking the Limits of Semiconductor Technology for the Future” at the Imec forum. Samsung Semiconductor announced it’s first DRAM product in 1984, and has been improving it’s capabilities in design and manufacturing ever since. Samsung also sees the future of memory chips as part of application-specific systems, and suggests that all of the innovation in end-products we envision for the future cannot occur without semiconductor memory.

Samsung’s world leading 3D vertical-NAND (VNAND) chips are based on simultaneous innovation in three different aspects of materials and design:

1)    Material changed from floating-gate,

2)    Rotated structure from horizontal to vertical (and use Gate All Around), and

3)    Stacked layers.

To accomplish these results, partners were needed from OEM and specialty-materials suppliers during the R&D of the special new hard-mask process needed to be able to form 2.5B vias with extremely high aspect-ratios.

Rick Gottscho, executive vice president of the global products group Lam Research Corp., in an exclusive interview with SST/SemiMD, explained that with proper control of hardmask deposition and etch processes the inherent line-edge-roughness (LER) of photoresist (PR) can be reduced. This sort of integrated process module can be developed independently by an OEM like Lam Research, but proving it in a device structure with other complex materials interactions requires collaboration with other leading researchers, and so Lam Research is now part of a new ‘Supplier Hub’ relationship at Imec.

Luc Van den hove, president and chief executive officer of Imec, commented, “we have been working with equipment and materials suppliers form the beginning, but we’re upgrading into this new ‘Supplier Hub.’ In the past most of the development occurred at the suppliers’ facilities and then results moved to Imec. Last year we announced a new joint ‘patterning center’ with ASML, and they’re transferring about one hundred people from Leuven. Today we announced a major collaboration with Lam Research. This is not a new relationship, since we’ve been working with Lam for over 20 years, but we’re stepping it up to a new level.”

Commitment, competence, and compromise are all vital to functional collaboration according to Aart J. de Geus, chairman and co-chief executive officer of Synopsys. Since he has long lead a major electronic design automation (EDA) company, de Geus has seen electronics industry trends over the 30 years that Imec has been running. Today’s advanced systems designs require coordination among many different players within the electronics industry ecosystem (Figure 2), with EDA and manufacturing R&D holding the center of innovation.

Fig. 2: Semiconductor manufacturing and design drive technology innovation throughout the global electronics industry. (Source: Synopsys)

“The complexity of what is being built is so high that the guarantee that what has been built will work is a challenge,” cautioned de Geus. Complexity in systems is a multiplicative function of the number of components, not a simple summation. Consequently, design verification is the greatest challenge for complex System-on-Chips (SoC). Faster simulation has always been the way to speed up verification, and future hardware and software need co-optimization. “How do you debug this, because that is 70% of the design time today when working with SoCs containing re-used IP? This will be one of the limiters in terms of product schedules,” advised de Geus.

Whether HMC stacks of DRAM, VNAND, or newer memory technologies such as spintronics or Resistive RAM (RRAM), nanoscale electronic systems will use 3D memories to reduce volume and signal delays. “Today we’re investigating all of the technologies needed to advance IC manufacturing below 10nm,” said Van den hove. The future of 3D memories will be complex, but industry R&D collaboration is preparing the foundation to be able to build such complex structures.

DISCLAIMER:  Ed Korczynski has or had a consulting relationship with Lam Research.