By Mark LaPedus
The NAND flash memory market is entering into a new and painful cycle, a period that will impact suppliers, OEMs and fab tool vendors alike.

For some time, there has been an oversupply and depressed pricing in the NAND market. In mid-2011, Micron, Samsung, SK Hynix and Toshiba put on the brakes in their capital spending plans. And in recent months, NAND suppliers in total have announced plans to cut 150,000 wafer starts per month, or about 12% of the world’s NAND capacity, amid ongoing losses and sluggish demand.

Just as suppliers moved to cut their production, spot shortages of NAND surfaced at some OEMs in early September. Most OEMs are not seeing any shortages, but that could all change. Apple, the world’s largest buyer of NAND, could cause some gyrations in the channels as it ramps up its new iPhone 5.

So what’s the outlook in the fluid and confusing NAND market? Amid a bitter legal battle with Samsung, speculation is rampant throughout the NAND industry about whether Apple will swap suppliers from Samsung to SK Hynix, Toshiba and Micron. If that happens, Samsung would face an oversupply in NAND, while others may see capacity shortfalls.

The outlook is also not so rosy for fab tool vendors, which counted on a big capital spending cycle for NAND. In fact, NAND suppliers are expected to push out their capital spending plans until June of 2013 and perhaps beyond, said Vijay Rakesh, an analyst with Sterne Agee.

The lack of capital spending is expected to create a shortfall in NAND capacity, creating perhaps a long cycle of acute shortages. Presently, there is a capacity glut for NAND. “Demand should catch up with capacity by mid-2013,” said Jim Handy, an analyst with Objective-Analysis. “Then, there could be NAND shortages from then until the middle of 2015.”

In total, suppliers are expected to ship 28.013 billion gigabits of NAND in 2012, which represents a bit growth of 49% over 2011, according to Stern Agee. The figure is lower than the historical averages in terms of bit growth, which ranges from 65% to 85%, according to the firm. In total, suppliers are expected to ship 43.756 billion gigabits of NAND in 2013, which represents a bit growth of 56%, according to Stern Agee.

Boom to bust
NAND has seen its share of boom and bust cycles. Several years ago, NAND vendors witnessed a meteoric rise amid a boom for cell phones, flash cards, USB drives and other products.

Then, over the last two or so years, Micron, Samsung, SK Hynix and Toshiba began to expand their NAND production at a dramatic pace. The goal was to meet the anticipated demand for the next wave of product drivers, such as smartphones, solid-state drives (SSDs), tablets and ultrabooks.

Seeking to drive down product costs, particularly for SSDs, NAND vendors took the lead in process technology. For example, the Toshiba-SanDisk duo has been ramping up parts based on the world’s most advanced process, a 19nm technology.

The bottom fell out of the NAND market in recent times. NAND vendors built up too much fab capacity. Average selling prices (ASPs) for NAND fell by 46% in the first half of 2012. Demand for NAND in smartphones and tablets remains overwhelming, but SSD and ultrabook shipments have been disappointing thus far.

“The adoption of solid-state drives is not ramping as quickly as forecast, and with only a modest increase in the bits per box for mobile devices, we now see NAND bit growth in the range of 60% to 65%,” said Mike Splinter, chairman and chief executive of Applied Materials, during a recent conference call. As a result, NAND vendors in total plan to cut production by roughly 150,000 wafer starts per month “on top of a reduction in their capital spending,” Splinter said.

Based on recent announcements, Toshiba is cutting 30% of its NAND production, Micron is reducing its output by 15%, and SK Hynix and Samsung are each at 10%, said Hans Mosesmann, an analyst with Raymond James. “Using these percentages, this would equate to a 12% reduction in supply,” he said.

NAND vendors expected bit growth of about 70% in 2012, but they have lowered their forecasts to about 45%, said Robert Witkow, president of Westwood Marketing, a research firm. “All manufacturers are regulating bit growth by slowing the transitions of 2xnm to the 1xnm node,” Witkow said. “All manufacturers are slowing their transitions from 64-Gbit to 128-Gbit devices.”

One OEM, OCZ Technology, lowered its quarterly forecast in September, saying it could not obtain enough NAND parts for its SSDs. “My price survey and other feedback I’ve received confirm some tightness (in NAND supply),” Witkow said. “If we have allocation in NAND, which I think is possible in 2012, it will be short-lived. I think the NAND market will ease at the end of October, as production sold for Christmas winds down.”

The average selling price (ASP) outlook is good for consumers, but horrific for suppliers. In September 2010, NAND crossed the $1.00/GB price point. The price dropped to $0.35/GB in May of 2012, according to Objective-Analysis’ Handy. “It hit $0.31/GB in June, but then it went back up to $0.36/GB in August,” Handy said. “The June pricing was below manufacturing costs, which is unsustainable. It could go as low as $0.31/GB again, but not temporarily as it did before. That would be permanent.”

NAND CapEx slows
On the fab tool side of the equation, Applied Materials and others saw a softening in demand for gear in the summer, due in part to sharp declines in foundry and NAND spending. By late August, tool vendors saw a further deterioration in NAND, causing more tool pushouts, according to Applied’s Splinter.

Capital spending will remain anemic in DRAMs. The foundries expanded their 28nm capacities earlier this year. But more recently, foundries put the brakes on spending to digest their new tool buys, Splinter said. In total, fab tool capital spending is expected to reach $30 billion to $33 billion in 2012, down 10% to 20% from 2011, he said. In its original projection, Applied forecasted a flat year in fab tool spending.

There’s good and bad news for fab tool vendors. For example, Samsung, the world’s largest NAND vendor, is cutting some NAND production. But the company also is converting some of its NAND production to system LSI and foundry services. As it turns out, logic is more profitable than NAND.

Samsung still wants to remain the leader in NAND. Last year, for example, the company began ramping up NAND production in Line 16 in Korea. “Samsung has slowed its expansion of Line 16, but it did not cut wafer starts,” said Westwood Marketing’s Witkow.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, is a foundry plant dedicated for Apple.

The other fab in Austin is currently a NAND facility. Austin represents about 20% of Samsung’s total NAND capacity, according to Barclays Capital. However, Samsung is converting that fab from NAND into a system LSI plant, said Christian Gregor Dieseldorff, an analyst with SEMI. “Ultimately, all of Austin will be converted to system LSI,” Dieseldorff said.

In Korea, Samsung’s main logic/foundry fab is called S1, which is being expanded. Samsung is converting its Line 14 plant in Korea from NAND to 28nm logic capacity. Line 14 is now part of S1, he said.

Meanwhile, Toshiba, the world’s second largest NAND vendor, in June announced plans to cut NAND production by about 30% at its Yokkaichi Operation fab in Mie Prefecture, Japan. At a minimum, this could remove 6% of worldwide NAND supply, according to Barclays Capital.

Micron, the world’s third largest NAND vendor, is re-balancing its capacity. “Micron increased its triple-level-cell (TLC) wafer production slightly, but reduced its multi-level-cell (MLC) slightly in June. My belief is that the move was taken to support the Lexar consumer product builds for Christmas. Micron will likely shift (its production) back to MLC shortly,” said Westwood Marketing’s Witkow.

SK Hynix, the world’s fourth largest NAND vendor, added 10,000 wafer starts at its new M12 fab in Korea. But SK Hynix is also mulling plans to shift its capacity from NAND to DRAM in M12, according to Barclays Capital.

By Mark LaPedus
For years, many have predicted the end of flash memory scaling, particularly NAND, but the technology continues to defy the odds as it moves down the process curve.

Still, there are signs that the floating gate structure in today’s flash memory is on its last legs. The floating gate is seeing an undesirable reduction in the control gate to capacitive coupling ratio. And there is an increase in cell-to-cell interference in the word lines.

“The floating gate has been very successful in scaling down to the current 20nm node or even the 1xnm node,” said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “There is not much room for the floating gate to scale. Nobody really believes that planar NAND can go below 10nm.”

Today, the Toshiba-SanDisk duo is shipping NAND devices based on the world’s most advanced process, a 19nm technology. Going forward in NAND, Lee and others see at least two or more nodes remaining in the 1xnm regime.

The question is what’s after NAND flash? Currently, the industry is pursuing three basic categories in the NAND replacement sweepstakes: scaling existing NAND; 3D NAND; and the next-generation memory types.

There is no clear-cut winner right now. But in some circles, the initial and most promising successor is 3D NAND. “3D NAND is an extension of existing NAND,” Lee said. “Vertical NAND is in the development stage right now. The timeline for mass production is as early as 2013. Some companies have announced 2015.”

Defying the odds
Clearly, flash scaling has defied the odds. Ten years ago, Intel, the first vendor that commercialized NOR flash, predicted that flash would hit the wall at 65nm. Banking on those predictions, a number of firms began to develop various next-generation memory technologies that could replace NAND, NOR or DRAM—or all three. FeRAM, MRAM, phase-change and ReRAM are among those candidates.

The prediction was wrong, however. NAND has scaled down to 19nm, while NOR has migrated to 45nm. Thanks to 193nm immersion lithography and self-aligned double patterning (SADP), flash vendors have been able to scale the floating gate.

The ability to scale NAND and NOR has also pushed out the need for the next-generation memory types. And besides, most of these new memory types are still in R&D. They are expensive to make and difficult to scale.

Scaling today’s NAND down to 10nm is also difficult. NAND vendors may have to use self-aligned quadruple patterning, as extreme ultraviolet (EUV) lithography remains delayed. “NAND is even beyond current EUV resolutions. Even if EUV is available as of today, double patterning has to be used together with EUV,” Lee said.

There is also a remote chance that today’s 2D NAND could scale further using charge trap technology. Charge trap uses a silicon nitride film to store electrons. “I think the generation of charge trap flash as a planar device is limited,” he said.

Initially, if or when today’s NAND runs out of gas, the industry is banking on 3D NAND. “With 3D NAND, scaling is no longer driven by lithography. The gate length is defined by deposition,” Lee said.

3D NAND is also challenging, but the production steps are slightly different than 3D stacked DRAM and logic. The key step to 3D NAND is to build a multitude of oxide/nitride or oxide/doped polysilicon stacked layers. Another key step is to fill the deep memory holes or trench slits. “The top foreseeable challenges are ultra-high-aspect ratio (>40:1) conductor etch and dielectric etch with high etch selectivity to the hard mask,” Lee said in a recent paper.

There’s another challenge as well: Can the 3D NAND developers put their products into production? The main 3D NAND contenders are Toshiba’s BiCS, Samsung’s VG-NAND, Macronix’ BE-SONOS, Hynix’ vertical cylindrical FG, SanDisk’s 3D memory and Intel/Micron’s stackable PCM, according to Forward Insights.

The 3D NAND industry emerged in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. BiCs makes use of a “punch-and plug” structure and charge trap memory films. Toshiba has fabricated a prototype 32-Gbit BiCS flash memory test array with a 16-layer memory cell using 60nm design rules.

In 2009, Samsung described its 3D NAND technology based on a terabit cell array transistor (TCAT). A year later, Macronix talked about a BE-SONOS charge-trapping technology. And Hynix is developing a 3D dual control-gate with a surrounding floating-gate.

One of the newer candidates is the stackable phase-change memory (PCM) device from Intel and Micron. Micron recently announced a 2D PCM device based on a 45nm process. In PCM, it is difficult to scale the cell array. PCM is also limited by the power required to change from the crystalline to an amorphous state.

Researchers are looking at new materials beyond traditional GST-225 schemes to overcome these limitations. Among those materials are binary and ternary alloys like germanium telluride (GeTe). “GeTe is one of the enablers,” said Jean-Luc Delcarri, general manager of Altatech, a CVD and inspection equipment subsidiary of Soitec. Altatech has installed its CVD system at CEA-Leti, which is developing PCM for the sub-20nm node.

It’s unclear which 3D NAND devices will eventually move into production, but there is a huge appetite for NAND in mobile and other applications. “I can’t say which vendor is ahead,” Applied’s Lee said. “I think vertical NAND will likely be adopted in traditional applications. The biggest applications are smartphones, tablets and mobile computing. What is still to come are SSDs.”

3D NAND debate
Analysts have slightly different viewpoints. “The only company that has told me a schedule is Toshiba, who plans to sample 3D NAND in 2013,” said Jim Handy, an analyst with Objective-Analysis, a research firm.

“The thing that is driving (3D NAND) is the use for more bytes in video,” Handy said. “3D NAND is straightforward for a DRAM maker since it has stacked SiO2 and polysilicon layers like a stacked capacitor DRAM and trenches like a trench cell DRAM. I have heard that the aspect ratios for the trenches are somewhat tricky.”

Greg Wong, an analyst with Forward Insights, does not see commercial production for 3D NAND until 2015 or so. “NAND flash manufacturers are pushing planar NAND flash to sub-20nm nodes. As they extend the roadmap for 2D NAND, the introduction of 3D NAND gets pushed out,” Wong said.

“There are technical challenges with etching a high aspect ratio pillar and multiple stacks, but the big challenge is economic. The investment required is significantly more for 3D than 2D NAND,” Wong said. “3D NAND employing charge trapping technology will have some challenges in meeting the performance specifications of 2D NAND. However, by stacking multiple layers, lower cost per bit can be attained.”

Alan Niebel, president of Web-Feet Research, agreed. “3D NAND should enter the market around 2015 (or after). Designing and qualifying 3D NAND will probably be a seven year process, which started in 2007. Concurrently, it takes easily another five years to perfect the manufacturing and especially in manufacturing 3D ICs,” Niebel said.

“3D NAND should have a much higher areal density and lower cost than 2D NAND, since the F2 divides in half with each layer, probably four layers max per chip. Performance in both speeds (read and write) and endurance will deteriorate with 3D NAND compared to 2D,” he added. “The stacked structure will have more bits to address, more interconnects with each layer and longer distance from cell to controller that will add latency to the 3D. Perhaps endurance may not suffer too much if the lithography is the same for 2D and 3D NAND cells, but by stacking them in 3D, these additional steps could possibly fatigue the control gate oxides and further reduce endurance.”

Besides the technology challenges, Applied’s Lee sees another hurdle—cost. “NAND vendors will go into 3D only if they can meet a cost target. We are quite confident the cost structure of 3D NAND will be lower than 2D NAND. The reason is that 3D NAND is less lithographic and double-patterning heavy,” he said.