By Mark LaPedus
New research reveals that 53% of office workers with computers are opting to either fix their own computer problems, or ask a co-worker or someone else for help, instead of relying on an IT professional/helpdesk. The nationwide survey, conducted online by Harris Interactive on behalf of Crucial.com, also revealed that 29% of office computer users cite computer problems (lost files, slowness, crashes, etc.) as the top reason for reduced productivity in the office. Office computer problems trumped co-workers (25%), workload (22%), management (22%) and customers/clients/vendors (15%) when it comes to negatively affecting worker productivity in the office.

Big banks may be considered too big to fail, but their size and operational complexity create performance drags that could also make them too big to succeed, according to Gartner. Bank CIOs and COOs must innovate in IT and operations to negate a problem Gartner has identified as the “law of diminishing IT returns.”

Intel announced its annual equipment and materials supplier awards. The awards provide an insight regarding the fab suppliers at Intel, which normally declines to comment about the identity of its vendors. The winners are interesting, but it’s even more interesting to see which vendors failed to make the list. Meanwhile, Intel announced the eight winners of the company’s most prestigious award for equipment and materials suppliers, the Supplier Continuous Quality Improvement (SCQI) award. In addition, Intel announced that 17 equipment and materials companies will receive the 2012 Intel Preferred Quality Supplier (PQS) award.

DARPA has achieved world record power output levels using silicon-based technologies for millimeter-wave power amplifiers. The power amp was based on a multiple-stacked, 45nm silicon-on-insulator (SOI) CMOS device.

Electronic components distributor Digi-Key announced the signing of a global distribution agreement with Adesto Technologies, a developer of nonvolatile memory chips. One of Adesto’s investors is Applied Ventures, the venture capital arm of Applied Materials.

The global semiconductor materials market decreased 2% in 2012 compared to 2011, while worldwide semiconductor revenues declined 3%, according to SEMI.

For the Southeast Asia region, SEMI expects to see capital equipment investment to bottom out in the first half of 2013 and a mild pickup in the second half followed by a strong recovery in 2014. Overall front-end fab equipment spending is expected to double next year from $810 million in 2013 to $1.62 billion in 2014, according to SEMI.

Mentor Graphics announced various hardware and software solutions to accelerate the verification of Serial Attached SCSI (SAS) second-generation (Gen 2) products. Using the Mentor verification solutions, designers can test their SAS Gen2 devices integrated on their SoC designs, and develop and test their software drivers and applications prior to silicon being available.

Entegris, a supplier of contamination control and materials handling solutions, has acquired the assets of Jetalon Solutions, a California-based supplier of fluid metrology products.

Avago announced the execution of a definitive agreement to acquire CyOptics, a supplier of indium phosphide (InP) optical chip and component technologies for the data communications and telecommunications markets, for an aggregate acquisition price of approximately $400 million in cash.

2012 was a miserable year for the semiconductor market, with only 8 of the top 25 chipmakers managing to eke out revenue growth. Among the top 25 suppliers, the only companies to expand revenue in 2012 were No. 2 Samsung, No. 3 Qualcomm, No. 9 Broadcom, No. 11 Sony, No. 14 NXP, No.15 nVidia, No.18 MediaTek and No. 24 LSI.

Worldwide PC shipments totaled 79.2 million units in the first quarter of 2013, a 11.2% decline from the first quarter of 2012, according to preliminary results by Gartner. Global PC shipments went below 80 million units for the first time since the second quarter of 2009.

3D printing, touted as an enabling platform for applications ranging from personalized medicine to personal drones, will grow to an $8.4 billion market in 2025, up from $777 million in 2012. However, consumer applications will have limited upside, according to Lux Research, while industrial uses generate the most value.

By Mark LaPedus
In today’s systems, consumers want more performance and bandwidth with a longer battery life.

Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the past few years,” said Abe Yee, senior director of advanced technology and package development at Nvidia. “Memory bandwidth has not kept up.”

In fact, there is a growing gap between memory bandwidth and overall system requirements, creating an unwanted I/O bottleneck, Yee said. The memory bandwidth gap, resistance-capacitance (RC) delays and other factors are fueling the development of new 3D DRAM schemes like Wide I/O. “We need Wide I/O memory,” he said. “We also need a known good die stack.”

But advanced chip stacking has a multitude of challenges and is still a few years away from mass production. One of the bigger, and sometimes forgotten, challenges is the ability to obtain and test known good die (KGD). A KGD is an unpackaged part or a bare die that meets a given specification.

As chip complexity increases, the industry may need to lower its targets and not expect a perfect KGD. In other words, the idea of having a KGD may not be attainable. “Ensuring KGD is (expected to be) more difficult in the ‘more than Moore Era,’ “ said Bill Bottoms, chairman and chief executive of ATE vendor Third Millennium Test Solutions (3MTS), in a recent presentation. “The era of known good die is drawing to an end. The concept of known good die will be displaced by ‘probably good die’ for very complex systems.”

Not all is lost, however. To address the KGD problem, the industry is developing a new class of probe cards. Chipmakers also are counting on a range of design-for-test (DFT) technologies, such as boundary scan, built-in-self-test (BIST), redundancy and repair, to enable the “probably good die” era.

Live and let die
KGD became a major issue in the 1980s, when the industry began to push multi-chip modules (MCMs) in systems. In MCMs, several unpackaged dies are stacked or assembled side-by-side within a module as a means to create smaller and faster systems.

MCMs met with limited success and a plethora of startups that were pushing the technology folded in the 1980s and 1990s. “The problem (with MCMs) was the dielectrics,” recalled Richard Otte, president and chief executive of Promex Industries, an IC packaging house. “The dielectrics were crummy.”

The other problem with MCMs was (and still is) the ability to obtain KGD. For years, the industry has procured KGD or bare die for use in MCMs, RF modules and system-in-packages (SIPs). Generally, a bare die takes up less space in a system compared with a traditional packaged part. For this reason, a large percentage of RF chips are sold as bare die and then assembled in RF modules. Analog chips, discretes, memories, MCUs and passives also can be sold as bare die.

Still, IC makers prefer to sell packaged parts, which can be tested in conventional ATE to ensure their quality. Bare die are sometimes viewed as a nuisance because they require specialized testing and handling. As a result, they are sold at a premium.

Selling KGD or bare die “is something chipmakers would prefer not to do,” said Raj Pendse, vice president and chief marketing officer at STATS ChipPAC. “It’s hard to guarantee the quality of KGD. It is sometimes not possible to access all of the test vectors at the die level.”

The challenges escalate for 2.5D/3D designs. In chip stacking, the probability of obtaining KGD decreases. For example, the average yield for a memory wafer is around 50% today, said Robert Patti, chief technology officer for Tezzaron Semiconductor, a 3D DRAM supplier. For a four-layer stacked memory device, the average yield could go as low as 6%, he said, which he described as “not economically viable.”

The inadvertent use of a defective die is catastrophic in 2.5D/3D designs. It will result in yield loss. And in many cases, the entire part must be discarded.

There are other challenges, especially as chipmakers move towards heterogeneous 2.5D/3D designs. In one scenario, an IC maker may use an internal part. Then, the company obtains and integrates a separate bare die from another vendor. But if the device fails in the field, it’s unclear who will take responsibility for the faulty part.

Settling for imperfection
To attack the KGD problem, chipmakers will require breakthroughs on two basic fronts: probe cards and DFT. It also requires a different test flow. The flow for conventional packaged chips includes IC manufacturing, wafer sort, packaging and final test. Wafer sort is considered an initial screening process for packaged ICs.

In contrast, a bare die is not tested at final test using conventional ATE. Instead, a die is tested at wafer sort using a wafer prober. In this flow, chipmakers claim they can achieve a reliable KGD, but overall test costs are sometimes higher. Die failure rates are reduced, but they are never totally eliminated in wafer-level testing.

For 2.5D/3D testing, the industry is working on new probe card technology. A wafer prober is incorporated with a custom probe card, which itself has thousands of probing needles that hit the bond pads on a die. In effect, the prober detects defective die, which are eliminated.

In complex designs, the needles may miss some of the tiny bond pads on the die. The contact force of the needles also could damage the die. Concerning KGD in 2.5D/3D designs, the industry requires “improvements in fine-pitch probe technology,” said Rich Rice, senior vice president of sales for North America at Advanced Semiconductor Engineering (ASE). Specifically, the big challenge for the industry is to develop probe cards that can handle greater than 1,000 contacts and pitches below 50um, Rice said.

In probe cards, there are two basic camps. FormFactor and others are working on fine-pitch probe cards using MEMS-based technology. In another camp, IMEC and Cascade Microtech have been working on a “rocking beam interposer” (RBI) probe card technology. RBI is based on Cascade’s membrane technology. “The metal energy doesn’t bend. It rocks,” said Ken Smith, vice president of technology development at Cascade, a supplier of wafer probers and probe cards.

In RBI, the probe tips are 6um square and 15um tall. With tip forces below 1 gram-force, RBI has demonstrated 40um and below pitches with a pad damage less than 100nm deep. “This technology is still in the early stages of the development cycle,” Smith said during a recent presentation at an event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

Even with breakthroughs in probe cards, 3D test still remains a challenge. In the flow, 3D devices will require at least four more test steps: a pre-bond test before stacking; a mid-bond test in the partial stacking phase; a post-bond test after final stacking; and a final test. The interposer and TSVs may also require separate testing.

Conventional ATE cannot be used in many, or possibly any, of these steps. So test must start in the design phase with various DFT techniques. In one scenario envisioned by Mentor Graphics, boundary scan can be used to test the bottom die in a 2.5D/3D design. Embedded core test can be used to test the middle or other dies, according to Mentor.

“The bigger challenge is with stacked logic die,” said Steve Pateras, product marketing director at Mentor. “There are a number of issues there. One is the known-good die problem. How do you ensure you’re getting good die when you stack them together? With bare logic die, particularly with heterogeneous parts, the quality of those parts comes into question.”

For years, memory makers have made use of BIST, repair and redundancy in their 2D designs, which may translate in the 2.5D/3D world. “With memory it’s easier, because there’s a robust testing methodology for bare memory die. The JEDEC memories have scan chains in them, which is one way of testing the memories and the SoC. You can use memory BIST,” Pateras said.

Using such techniques, 3D DRAM maker Tezzaron claims to have obtained better yields in 3D over 2D. “You have to change the way you think about design,” said Tezzaron’s Patti. “The secret to KGD is design-for-repair.”

Tezzaron refers to its design-for-repair and BIST solution as “BiSTAR.” Designed to repair bad memory cells and ensure a known good memory stack, BiSTAR includes 256 BIST sequencers, which run independently in parallel.

Besides repair and BIST, Patti said the industry must rethink its definition of KGD and may need to settle for something less. “Will we ever have 100% perfect KGD? It’s probably not practical,” he said. “A ‘kind of a good die’ may be acceptable. We may also have to accept the idea of having ‘not bad die.’”

By Mark LaPedus
For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence.

The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skipping” in the fabless-foundry world could reach new heights.

Two foundry vendors, GlobalFoundries and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), recently accelerated their respective 14nm-class finFET shipment schedules by a year or so. In effect, the companies have shrunk the process cadence between their planar 20nm and 3D-like finFET technologies to roughly a year.

Samsung is expected to follow a similar path. In many respects, the foundries appear to be luring customers into making the giant leap from 28nm (or above) processes to finFETs, thereby skipping 20nm. The reason is largely due to lackluster demand for 20nm planar, and they are aggressively marketing their finFET technologies right now.

Rival United Microelectronics Corp. (UMC) has a different strategy. UMC will move directly from 28nm planar to 14nm-class finFETs, bypassing the 20nm planar node. UMC recently licensed finFET technology from IBM, but it will stick with bulk CMOS. For its part, IBM will ramp up finFETs using silicon-on-insulator (SOI) technology.

The foundries are speeding up their finFET efforts for several reasons. First, there is a perception that the foundries are falling further behind Intel. The chip giant rolled out finFETs at 22nm and is offering the technology to select foundry customers. Intel plans to begin ramping up its 14nm finFET process by the fourth quarter of 2013.

Some chipmakers have been openly critical about the 20nm foundry planar process, saying the technology puts the industry behind the traditional performance curve. “I know some customers want more,” acknowledged Morris Chang, chairman and chief executive of TSMC, in a recent conference call.

So, at 20nm and beyond, chipmakers are weighing their options and exploring the trade-offs. “There will be customers that will skip 20nm to get to (finFETs),” Chang said. “I think there will be customers that will be light on one (process technology) and heavy on another.”

The benefits of finFETs are clear, but the industry is finally coming to grips with the challenges associated with the transistor technology. Cost, patterning and variation are just a few of the issues. The complexity will require more and deeper collaboration between foundries and their customers. “The challenge for us is to work across the ecosystem with our partners and have earlier tapeouts that are fully debugged and tested,” said Gregg Bartlett, senior vice president and chief technology officer at GlobalFoundries.

All told, the fabless-foundry model is still alive and well, but the business continues to change. Going forward, leading-edge foundries will offer fewer process derivatives. Customers will have fewer choices. And in the future, expect possibly one foundry to exit from the leading-edge process race, with more consolidation seen on the horizon.

Skipping around the IC world
At one time, most leading-edge chipmakers followed the natural progression of process technology nodes. The dynamics began to change starting around the 90nm node, when chipmakers migrated towards sub-wavelength lithography, low-k, design-for-manufacturing (DFM) and other technologies.

IC design and manufacturing costs began to soar. As the complexity and cost escalated at each process node, it was no longer a clear-cut decision to follow the natural cadence of process nodes. Chipmakers weighed the various technical and economic trade-offs.

Starting at 90nm, node skipping among chipmakers became the rule instead of the exception. For example, Netronome is currently shipping communications processors based on a 65nm process from TSMC. Instead of moving to 40nm or 28nm, Netronome recently decided to make a giant leap from 65nm to Intel’s 22nm finFET foundry technology. The decision, according to Netronome, was based on density, power consumption and cost.

Node skipping is expected to reach new heights at the 20nm planar process. The so-called “time-to-market” IC makers, such as AMD, Altera, Nvidia, Qualcomm, Samsung, and Xilinx, likely will make the traditional progression from 28nm to the 20nm planar node before moving to finFETs.

Many of the so-called fast-followers, such as Broadcom, Freescale, Marvell and LSI, are still on the fence. At a recent event, for example, a Marvell representative questioned the feasibility of the 20nm planar node, saying the technology has a “negative ROI.”

Previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process, thereby providing customers with fewer choices.

The 20nm planar node also brings some new and challenging technologies to the mix, such as double patterning and the introduction of a third layer of local interconnects called the middle-of-the-line. At 20nm planar, there is a performance boost over 28nm, but the transistor speeds slow down as operating voltage is reduced.

IC makers that moved from 40nm to 28nm have experienced a 35% average increase in speed and a 40% power reduction, said Jack Sun, vice president of R&D and chief technology officer at TSMC. In comparison, IC vendors that will move from 28nm to 20nm planar are expected to see a 15% increase in speed and 20% less power, Sun said.

With that in mind, there is a temptation to skip 20nm and migrate to finFETs. FinFETs take the traditional 2D planar design and turn the conductive channel on its side, resulting in a 3D “fin” structure surrounded by a gate that controls the flow of current.

Compared to 32nm planar, finFET transistors enable a 37% performance increase at low voltages and a power reduction of 50% or more, according to Intel. Intel’s own Tri-Gate transistor enables a steeper sub-threshold slope at around 80 mV/decade or below, compared to 100 mV/decade for leading-edge planar transistors, said Mark Bohr, senior fellow at Intel, at a recent event.

“Vdd scaling has slowed down. Leakage is an issue as geometries shrink,” said Srinivas Nori, director of SoC marketing at GlobalFoundries. “The value (that finFETs) bring is that it enables one to lower the Vdd. Leakage is better controlled. The variation of the Vt is also much better controlled.”

The benefits are easy to grasp, but the hard part is obvious. “If I was a designer, I would be worried,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that is promoting SOI. “If you go back to the standard way of doing things in bulk, and you want a transistor with a different Vt and that drives a different current, you printed different line widths. You just made a fatter transistor. And you paid a little a bit of a penalty in the capacitance,” Mendez said. “How the heck can do you that in finFETs? It’s impossible. So, to make finFETs, you go in quantum steps. The way you actually do this is that you put down one fin, two fins or three fins on a structure.”

Besides the quantum issues, there are other problems. “The fin height is now a huge variable. In a junction-isolated fin, I don’t know how that is accurately controlled. So, from my perspective, this is a tricky thing for an SoC guy to get around. I would imagine you would need pretty stiff design rules to account for this,” he said.

Because of fin height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. The SOI proponents are pushing fully-depleted SOI (FD-SOI), claiming the technology can reduce the process steps and variability with little or no cost penalty.

New roadmaps
The foundries are still pushing bulk, but they have changed their roadmaps. In September, GlobalFoundries rolled out its finFET technology, dubbed 14nm-XM, based on a “modular fin” approach. GlobalFoundries opted to marry a 14nm front-end fin with a 20nm planar BEOL flow. In doing so, the company has accelerated its finFET process by a year. Product tape-outs are expected in 2013, with production slated for 2014.

“Today, customers, IP vendors and the whole ecosystem can actually start working on finFETs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “There are about 7,000 design rules that will carry over from 20nm planar to finFET. From a design point of view, the very early PDKs are almost the same as 20nm.”

Earlier this year, TSMC thought 20nm planar would become a popular node and announced a 20nm pilot line to prepare for the big ramp. But initial 20nm demand is lukewarm. TSMC claims to have 50 tape-outs for the technology, roughly one-fifth compared to that of 28nm.

TSMC’s 20nm pilot line is still on track for 2013. But last month TSMC accelerated its finFET risk production schedule from February 2014 to November 2013. Mass production is slated a year after its 20nm planar process. “This is a somewhat faster cadence than the previous generation,” TSMC’s Chang said.

Meanwhile, UMC said it has developed 20nm planar capability, but the company is not pursuing it as a mainstream process offering. Instead, it is more or less skipping 20nm and pursing finFETs. “After 28nm, finFET will be our focus,” said Shih-Wei Sun, chief executive of UMC, during a recent conference call.

Three pure-play foundries, TSMC, GlobalFoundries and UMC, are expected to be in the top 20 rankings of leading semiconductor suppliers in 2012, according to IC Insights.

In the rankings, Intel is projected to remain in first place in terms of sales in 2012, followed in order by Samsung, TSMC, Qualcomm, TI, Toshiba, Renesas, SK Hynix, Micron, and ST.

The only expected movement with regard to the top 5 spots in the 2012 ranking is that fabless supplier Qualcomm is forecast to register a 30% surge in sales this year and move up three positions to replace TI as the fourth largest semiconductor supplier, according to the firm.

As a result of its performance this year, GlobalFoundries is forecast to replace Elpida and move into the top 20 ranking for the first time, rising from the 21st spot in 2011 to 15th place in 2012, according to the firm. UMC will remain in 20th place. Sales from pure-play foundry GlobalFoundries are forecast to jump by 31% while foundry giant TSMC is expected to show a 17% increase this year, according to IC Insights.

Combined, these three foundries are forecast to log a 16% increase in 2012/2011 sales, quite impressive considering the expected 2% decline in the worldwide semiconductor market this year, according to the firm.

The continued success of the fabless/foundry business model is evident when examining the top 20 semiconductor suppliers ranked by growth rate. The top five performers are expected to include three fabless companies, Qualcomm, Nvidia, and Broadcom, and two pure-play foundries, GlobalFoundries and TSMC, according to the firm.

Illustrating the difficult year faced by the majority of the top 20 semiconductor suppliers, 12 of the top 20 ranked companies are forecast to register a sales decline this year, including 7 of the top 10 largest semiconductor suppliers in the world (#1 Intel, #2 Samsung, #4 TI, #6 Toshiba, #7 Renesas, #8 SK Hynix, and #10 ST).

By Mark LaPedus
As chipmakers move toward 20nm designs, finFETs and 3D stacked devices, the industry is beginning to re-think the fabless-foundry model.

Leading-edge foundries are finally getting serious about the “virtual IDM” model, in which vendors will act more like integrated device manufacturers (IDMs), as opposed to being mere production partners. In this model, the foundries are not only manufacturing partners, but there is a deeper collaboration within a customer’s design team.

In fact, given the variability challenges with finFETs, there is a school of thought that chipmakers must reside at the same physical location as their foundry partners’ fabs to ensure that design and manufacturing are on the same page. Otherwise, according to some experts, the chances for first-silicon success are shaky.

For this reason and others, Taiwan Semiconductor Manufacturing Co. (TSMC) may take the “virtual IDM” model a step further. TSMC is considering a plan to build separate fabs for individual companies. And as part of its strategy, TSMC has accelerated its finFET roadmap.

Rival GlobalFoundries is considering a plan to offer dedicated modules within a fab for customers. And taking another approach, United Microelectronics Corp. has floated an equity placement under which companies can buy a 10% stake in UMC. UMC also has licensed IBM’s 20nm and finFET technologies.

Another foundry vendor, Samsung Electronics Co, has perhaps set the tone for the industry: It has already built a dedicated fab for Apple. And separately, in a surprise move, fabless chipmaker Qualcomm is considering the idea of building its own fab to gain better control of the manufacturing process.

Qualcomm CEO “Paul Jacobs has discussed it openly of late,” said G. Dan Hutcheson, president of VLSI Research. “Qualcomm certainly has the revenues to build its own fab and start making its own wafers. The chance of success is still low. It would cost at least three times, and possibly as much as five times, to successfully get your first fab to viable production, or approximately $15 billion to $25 billion. In other words, it would be an out-of-body experience for the management team that tries it.”

Sea of change
In any case, there could be a sea of change taking place in the traditional fabless-foundry model. “The traditional foundry model, where you throw a GDS2 file over the wall, no longer works,” said Mojy Chian, senior vice president of design enablement at GlobalFoundries. “We have to work closer with the fabless guys. New challenges at 20nm and beyond will require deep, IDM-like collaboration to accelerate the time-to-market. In fact, the collaboration should start two to two-and-a-half years ahead of tape out.”

In the late 1980s, the pure-play foundries emerged, which spawned a plethora of fabless companies. One of the drawbacks with the fabless-foundry model is that the design houses and foundries sometimes work in silos and do not cooperate. In some cases, fabless vendors will throw a clunky design “over the wall” to the foundries, which are still expected to make the chip on time. This brute-force methodology has experienced mixed success.

The fabless and foundry firms began to change their ways at the 130nm node amid soaring IC design and manufacturing costs. “130nm is when process and design began to be recoupled. The result was the rise of DFM, which didn’t exist before then,” said VLSI’s Hutcheson.

Then, starting in the early part of this decade, several foundries billed themselves as “virtual IDMs,” claiming they would work more closely with customers. But some of those efforts have fallen short of expectations. “The leading fabless suppliers got hurt badly when the leading foundries hadn’t dealt well with variability at 40nm, and more recently, with design-manufacturing interactive yield losses at 28nm,” Hutcheson said.

Now, as the IC industry moves toward the 20nm node and beyond, the foundries have become more serious about embracing the “virtual IDM” model and for good reason: The stakes are higher. At 130nm, a fab was $1.45 billion, process R&D costs were $250 million, and design costs were $15 million. But at 22nm, a fab runs $6.7 billion, process R&D is $1.3 billion, and design costs are $150 million.

Simply put, the traditional foundry model must evolve. “You can’t do it in silos,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “The key is to have a tighter integration between product design and manufacturing.”

This is especially true in the finFET era. Intel has moved finFETs into production at 22nm. Given the variability issues, the foundries face challenges to put finFETs into production at 14nm.

Intel and the foundries are in the bulk finFET camp. But to make the finFET transition easier, the foundries should look at silicon-on-insulator (SOI) technology, said Chenming Calvin Hu, professor of electrical engineering at the University of California at Berkeley. “We are going to see (both bulk and SOI finFETs) in volume manufacturing,” Hu said. “[SOI] is easier. The supply chain is the one thing that manufacturers need to be assured of.”

New business models
On the business side, the industry could take one of two routes: Maintain the fabless-foundry status quo or move toward a “virtual IDM” model. Morris Chang, chairman and chief executive of TSMC, sees yet another model: Build dedicated fabs or joint-venture fabs for larger customers.

“We made our mark serving many customers (in multiple fabs). We will retain that capability,” Chang said during a recent conference call. “There are going to be larger customers. So it makes complete sense to have one dedicated fab, or more than one fab, for one customer.”

GlobalFoundries, meanwhile, is considering a slightly different model. “This is hypothetical,” said GlobalFoundries’ Kengeri. “Within a fab, we have modules. If one of our customers wants a dedicated module, it’s open for discussion.”

In that arrangement, a chipmaker may have to share the risk and cost. And it must make economic sense. Clearly, though, Apple is one candidate for a dedicated fab. In fact, Samsung already has built a dedicated fab for Apple in Austin, Texas.

Altera, Broadcom, Nvidia, Qualcomm and Xilinx are also possible candidates to occupy part or all of a fab. Qualcomm, for one, has the volumes and already is sourcing parts from all of the leading-edge foundries to keep up with 28nm demand.

Qualcomm’s multi-foundry sourcing strategy “is a very expensive approach today, as designs don’t port to multiple foundries like they used to,” said VLSI’s Hutcheson. “Yields are far more difficult to obtain at these advanced nodes, and splitting production across multiple fabs means either less relevant data per learning cycle or longer learning cycle times. That results in longer time-to-money and higher costs, making going the IDM route seem more attractive.”

It’s unlikely that Qualcomm will build its own fab, but it is possible it will end up with a joint venture fab with a foundry. In addition, Qualcomm and others would like the foundries to speed up their process roadmaps. The foundries are falling behind Intel, which also offers foundry services on a limited basis.

TSMC, for one, plans to accelerate its finFET efforts. Originally, TSMC planned to introduce finFETs at 14nm by late 2014. Now, the company has no plans to brand its finFETs at 14nm, but rather it will introduce the technology at 16nm. TSMC’s finFET “risk production” is slated for the end of 2013 or early 2014, with production scheduled for the second half of 2015, Chang said.

TSMC is not banking on extreme ultraviolet (EUV) lithography for 16nm. “We are very confident we can make 16nm finFETs without EUV,” he said. “I think EUV will come in at 10nm.”

To accelerate 450mm fabs and EUV in the market, Intel recently inked a deal with ASML. ASML has also enabled customers to take a 25% stake in the company. Intel plans to acquire up to a 15% stake in ASML.

TSMC and Samsung are also negotiating with ASML to take separate stakes in ASML. Taking a page from the ASML-Intel deal, UMC separately floated private equity shares under which strategic partners can take up to a 10% stake in UMC.

This represents a change for UMC. The company has developed its own processes and has shied away from forming strategic alliances. UMC has controlled its own destiny, but it also has fallen behind its rivals.

To jumpstart its process roadmap, UMC recently licensed 20nm and finFET technology from IBM. UMC’s finFET technology is reportedly a 14nm or 16nm front-end, with 20nm backend. “For UMC to do a finFET from scratch is very challenging,” said Shih-Wei Sun, chief executive of UMC, in a recent conference call. “This will kick start our finFET efforts.”

GlobalFoundries and Samsung have yet to change their finFET strategies. GlobalFoundries still plans to roll out a finFET at the 14nm node in the fourth quarter of 2014 or first quarter of 2015, according to Kengeri.

By Mark LaPedus

Hoping to play catch-up in the process race amid Intel Corp.’s finFET ramp at the 22nm node, Nvidia, Qualcomm and other leading-edge fabless chip makers are ringing the alarm bells and taking a drastic step: They are nudging their foundry partners to accelerate their respective finFET production schedules.

Nvidia Corp., for example, wants finFETs sooner than later. The graphics chip maker said it is in talks with its foundry vendor — reportedly Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) — to accelerate its finFET production schedule. Nvidia hopes its foundry partner will offer finFETs before its stated plans at the 14nm node. “We have to figure out a way to pull that in,” said Sameer Halepete, vice president of VLSI engineering at Nvidia, at the Mentor Graphics User Group Meeting in Santa Clara, Calif.

In one possible scenario, the leading-edge foundries could pull in or speed up their finFET schedules, and may offer the advanced transistor technology at a “half-node somewhere between 22nm and 14nm,” said Walden Rhines, chairman and CEO of Mentor Graphics Corp., in an interview at the same event.

It’s unclear if the foundries will accelerate their finFET schedule — yet. At a recent event, the Common Platform members — IBM, GlobalFoundries and Samsung — all said they would put finFETs in production at the 14nm node.

For some time, rival TSMC has been mulling plans to alter its finFET schedule. TSMC, which will host its annual technology event in San Jose, Calif. next week, will shortly make at least one big announcement. It is expected to raise its capital spending from $6 billion to $7 billion in 2012, which is still roughly flat over 2011, according to Barclays Capital.

Broken model?

In any case, there are some cracks appearing in the delicate fabless-foundry model. “Is the fabless-foundry model broken? We keep getting asked if silicon production by node is slowing. The answer is that it is not for the memory and processor IDMs, but definitely for the foundries,” said G. Dan Hutcheson, president of VLSI Research Inc.

“The fabless companies at the leading edge, such as Nvidia and Qualcomm, are visibly concerned about their foundries’ ability to keep up with Moore’s Law,” he said. “To stay in the game, they need a steady decline in cost-per-transistor.”

For years, Intel Corp. has been the clear leader in terms of logic process technology — and by a wide margin. But in more recent times, the foundries began to invest more in technology, with hopes to close the process technology gap with Intel. And at one time, the leading-edge foundries claimed to be only a process node or so behind mighty Intel, enabling the fabless community and integrate device manufacturers (IDMs) to gain access to leading-edge process technology.

More recently, Intel has taken what could be an insurmountable lead in process technology. At present, Intel is ramping up its 22nm process based on advanced finFET transistors, giving the chip giant a leg-up on its microprocessor and graphics processor rivals. Intel is also taking some major steps in the foundry business. To date, the company has announced three foundry customers, which will leverage Intel’s new finFET transistor structures at 22nm to give them a perceived jump on their rivals.

Meanwhile, GlobalFoundries, Samsung, TSMC and UMC  are currently ramping 28nm technology. Both the 28nm and 22nm process technologies from the foundries are planar transistor structures. In their latest roadmaps, the leading-edge foundries will not migrate to more advanced finFETs structures until the 14nm node in 2014 or 2015, meaning the foundries — and their customers — appear to be roughly two to three years behind Intel in the finFET race.

GlobalFoundries plans to have test chips at 14nm in late 2014, said Michael Noonen, senior vice president of worldwide sales and marketing for the foundry vendor. The devices will be built within its new 300mm fab in New York, he said in a recent interview.

The 1 trillion transistor SOC

Meanwhile, in his keynote at the Mentor’s event, entitled “Superphones to Supercomputers: The quest for a trillion transistor SOC,” Nvidia’s Halepete echoed VLSI Research’s assertions that the industry faces challenges to maintain the cost-per-transistor curve.

Nvidia’s current 40nm GPU is a 3.2 billion transistor device. In the keynote, Halepete said the 1 trillion transistor SOC envisioned by Nvidia would likely appear by the end of this decade. The proposed SOC from Nvidia, which is just a concept right now, would likely be based on an 8nm process using finFETS and 450mm wafers.

But even before Nvidia embarks on this ambitious SOC, the company currently faces challenges to migrate from the 28nm to 20nm nodes. One of the challenges is what he called “time-to-tapeout,” in which there are more process steps in the fab at each process node. As a result, the ability to obtain first silicon takes four to six weeks longer than previous nodes, causing challenges in terms of time-to-market. Other scaling issues include power management and defectivity, he added.

In an interview after the presentation, Halepete said Nvidia would like to “pull in” and implement finFET structures at the 20nm node — rather than 14nm. He said that the foundry partners have yet to alter their finFET roadmaps, meaning that Nvidia has no other choice but to design products on planar structures at 20nm — at least for now.

Others believe the foundry finFET roadmap is fluid. Chip makers that use foundry services may have to make do with planar structures at the 20nm. “20nm is here,” said Mentor’s Rhines in an interview. “20nm is largely developed.”

At or around 14nm, there are several scenarios. Chip makers that use the foundries “all agree they want finFETs at 14nm,” Rhines said. At 14nm, chip makers would like to insert extreme ultraviolet (EUV) lithography in the production flow. But if EUV slips, Rhines sees a scenario — and perhaps a strong chance — that the foundries would devise a half-node at 18nm.

In this case, there is a strong possibility that the foundries would accelerate the finFET schedules and roll out finFET technology “somewhere between 22nm and 14nm” – possibly at 18nm, he said.

Besides the move to finFETs, Rhines said he is seeing some intriguing dynamics at the current 28nm node. In recent times, the foundries have put in an “enormous investment” at the 32nm/28nm node, he said.

In fact, some 18.6 percent of the world’s silicon capacity revolves around the 32nm/28nm node right now, but the revenues do not reflect this percentage. This implies there are still yield issues at the node, meaning there is a major upside when the foundries resolve the problems, he said. Once the “yields catch up,” he said, “32/28nm is going to be a huge node.”

To solve the issue, TSMC is expected to raise its capital spending. The company is expected to use the capex to “add 28nm capacity” and “speed up the yield improvement on existing 28nm capacity,” said C. J. Muse, an analyst with Barclays Capital.

“For Samsung, we expect the company will convert capacity in Austin from NAND to system LSI for Qualcomm’s 28nm business,” Muse said. “We expect Samsung’s budget to rise, but likely more modestly than the TSMC increase.”

For GlobalFoundries, “we still look for a 30-plus percent downtick in spending in 2012, though we’d note that our recent checks suggest that the company is pulling in some equipment for the Dresden fab, including about three immersion tools,” he said. “This suggests potential for modest upside to our $3.4 billion capex estimate for 2012.”

UMC’s capital spending sits on $2 billion in 2012. “If UMC is able to improve on their polysilicon process, the foundry may be able to win some low-end 28nm wireless business, particularly from customers who continue to be excluded from TSMC’s limited 28nm capacity allocation,” he said.

By Mark LaPedus

The shift towards a new class of exascale computers will require new breakthroughs in power management and chip-level technologies like memories, according to a technologist at an event last week sponsored by the IEEE San Francisco Bay Area Nanotechnology Council.

A number of entities are racing each other to develop exascale systems, which are supercomputers that are targeted to run faster than a petaflop — or one quadrillion floating point operations per second. Targeted by 2018 or so, exascale computers would operate at 10¹8 flops and would be used for climate modeling, defense, Internet searching, medicine, physics and other applications.

“The biggest challenge (for exascale computing) is energy and power,” said Matthew Marinella, a senior technical staff member of Sandia National Laboratories, during a presentation at the IEEE event, entitled “Emerging Non-Volatile Memory Technologies. “The next challenge is memory and storage.”

Sandia is developing an exascale system as part of a DARPA program. In the short term, the lab has found a memory solution for an exascale system: Micron Technology Inc.’s Hybrid Memory Cube (HMC). Long term, Sandia is looking at a storage-class memory architecture based on resistive RAMs (ReRAMs).

One of Sandia’s ReRAM candidates is based on the memristor from Hewlett-Packard Co.  Memristor-based ReRAMs could be out sooner than later. “We have a significant commercialization effort going on,” said R. Stanley Williams, senior HP fellow and director of quantum science research at HP Labs, during a presentation at the IEEE event, located in Santa Clara, Calif.

At the IEEE event, several other entities also presented details about various next-generation memory technologies, including IBM Corp. and its racetrack memory.

Supercomputer race

For years, there has been an intense competition among nations in the supercomputer field. The U.S. and Japan dominated the field until 2010, when the National Supercomputing Center in Tianjin, China stunned the industry and rolled out the world’s fastest supercomputer: the Tianhe-1A.  Built around graphics processor units (GPUs) from Nvidia Inc.,  the Tianhe-1A is one of the few petascale-class supercomputers in the world.

K computer installed in a room (Source: Fujitsu)

Then, in June of 2011, Japan’s Fujitsu Ltd. took the lead by rolling out the K computer. Based on 705,024 Sparc64 processor cores, the K system became the first computer to top 10 petaflops. At present, the United States is in third place with Jaguar, a supercomputer built by Cray Inc. Based on 224,162 Opteron cores, Jaguar has a peak performance of just over 1.75 petaflops.

Seeking to leapfrog one another, various entities are building exascale systems. In one effort in the United States, Sandia National Laboratories in 2010 was selected as one of four institutions to develop new exascale prototype systems for the Defense Advanced Research Projects Agency (DARPA). As part of a $100 million effort, DARPA also launched the Ubiquitous High Performance Computing (UHPC) program.  Intel, Nvidia and Massachusetts Institute of Technology Computer Science and Artificial Intelligence Laboratory are also part of the group.

Sandia, which expects its prototype to be completed by 2018, is a government-owned/contractor operated (GOCO) facility. Sandia Corp., a Lockheed Martin company, manages Sandia for the U.S. Department of Energy’s National Nuclear Security Administration.

There are various roadblocks in developing an exascale system. Power management, software programming, processing power, memory bandwidth and storage are just are a few of the challenges.

Power management is a central issue in supercomputing. For example, IBM’s Roadrunner supercomputer, the first supercomputer to break one petaflop in performance in 2008, runs at 7 megawatts. This is the equivalent energy to power 5,000 homes, Marinella said.

On the memory side, there is a crying need for a new technology in supercomputing. Social networking startup Facebook sees a similar need for its datacenters. DRAMs are cheap, but they are power-hungry devices that are becoming difficult to scale.  “DRAM per flop is going down,” Marinella said during the presentation.

Hybrid Memory Cube (HMC). (Source: Micron Technology)

For its exascale project, Sandia is initially looking to use Micron’s HMC, he said.  Rolled out last year, HMC is a 3D device that will incorporate DRAM arrays stacked on a logic chip. The device is connected with 2,000 to 3,000 through-silicon vias (TSVs).

To speed up the HMC, Sandia is looking to use optical interconnects. By 2020, Sandia is also proposing the idea of developing what it calls a “Universal Memory Logic Cube.”  Based on optical interconnects, ReRAM and possibility a system-on-a-chip, the stacked device is basically an “entire supercomputer on a chip,” Marinella said.

One of the ReRAM candidates for this device is HP’s memristor. On a slide, both HP and Sandia showed a “4D address architecture” based on the memristor. The memristor, short for “memory resistor,” was postulated to be the fourth basic circuit element by Leon Chua of the University of California at Berkeley in 1971.

A memristor is a passive two-terminal electronic device. In memristance, if the flow of a charge is stopped by turning off the applied voltage, this component will “remember” the last resistance that it had, according to HP. HP hopes to commercialize the memristor in the form of a ReRAM. Besides supercomputing, HP and its co-development partner, South Korean memory maker SK Hynix, are looking at several current applications such as storage.

Source: HP

During an interview after his presentation at the IEEE event, Williams said the memristor-based ReRAM is making progress. “We are clearly on a path towards viability,” he said, without elaborating on the details of the proposed ReRAM or 4D architecture.

Like all presenters at the event, Williams said there is a need for a new memory type. DRAMs are running out of gas and floating-gate flash could hit the wall at 14nm.

The new memory types include ReRAMs, MRAMs, phase-change memories, among others. But the trouble is that the newfangled memory types are difficult to scale and make. And if or when these newfangled memories reach production, these devises may not create new markets, but rather they could cannibalize existing markets.

For this reason and others, vendors could potentially delay the introduction or slow the development of these new memory types. “The business issues are trumping the technical issues,” Williams said.

During a separate presentation, Yiming Huai, vice president of technology at Avalanche Technology Inc.,  said he believes the next-generation memory types will be required sooner than later. Current memory types like NAND suffer from endurance and reliability issues. “Existing memories face increasing challenges beyond 32nm,” he said.

He also disclosed more details about Avalanche’s technology, a spin-torque MRAM. Dubbed AvRAM, Avalanche’s technology is going after the embedded market. The startup has developed a 64-Mbit device based on 65nm technology.

In another presentation, IBM discussed its previously-announced  Racetrack memory, which moves data by sliding magnetic bits back and forth along nanowire “racetracks.” Last year, IBM claimed to have measured the time and distance of domain wall acceleration and deceleration in response to electric current pulses. More recently, the company has demonstrated 256-cell, 8 x 32 nanowire device based on a 90nm process, said Stuart Parkin, an IBM fellow at IBM Research in Almaden, during the presentation.

By David Lammers and Mark LaPedus

Capacity demand is heating up as the leading foundries continue to struggle with ”poor yields” at the 28nm node, according to a new report from VLSI Research Inc.

“We’ve heard that TSMC is fully booked into the second quarter,” according to the report. “In general, from a foundry order perspective, capacity demand is filling out for the second quarter.”

But amid strong and sudden demand, the yields are still relatively low at the leading-edge 28nm node. Foundry vendors are struggling to ramp up their high-k/metal-gate and non-high-k technologies at 28nm, where demand is soaring. This has been an ongoing problem for some time and the issues continue.

The foundries in general have “major yield problems in ramping 28nm HKMG (high-k/metal-gate),” said Handel Jones, an analyst with International Business Strategies Inc. (IBS), a research firm. The “problems are DFM-related: physical design, reticles, and process parameters variations.”

“This is hitting some fabless companies hard,” according to VLSI Research. “Nvida is having issues with getting enough GPUs to the degree that it has been reported that Apple is shifting to use more of Intel’s integrated graphics for their low-end and mid-range models of MacBook. Apple itself has had issues getting its advanced A-series out.”

The report is referring to Apple’s A6 processor, which is made on a foundry basis by Samsung Electronics Co. Ltd. TSMC is the foundry for Nvidia, Qualcomm and others.

“We’ve also heard that AMD and Qualcomm may be having 28nm yield struggles as well. While the revenue ramp for 28nm has been painfully slow for the foundries, they need more equipment to keep up with demand,” according to the report. “While they haven’t raised capex plans recently, they are front loading their buying into the first half as a result.”

In response, a spokeswoman from TSMC said: “We are working very hard to improve our 28nm yields, and the prospect looks good. Regarding demand/supply for 28nm, yes, we are very tight, and are
also trying our best to bring up more capacity to ease the tightness somewhat.”

Responding to the reports, a spokeswoman for Samsung said: “As you know, we don’t comment on customer engagements. I can confirm that we are not experiencing any problems with our 32/28 nanometer technologies. Both are on track with no delays.”

Samsung is also reportedly struggling with its yields for its 21nm NAND products, according to VLSI Research. In response, a spokesman for Samsung said: “As the international leader in NAND solutions, Samsung is experiencing continued strong growth in demand for all of our advanced NAND, which support many high performance applications . In meeting this demand, we are not experiencing issues that impact our operations.”

There could be more trouble ahead on the foundry front. GlobalFoundries, Samsung and TSMC are moving full speed ahead in developing 20nm technology, based on a planar process. “22/20nm planar CMOS will have a range of technology challenges,” said IBS’ Jones. “20nm planar technology will be more difficult to optimize the parametric yields than 28nm, due to leakage-related DFM problems. It requires a very tight control over process parameters and close link with design flows.”

By Mark LaPedus, SemiMD senior editor

For some time, Intel Corp.’s dominance in the x86-based microprocessor market has been under siege on two and fast-growing fronts: smartphones and tablets.

Intel has attempted to fend off the challenge — mainly from the ARM processor camp — but the chip giant has little to show for its mobile and tablet efforts and is still losing ground in the arena. Much to Intel’s chagrin, ARM’s technology continues to dominate the processor sockets within smartphones and tablets.

ARM could expand its thrust in both the mobile — and desktop — space this year, as its technology is being ported to Microsoft’s Windows 8 operating system. Due out in the second half of 2012, Windows 8 is the first PC operating system to support ARM. Nvidia, Qualcomm and others are pushing Windows-based ARM processors for PCs.

So, as its core PC market continues to slow, Intel faces mounting pressure to gain some traction in the smartphone and tablet chip markets. After several false starts in the arena, Intel has recently rolled out a new set of initiatives, products and processes. As reported, seeking to fend off AMD, ARM and others, Intel recently rolled out a 22nm process based on a tri-gate transistor technology.

Still, the question is clear: Can Intel finally succeed on the mobile/tablet chip front? Analysts are mixed. Most are skeptical about Intel’s new cell-phone chip efforts, but they are bullish about its response against tablets.

New mobile push

In recent times, Intel has aggressively moved on the mobile front. To re-enter the cell-phone chipset or baseband market, Intel in 2010 acquired Infineon Technologies AG’s Wireless Solutions Business for $1.4 billion. In a separate effort, Intel also hopes to fend off competitive pressure in the tablet PC market with its so-called UltraBook initiative. UltraBooks are said to be smaller and lighter notebook PCs.

At the Consumer Electronics Show (CES) in Las Vegas this week, Intel took other major steps in the segments. Intel and Google Inc.’s Motorola Mobility unit announced that the two companies were entering into a multi-year, multi-device strategic relationship. The deal includes smartphones in which Motorola will begin shipping later this year using Intel’s Atom processors and the Android platform.

Intel also announced a similar deal with China’s Lenovo, which is fielding smartphones. The smartphones will be based on the Atom processor Z2460 platform, formerly called “Medfield,” which is an x86-based application processor designed for smartphones and tablets. It competes against similar products based on ARM’s processor technology.

“Our efforts with Lenovo and Motorola Mobility will help to establish Intel processors in smartphones and provide a solid foundation from which to build in 2012 and into the future,” said Intel President and CEO Paul Otellini at CES.

On another front, Intel at CES demonstrated a prototype ultrabook, dubbed Nikiski, which features a transparent touch pad panel allowing tablet-style operation. This represents the first wave of tablet-style ultrabooks designed to fend off Apple Inc.’s iPad and other competing devices.

Intel claims that a total of more than 75 ultrabook systems are expected to ship this year from industry partners. Asus, Acer and a few other OEMS have announced ultrabook systems thus far. At CES, Dell showed its first ultrabook, based on Intel’s Core i7 processor. Scheduled for February availability, the system weighs 2.99 pounds and provides up to 8 hours of battery life.

Intel will further accelerate ultrabook innovation in 2012 with third-generation Intel Core processors, codenamed “Ivy Bridge,” based on a 22nm process and its tri-gate transistor technology.

The great debate

Analysts were mixed about Intel’s efforts. “We do see incrementally positive comments on ultrabooks as well as demo smartphones using Medfield that should come to market in 2Q12. But we think this is more of a 2013 story for Intel,” said C.J. Muse, an analyst at Barclays Capital.

Hans Mosesmann, an analyst with Raymond James, said: “Intel is having a solid CES with what appears to be some traction (finally) with ultrabooks. Smartphones remain a mixed bag with Intel only showing off a Medfield Atom reference design. While traction in mobile is a key concern for investors given the current dominance by ARM in this market, we suspect that the news was likely expected and will do little to answer mobility questions in the near-term.”

Auguste Gus Richard, an analyst at Piper Jaffray & Co., agreed: “Intel will claim Medfield is a significant product introduction for mobile and Qualcomm will expect Windows 8 to drive ARM processors into PCs. We predict neither will happen in (calendar 2012). Windows 8 is likely late and we think Medfield phones are unlikely to gain traction. We expect the status quo will remain for microprocessors in phones and PCs for the most part in CY12 with only very minor incursions. We expect tablets to remain primarily ARM-based and cannibalize PCs.”

Regarding the ultrabook, Richard is also bearish. “Intel’s response to tablets is the ultrabook, or a PC version of a MacBook Air. While this may breathe some life into notebooks, the first generation of ultrabooks is not in our view going to slow the momentum of tablets. Initially, ultrabooks will be expensive and have a relatively short battery life relative to tablets. We continue to expect tablet growth to come at the expense of notebooks in CY12,” he said.

Others, however, are bullish about ultrabooks. Ultrabooks represent the fastest-growing segment of the global PC market, according to IHS iSuppli. The research firm predicts global ultrabook shipments will soar to 29 million units in 2012, up from less than 1 million in 2011. By 2015, shipments will soar to 136 million and will represent 43 percent of global notebook PC shipments, up from 2 percent in 2011 and 13 percent in 2012.

“The Nikiski and similar hybrid products will help the PC market fight back against the media tablet onslaught,” said Matthew Wilkins, principal analyst for compute platforms research at IHS. “Consumers clearly love the convenience and ease of use of the tablet. So to offer a very thin-form-factor device that can be used as a tablet as well as a notebook represents a much more competitive proposition for PC makers.”

Despite saying that ultrabooks remain a 2013 story, Barclays’ Muse agreed: “The ultrabook concept appears to be well-received with almost every major PC vendor eager to jump on the ultrabook bandwagon in order to compete against tablets, which are becoming increasingly laptop-like, sporting multi-core processors and keyboard docks.

“As for overall impact to PC demand, while we remain bullish on the outlook for ultrabook adoption with the expectation that ultrabooks will account for 19 percent of overall notebook shipments in 2012 or 40 million units, we think it’s fair to say that Ultrabooks could, to some extent, cannibalize traditional laptops,” Muse said.

There are other challenges for Intel. For example, several companies are developing desktop and notebook systems based on ARM processors and Windows 8.

Vijay Rakesh, an analyst with Sterne Agee, is bullish on this segment. “While betting on (the) Windows launch dates has been difficult, we believe all major PC OEMs and ODMs are now working on ARM-based platforms for Windows 8,” he said. “The major ARM players collaborating with PC OEM-ODMs include Qualcomm Snapdragon, Nvidia Tegra and Texas Instruments OMAP. The PC market is expected to grow (about) 5 percent in C2012, but we believe about 5-10 percent plus of the PC mix could move to ARM-based solutions in C3Q/4Q thereby crimping the available market for x86 and Intel-AMD based solutions.”

Craig Berger, an analyst with FBR, said: “Beyond the near term, we do see some risks that Windows on ARM (WoA)–based notebooks could eat into Intel’s notebook CPU market over time. Further, Apple’s iPad and other tablets are cannibalizing some core PC growth. That said, Intel’s Ultrabook program seems a solid response to the WoA device threat, with more innovative notebooks likely to help spur the market.”

In other words, don’t count out Intel. “We think the firm’s execution is top notch with a robust product roadmap, process leadership, technology leadership (high-K, 3D transistors), and scale advantages—all as it pushes forward more aggressively into embedded and software markets,” Berger said.

Sematech announced the speakers for the 2011 International Symposia on Extreme Ultraviolet Lithography (EUVL) and Lithography Extensions.

Jia Li of Nvidia, Han-ku Cho of Samsung Electronics; and Risto Puhakka of VLSI Research, will address the conference, planned for Oct. 17-21 at Miami’s JW Marriott Marquis Hotel. The EUVL event is organized by Sematech, in cooperation with EIDEC and Imec, while the Lithography Extensions Symposium is in cooperation with Imec.

Jia Li, director of wafer foundry operations at Nvidia, leads a team evaluating 20nm and 14nm process technologies, including the readiness of EUV for and the extendability of 193nm immersion lithography to the 14nm node. His speech will address lithography challenges, including critical dimension/line-edge roughness (LER) control, defect elimination, and throughput.

Han-ku Cho, vice president and head of the photomask team at Samsung Electronics, is the keynote speaker at the 2011 International Symposium on Extreme Ultraviolet Lithography. Cho joined Samsung’s Electronics Semiconductor Business in 1995 and has served as vice president and director since 2007, in charge of production, management, and technology development of the Photomask Team at the company’s  Semiconductor R&D Center. Cho led the Korean government program in EUV lithography for nine years.

Cho’s topic, “EUV Readiness and ASML NXE: 3100 Performance,” will look at the current status and readiness of EUVL as well as the EUV mask fabrication process from the viewpoint of a device manufacturer. He will include imaging performance and issues related to the NXE: 3100, as well as achievements and prospects in EUV resist development focused on line width roughness reduction.

Risto Puhakka, president of VLSI Research, Inc., is the keynote speaker at the 2011 International Symposium on Lithography Extensions. He will explore the conditions that enable innovative lithography technologies to be introduced into mainstream semiconductor manufacturing.