Tim Archer

By David Lammers

Wafer-level packaging and 3D NAND are two market drivers that will propel revenues at the combined Lam-Novellus operation this year and next, chief operating officer Tim Archer said.

In a conference call following release of Novellus Systems’ fourth quarter and full-year 2011 results, Archer was asked if he stood by earlier predictions that Novellus’s revenues would reach the $2 billion level in the next two years, up from about $1.35 billion last year.

“2013 will be a strong year for wafer front end (WFE) investments overall, and in our case we will see a payoff from our focus on the 3D packaging space. WLP represents $700 million in new SAM (served available market) and already we are seeing tremendous growth in the copper electroplating segment. And we are still a strong believer that 3D NAND will begin to take off in 2013,” Archer said.

As memory companies build NAND devices with 16 to 32 layers of NAND memory cells, Novellus will be able to sell more plasma-enhanced CVD and dry strip tools, he said. Tungsten back fill is another area of opportunity.

“When we compare 2D to 3D NAND, the Novellus opportunity grows by about 30 percent at the same bit growth rate, according to our analysis,” Archer said.

Throughout the conference call, various stock analysts congratulated CEO Rick Hill on his 19 years of service at Novellus. Hill said while the merger between Lam and Novellus is likely to be completed in the second quarter, another Novellus conference call is unlikely. As Hill departs, Lam Research CEO Martin Anstice will lead the combined company, with Archer serving as the COO.

Hill said he is more optimistic about capital spending in 2012 than most other CEOs and industry analysts. While foundry investments will remain relatively strong in the first half, Hill said he is optimistic about a recovery in NAND-related investments in the second half of the year, partly because Ultrabook-style computers will rely more heavily on solid-state disk drives. Also, he said China will begin to invest in leading-edge semiconductor production, moving quickly forward with a “major thrust at the leading edge, which they are quite capable of doing.”

Governments in Europe and the United States will continue to stoke their economies in 2012. “This is an election year, and money will be stuffed in because leaders are worried about deflation,” Hill said.

While Novellus’ 2011 revenues were identical to 2010 revenues, at $1.35 billion, Hill said the company earned an all-time-high earnings per share of $3.20. Bookings in Q4 were $286.9 million, up $60 million (26.4 percent) from Q3 2011 bookings of $226.9 million.

Improving the Quality of PVD Cu Seed Layer

By David Lammers

Novellus Systems CEO Rick Hill, in what may be one of his last public appearances in that role, said orders for semiconductor equipment are strengthening and 2012 may turn out to be much better than prognosticators are forecasting.

Speaking early Thursday (Jan. 12) at the Needham Growth Conference for investors, Hill said “the force fields are in place” for 2012 to be “flat to slightly up” in terms of semiconductor equipment revenues.

In its mid-quarter update in December, Novellus executives said orders were bouncing back from the second-half dip. Hill said forecasters which see a roughly 5-10 percent decline in wafer fab equipment spending this year may be proven wrong. Calling himself “a lone wolf” in predicting a flat or positive growth year, Hill said “by the end of the second quarter I think we’ll see Dataquest saying that the industry is growing again.”

On Wednesday, SEMI predicted that fab equipment spending will decline about 11 percent in 2012, though it hedged that forecast by saying that several of the largest companies could upgrade their spending plans, resulting in a relatively small 4 percent decline from the robust spending seen in 2011 overall. WFE spending was in the $30 billion range last year.

Displaying his acerbic wit, Hill said “the world may be coming apart, but people are still busy buying electronics products so they can read all about it.”

In a familiar line of argument, he said equipment investments will be driven by new applications and systems made possible by advancing semiconductor technologies. Among the growth engines are solid-state disk drives (SSDs) which have long been a favorite topic for Hill and other Novellus executives. He said progress is being made in the vertical NAND development effort, which would require depositing from 32 to 64 alternating layers of nitrides and oxides, with deeply etched holes created to form connections between the vertically stacked storage cells.

Widespread addoption of SSDs is “on the horizon, reachable and touchable,” he said, adding that the cost per bit and density of NAND devices are “at an inflection point to replace rotating (HDD) memory with solid-state storage.”

Hill claimed that the vertical NAND emphasis on deposition and etch plays into the hands of the combined Novellus-Lam company, a deal which Hill said is likely to close in the second quarter. The enlarged Lam Research will be better able to develop dep-and-etch solutions for customers fielding vertical NAND products. “There is no question the combined companies (Novellus and Lam) can better address a spectrum of applications. The combined companies have more arrows in the quiver.”

Hill said the 450mm wafer transition will “start to materialize” in 2017, after EUV lithography works out its challenges. “The first push has to be to make EUV viable. That is numero uno. Then we have to freeze on a node for 450, so that we can have a more organized transition that is economically viable.”

Hill has said he will retire from Novellus after the merger goes into effect. He briefly touched on his 38-year career in the semiconductor industry, noting that the equipment industry changed after 2000 as mega-sized semiconductor companies came to dominate. While acknowledging there “will always be opportunities” for the smaller equipment companies, Hill said the largest chip makers require vendors which can scale equipment production “from zero to the highest levels” of volume production in roughly six months.

“It is tough for the small companies,” Hill concluded.

By David Lammers

Novellus Systems CEO Rick Hill said equipment bookings may be recovering from a recent bottom, with Novellus’s fourth quarter bookings expected to be up 10 to 30 percent from the third quarter.

Hill concluded a conference call about the company’s third quarter results by saying that he has found “a small bit of good news” in the recent jump in bookings and the improved forecast for the rest of the fourth quarter.

The company reported Wednesday (Oct. 26) that Q3 bookings were $226.9 million, down $84.7 million (27.2 percent) from Q2 bookings of $311.6 million. Third quarter shipments were $301.6 million, down $57.7 million (16.1 percent) from the second quarter.

While the markets in the United States and Europe for computers and other electronics remain “soft,” Hill said demand in Asia is relatively strong. While he shied away from saying that the floods in Thailand, which have impacted HDD production, would have a direct impact on orders for Novellus, he said the trend is to replace HDDs with solid-state drives (SSDs).

Novellus has a two-pronged growth strategy, based on an expected takeoff of the vertical NAND memories where bits are stacked using sophisticated deposition tools, and continued growth in wafer-level packaging and TSV interconnects. The move toward finFETs also drives demand for new deposition equipment.

Conformal oxide deposited over FinFET core by Novellus Vector CFD. Image courtesy of Novellus

“As we see more SSD-based computers hit the consumer marketplace, that will require more capacity,” Hill said. Asked if NAND vendors would backfill existing fabs with vertical NAND capacity, Hill said he “absolutely” expects companies to move to vertical NAND next year at both existing and green field fabs. Besides adding volumetric transistor density, the V-NAND memories are less reliant on the expensive lithographic tools, he said, adding that vertical NAND becomes more attractive as EUV lithography throughputs and costs remain clouded.

“V NAND allows our customers to enjoy lithography cost reductions. 2012 is when we will begin to see capacity come on line,” Hill said.

TSVs are another technology advance on the verge of taking off, as designers begin to appreciate that “volumetric transistor density, not just area density, is what counts. TSVs are, in my opinion, one of the most underutilized tools in the designer’s toolbox.”

The headwind facing the equipment industry since mid-summer has more to do with macroeconomic issues than with the appeal of today’s electronics products. “It is the fundamental irresponsibility of sovereign nations, including our own, to deal with the inability to cut spending,” Hill said.

During the third quarter, Novellus continued to buy back shares of its own stock. Over the last five years, Novellus has bought back much of its available stock, worth about $3 billion, at an average share price of $27.73. The board of directors has authorized up to $500 million worth of additional stock repurchases by December 2014, which one stock analyst said, speaking half seriously, will be a stealth form of “taking the company private.”

“I’ve asked our investors for their opinions (on the share buy backs) and the resounding reply is: ‘Keep doing what you are doing,’” Hill said.

By David Lammers

Semiconductor equipment executives participating in the Citi Technology Conference in New York earlier this week said development work on 450mm-capable equipment is picking up, but uncertainty continues over the timing of the transition.

Rick Hill, the CEO at Novellus Systems Inc., said he expects suppliers and semiconductor vendors to meet during the SEMI International Trade Partners Conference, set for Nov. 6-9 in Hawaii, to discuss funding mechanisms for 450mm R&D.

Intel, Samsung, and TSMC have said they would like to begin using the larger wafers in the middle of this decade, at the 14nm node or later.

Hill expressed skepticism about a fast transition to the larger wafer size. “First we have to have EUV before any transition to 450mm can occur. We can’t have an EUV tool with a throughput of six wafers per hour like we have now and expect it to be economically viable,” Hill said.

The Novellus CEO said he expects only three companies to make an early transition to 450mm. Since many companies will never build 450mm fabs, it will cause a divide among Novellus’s customer base, Hill said.

“Right now we are looking at the technology roadblocks,” he said, listing heavier wafers, uniform plasma densities, and electroplating as challenges. “For ECD, maintaining a uniform current, so we can plate at exactly the same thickness – putting down that 1000 Angstrom seed layer – promises to be a very difficult challenge,” he said.

George Davis, the chief financial officer at Applied Materials, said Applied “will ship some 450mm tools next year.” Applied will shift from relatively inexpensive design-related work going on now to 450mm tool building in the first half of 2012.

“We will start bending metal in 2012,” Davis said.

He reiterated a statement made during Semicon West, that Applied will invest slightly more than $100 million next year in 450mm equipment development.

Asked when the transition to the larger wafer diameter will begin, Davis said “it is very hard to call a consensus on when customers want 450mm equipment,” but added that Applied “wants to support our customers’ roadmaps.”

Asked if Applied sees the 450mm wafer transition as an opportunity to gain market share, Davis said the wafer transition is “a big enough inflection point that it does represent a share gain opportunity.”

Ernie Maddock, the chief financial officer at Lam Research, told the Citi conference participants that “there are opportunities for Lam Research at 450. Any time there is a major inflection point, we want to be very well positioned.”

(Source: IC Knowledge)

“We want to move with them,” Maddock said, referring to the companies committed to 450mm pilot lines. “It is a difficult challenge figuring out the timing. Some are saying they want it pulled in, others that they expect it to be pushed out. We want to go through a thoughtful process and think about the industry’s investment portfolio.”

All of the executives said their companies are spending more on R&D. Maddock said Lam is working with its customers on five major technology areas: through-silicon vias (TSVs), vertical NAND structures, 3D DRAM structures, 3D logic transistors, and the transition to 450mm wafers.

To some extent, investments in 450mm fabs depend on chip demand and the economic health of the semiconductor industry. Hill said Novellus believes overall demand for semiconductors is “fairly good.”

“Our customers are up one day, down the next. Nine months from now things might be different, but right now most don’t feel very good about things, so they tend to wait. It is not like 2009, when the industry was in a cash crisis. We are in a period of lack of confidence, not lack of demand,” Hill said.

Davis said the industry is in “one of those periods where there is a lot of volatility.” While some customers are putting orders on hold, few are cancelling, and many customers are hoping for a strong Christmas shopping season to spur demand for integrated circuits.

By David Lammers

The advent of 3D NAND memories may be only two or three years away, speakers said at Semicon West in San Francisco. By 2013 the major memory companies developing 3D NAND, including Hynix, Samsung, and Toshiba, may be ready with pilot lines, moving to volume production a year or so later. Taiwan-based Macronix International also has been developing a 3D NAND solution.

Samsung TCAT stack. (2009 Symposium on VLSI Technology)

The increasing emphasis on 3D NAND comes as the cost of advancing planar 2D NAND to the next technology node — lithography in particular — may be prohibitive. 3D NAND could come in with a 55nm half pitch, possible using a dry lithography toolset. And the basic steps are fairly straightforward. With Samsung’s TCAT process flow, for example, multiple oxide and nitride deposition layers are stacked. Then the silicon nitride is removed by a wet etch process, followed by a tungsten fill for the bit and word lines and contacts.

Fusen Chen, executive vice president at Novellus Systems Inc., said the 2D planar NAND architectures are at the 20nm node this year, moving to 1X technologies by 2013. That will require either self-aligned quad patterning with 193nm immersion scanners, or EUV lithography – in his view both “very expensive solutions.”

To avoid the high lithography costs, Chen said 3D NAND “will start in earnest in 2013.”

There also are materials challenges to scaling today’s planar NAND. A 1X planar NAND technology requires floating gate shaping and air gap engineering to deal with the parasitic capacitance coupling challenge, said Gil Lee, a senior director at Applied Materials who has worked for several memory manufacturers. Also, 2D NAND faces inter-poly dielectric scaling issues, requiring decoupled plasma nitridation to form the NONON dielectric.

Gil Lee (photo courtesy of Chris Edwards)

“When 3D goes into production depends on how far they can push 2D planar technology,” Lee said, adding that the “migration to 3D NAND revives the scaling roadmap again.”

Bart van Schravendijk, a senior fellow at Novellus, said that by 2013 the NAND makers will need double or quad patterning, either with or without EUV.  “The concern is that EUV plus SADP will be very costly. 3D NAND does not depend on lithography scaling. And TSVs are coming to NAND,” he said during a presentation at a TechXPOT session on emerging memory architectures.

While the NAND vendors are “very serious about 3D, there are a lot of challenges leading up to commercialization,” van Schravendijk said.

Each of the major memory companies has a different approach to a vertical channel NAND. Toshiba and Samsung prefer a charge-trapped flash technology, while Hynix is developing a vertical floating-gate structure. The various vertical NAND approaches employ either a gate-first or gate-last process flow.

3D NAND approaches. (Source: IMW 2011)

At the TechXPOT session both Lee and van Schravendijk outlined the major challenges facing vertical NAND.

Lee said multi-layer stack deposition requires low-cycle-time PECVD deposition, while the high aspect ratio etch requires high mask selectivity. Also, slimming of the control gate requires good control of the anisotropic slimming etch step. The high aspect ratio gap fill requires a highly flowable CVD film.

Lee said Applied’s technologists believe single-wafer processing in one station to be the most-effective solution for deposition, where very smooth films with an RMS of less than one nanometer are required.  Etching the 16-layer staircase contact structure, with a sufficient landing area for the contacts, requires an 80:1 aspect ratio contact area. The critical dimension control required is better than the lithographic CDs, and calls for very high throughput rates.

Bart van Schravendijk (photo courtesy of Chris Edwards)

Van Schravendijk said 3D multi-layered structures require excellent etch profile control, deposition of atomically smooth films, and improved tungsten fill. Wafer bow control, particles, and cost also are among the issues. “3D can be low cost if we can quickly switch between oxynitride — without particles — and silicon nitride deposition. We must have good oxide selectivity,” he said. Unlike the move to EUV for 1X 2D NAND, the good news is that “with 3D they don’t have to change the toolset. 3D is “no longer linked by litho.”

Enticed by a shift from a lithography capital intensive 2D flow to a deposition and etch intensive approach, the major equipment vendors are paying close attention to 3D NAND equipment development.

Girish Dixit, a Novellus vice president of process applications, said 3D NAND was one of the central themes at this year’s VLSI Symposium on Technology, held in Kyoto, Japan in early June. A panel discussion on memory technology, Dixit said, concluded that 3D NAND would emerge in pilot lines in 2013.

“There is a lot of activity in this area, partly because companies are facing limits on scaling today’s floating gate NAND. Companies are looking at how difficult it is to get the reliability and endurance their customers need at the 1X node with floating gate planar memory cells. And to scale planar memories, they will need to go to quad patterning or EUV,” he said.

In a recent Toshiba press release announcing readiness of a new line at its Yokkaichi fab complex, Toshiba said the new fab would be used for leading edge planar NAND as well as 3D flash memories, which the company referred to as “post-NAND flash memory.”

Chen said the 2D planar architecture may run out of steam at the 128 gigabit or 256 gigabit densities. With a 3D approach, the design rules are relaxed to 55 nm and “there is not an added layer of lithography – you can pattern all the bits in one shot.”

The challenge shifts to the deposition and etch steps. “Memory companies have to be able to etch the nitride selectively back to the oxide layer. To do that, they must engineer the material properties so they get the right interface, 64 times, with less than one defect.”

Chen said 3D NAND technology, looked at from a high level, involves stacks of oxide and nitride films. The nitride film is etched away and replaced with tungsten, leaving an oxide layer to separate the two bits.

“The 32 layers need to be very smooth, with better than 1 percent uniformity while eliminating all air bubbles,” Chen said.

Dixit said 3D NAND is “definitely not five years away. Before the VLSI conference, some people thought it was five or six years away. Now, the expectation is that it is only two to three years out,” he said.

Tim Archer, the chief operating officer at Novellus, said NAND costs dropped rapidly from 2000 to 2008. Since then, bit cost reductions have become more difficult to accomplish. By moving to 3D NAND, memory companies will avoid high lithography costs and be able to move to a smaller die size, albeit one with multiple vertical layers of memory cells.

Rather than adopt 16nm technology with multi-level-cell (MLC) NAND, memory vendors could turn to 55nm technology with 32 pairs of bit cells. “That will give the 3D NAND vendors a huge cost advantage. With that we will start to see a massive conversion to solid-state disk drives,” Archer said at Semicon West.

By David Lammers

Novellus Systems CEO Rick Hill said several major semiconductor companies have postponed orders, characterizing the pushouts as a “pause” in an otherwise robust semiconductor environment.

Hill, who has led Novellus for 18 years, spoke at the Novellus press and analyst event at Semicon West Monday, shortly after the company reported that sales for the second quarter were $350.2 million, down $63.0 million (15.2 percent) from the first quarter of this year. Bookings were $311.6 million, down $103.5 million or 24.9 percent from the first quarter.

He said the financial results “are not the greatest news, but I do believe they are temporary news.” World financial uncertainty, couple with the natural disasters in Japan, combined to weaken demand for semiconductors. “There is uncertainty in capital spending because of these worldwide events,” he said.

At an Applied Materials event this week, CEO Mike Splinter said factors such as high unemployment in the United States, the Greek debt crisis, and other macroeconomic issues “are weighing on the demand” for electronics products.

Splinter argued that “the fundamentals are still good” for the semiconductor industry, with a still largely untapped market in the so-called BRIC countries of Brazil, Russia, India and China. Those nations account for about 18 percent of the world economy, compared with the 23 percent share of the United States. But BRIC countries account for only 12 percent of electronics spending, while U.S. electronics sales are 28 percent of the total.

PC sales growth has not been stellar this year, and tablet sales by vendors other than Apple Inc. have been disappointing. “We thought DRAM investments would have come back this year, but that is less likely with the PC growth rates we are seeing,” he said.

Foundry utilization has dropped to the 80 percent range, low enough for some foundries to become more conservative. “They are cautious, but they want to be prepared” in case demand snaps back, Splinter said.

Hill recently returned from a trip to Taiwan, where major foundry executives described temporary changes to their investment plans. A major Korean semiconductor manufacturer also detailed its purchase delays, Hill told participants at the event.

At a Monday market briefing by market research firm Gartner Inc. and SEMI, Gartner research vice president Dean Freeman said the rest of 2011 will be buffeted by concerns over oil prices, sovereign debt, jobs, and housing. “Oil drives our economy,” Freeman noted, adding that “no one is putting many bets on the second half of this year, but 2012 should be stronger.”

Novellus executives put the event’s focus on a two-year window, saying that by 2013 the trends toward wafer level packaging, vertical NAND, finFETs and other advanced transistors, will propel Novellus’ annual revenues to the $2B level, up from roughly $1.5B now.

Tim Archer, the Novellus chief operating officer, said the company has developed tools capable of conformal films deposition, or CFD. In order to stack NAND cells, the nitride and oxide layers must be extremely smooth. “Our Vector CFD is an enabling technology for 3D transistors. It has the productivity needed to make this 3D NAND technology viable,” he said.

Archer said the first 3D NAND products could some as early as 2013, enabling a 60 percent die size improvement over the conventional multi-level-cell NAND products. By stacking as many as 32 bits vertically, memory companies will be able to get back on the cost reduction curves seen until recently.

“The cost per byte has been slowing recently, which is a bit concerning,” Archer said. With 3D NAND, companies will rely more heavily on CFD oxide and nitride deposition, as well as tungsten metal deposition equipment, recently put on the market by Novellus. The 3D NAND conversion will be less reliant on EUV lithography tools, which Hill said are far too expensive. A 3D NAND chip could rely on 55nm half-pitch, displacing MLC NAND based on 16nm technology, for example.

Armed with higher densities and aggressive cost reductions, NAND memory vendors will be able to price solid-state disk (SSD) memory at a roughly 2:1 ratio with hard disk drive storage.

“At 2:1, we will start to see a massive conversion to SSDs. 3D NAND will have a huge cost advantage,” Archer said.

At a SEMI press conference Monday, SEMI executive vice president Jonathan Davis said demand for semiconductor equipment and materials will likely be “steady as she goes” for the next year or two, after a strong rebound in 2010.

Davis, president of SEMI’s semiconductor business operation, said the semiconductor industry is likely to increase from $314 billion this year (the first year that chip revenues are expected to exceed the $300 billion threshold) to $375 billion in 2014, according to the World Semiconductor Trade Statistics (WSTS) council. That will drive “steady growth in fab capacity,” including continuing investments in North America by Intel, GlobalFoundries, and Samsung Austin, among others, Davis said.

While SEMI is predicting a 19 percent increase in wafer fab spending this year, a cyclical decline in spending by the test and assembly sector will drag down the total, resulting in a 12 percent increase in overall equipment spending this year. Of the $44.3 billion in expected equipment spending, a respectable $9 billion will be in North America, exceeded only by Taiwan’s spending. Dan Tracy, director of SEMI’s Industry Research & Statistics operation, said the test forecast depends partly on the “wild card” of investments by the memory IC vendors.

By Katherine Derbyshire

Of the many obstacles to low-k dielectric integration, plasma damage has always been one of the most severe. Plasma is used in both pre- and post-etch cleaning steps, as well as in the dielectric etch itself. Carbon depletion is one of the most notorious damage mechanisms, but the etch-clean cycle can also deposit residues on the dielectric surface, densify the dielectric material, and damage the sidewalls of features. If plasma damage is bad enough, the metal diffusion barrier may fail to adhere, allowing moisture and metal ions to infiltrate the dielectric. Even under optimum conditions, the damaged layer increases the effective dielectric constant of the structure. As device features get smaller, the damaged layer accounts for a larger fraction of the total linewidth, to the point where damage can offset the advantages of a lower dielectric constant.

At the Materials Research Society Spring Meeting in April, Olivier Joubert of LTM-CNRS bluntly suggested that the semiconductor industry needs a new strategy. Plasma damage is unavoidable, in his view, and ultimately limits the dielectric constant that can be achieved.

Even though manufacturers have been struggling with low-k integration issues for more than a decade, the view within the industry is somewhat more optimistic. Klaus Schuegraf, CTO of Applied Materials’ Silicon Systems Group, pointed out that third generation low-k materials are much more versatile than second generation materials. Second generation materials incorporated relatively large pores into dense carbon-doped oxide materials. Third generation materials, in contrast, still depend on carbon-doped oxides, but are based on new starting materials that incorporate nanometer-scale pores into the oxide’s molecular structure. In third generation materials, Schuegraf said, manufacturers can more precisely engineer porosity to achieve the dielectric constant and mechanical strength required by a particular integration scheme. This control of the material structure gives process engineers new avenues for repair of plasma damage. Though damage is a “fact of life,” Schuegraf said, it need not be a showstopper for the industry. Indeed, people interviewed for this article were generally optimistic about the outlook for dielectric repair processes to reverse the effects of carbon depletion.

Timing is an important variable in any potential repair strategy. Since damage can occur at several points, up to and including the final cleaning step before deposition of the metal diffusion barrier, the repair step should be inserted into the flow as late as possible. On the other hand, any repair of the dielectric must be completed before deposition of the diffusion barrier, both to ensure good barrier adhesion, and because deposition of the barrier will block any further changes to the dielectric.

Though people I spoke with were optimistic about repair, most were reluctant to discuss specific repair schemes in any detail. In work presented at MRS, Sven Zimmerman of Fraunhofer ENAS reported that methylation and silyation can both restore depleted carbon. His group immersed etched low-k materials in HMDS (C₆H₁₉NSi₂), finding that the Si-methyl groups bonded to the dielectric surface, while UV radiation helped to eliminate excess hydrogen.

In March, Novellus introduced the Lumier pre-treatment chamber for the company’s Vector Excel diffusion barrier deposition system. This chamber can provide heat treatment, optical treatment at a variety of wavelengths, and a controlled atmosphere, thereby supporting a number of potential pre-treatment strategies. According to Easwar Srinivasan, Novellus’ Director of Product Marketing for PECVD, the company has seen materials with as-deposited k=2.4 degrade to dielectric constants of 3.1-3.2 after etching. In internal tests, the company has been able to restore 70-80% of that damage. While similar numbers have been achieved in complete circuits, Boaz Kenane, director of technology for UVTP PECVD at Novellus, warned that the capacitance of fully integrated devices is difficult to measure and actual RC constants may vary. Pattern dependencies and the characteristics of the copper lines play important roles, above and beyond the contribution of the dielectric.

And there, perhaps, lies the most serious challenge for low-k integration, and for interconnect processes in general. No matter how successful integration of a low-k dielectric may be, it is ultimately just a delaying action. As feature sizes continue to shrink, the contribution of copper lines to circuit delays starts to climb rapidly. The capacitance problem is hard, but the resistance problem may be even harder. Both are likely to keep process engineers busy for a long time.

Novellus subsidiary Peter Wolters GmbH (Rendsburg, Germany) said it has introduced new gap measurement technology for double-side silicon prime wafer polishing (DSP), employing high-resolution sensors and new software algorithms. The advances in the AC2000-P³ system result in improved wafer quality control and higher throughputs, the company said.

In order to achieve ultra-flat wafer geometries, double-side polishing is the technology of choice to manufacture 300 mm and 450 mm prime silicon wafers.  The polishing wheel gap dimension and control throughout the polishing process is critical in determining the total within-wafer and wafer-to-wafer thickness variation (GBIR/TTV), the company said.  Figure 1 shows the impact of gap profile control on the GBIR measurement, a measure of the final prime wafer quality.

Source: Peter Wolters

To address the need for precise polishing wheel control during the double-side polishing process, Peter Wolters engineers incorporated several innovative features into the latest variant of the AC2000-P³ system.  New contactless gauges with increased accuracy now provide sub-micron resolution during the in-situ gap measurement.  This new sensor technology has been incorporated into Peter Wolters’ upper platen adaptive control (UPAC) system and provides faster response times to process variations incurred throughout the polishing process.

Additionally, the AC2000-P³ polishing process uses the industry’s first non-contact, sensor-based end point detection feature. This technology ensures repeatable within-batch and batch-to-batch wafer thickness, along with extremely low edge roll-off values (ESFQR).

Source: Peter Wolters GmbH

The new sensor technology incorporates a proprietary software algorithm that replaces time-based statistical process control (SPC) to precisely measure the final wafer thickness.  By eliminating non-value added polishing time, the system throughput has also been significantly increased.

“In preparation for next generation technology nodes, the new gauges and software algorithms developed for the AC2000-P3 will provide our customers with the combination of high productivity, process flexibility and precision polishing control that they require,” said Dave Celli, chief executive officer of Novellus’ Industrial Applications Group. “While designed for today’s 300 mm wafers, the AC2000-P³ can also simultaneously process up to five 450 mm wafers, thus preparing Peter Wolters’ customers for the next wafer size transition as well.”

By David Lammers

Faced with widespread concerns over the Japan earthquake, rising gasoline prices, and high U.S. debt, some semiconductor companies are becoming slightly more cautious, Novellus Systems executives said following release of Q1 financial results.

For the quarter ending March 26, Novellus reported its highest net profit in a decade, and the company bought back $200 million in stock. Net sales were $413.2 million, an increase of 7.5 percent from Q4, and net income was $96.4 million. However, Q1 shipments of $376.9 million were down $41 million, or 9.8 percent, from Q4 2010.

CEO Rick Hill said two customers pushed out all of their orders for Novellus’ semiconductor equipment in the quarter. But Hill said he believes those customers may quickly reverse course and reinstate their orders, rather than miss out on strong demand in the third quarter, as system companies prepare for what Hill said is likely to be a strong Christmas shopping season for electronics.

Hill said the pushouts represent “a short little setback” to what otherwise is a strong demand picture. When one stock analyst suggested that the chip industry is becoming “mature,” Hill took issue with that characterization.

“We are not yet in a period of mature growth. Rather than consumers becoming more mobile, as the energy cost of going mobile increases, we are seeing that people want ‘the experience’ to come to them. I don’t think the electronics industry is becoming mature. I see this (strong demand for electronics systems) continuing for the next five years,” Hill said.

Analysts queried Hill and Timothy Archer, the company’s chief operating officer, about two customers – one in the logic sector and another which makes both DRAM and NAND memories – which delayed all of their equipment orders from Novellus from the current second quarter to the third quarter. Hill said some customers “are becoming more cautious” as they look at what he called “the impact of external forces.”

The Japan quake has had a widespread impact on key parts of the supply chain, ranging from epi wafers, photoresists, 200-mm scanners, several cleaning chemicals and etchers, to MCUs and “a myriad of other sub-components.”

“It is difficult to believe, with the scale of the quake’s impact on suppliers, that it won’t have some impact” on systems customers, Hill said, adding that supply constraint problems will affect the second quarter and possibly the third quarter of this year before abating.

However, the longer-term picture is good, he said, predicting that some systems companies may find themselves short of goods to sell to a Christmas buying public eager to purchase smart phones, tablets, and other popular items. “End demand is so strong,” Hill said, “that the long-term trend is for more needs for more semiconductors.”

Hill acknowledged that what he called “five-dollar gas” will crimp pocketbooks, taking money away from consumers who would otherwise buy electronics. And he took a dig at the U.S. government, which he said is causing “unrest at home” by not being able to “spend less than it takes in” – implying that a “no credit – no cash” approach to the national debt may be what is needed.

Interior of the Novellus Sabre tool

Asked about a potential move to FinFET transistors, Hill said much of the company’s R&D has been invested in the tools needed to make the vertical transistors. “We are very well positioned there, but as much as I would like everything to go to FinFETs, the cost and production challenges of FinFETs for the mass of applications has to be considered.”

Some customers are more likely to use a fully depleted, planar SOI technology. “There is nothing more simple than a planar transistor. FinFETs are not as massively adaptable,” Hill said.

He said NAND will be the biggest opportunity going forward, as solid-state disk drives (SSDs) continue to gain share. Computers increasingly will eschew HDDs in favor of SSDs, and NAND densities will see a tenfold increase in the next year, he predicted.

Archer said while demand for personal computers remain strong, some new entrants to the tablet space have yet to gain traction, causing foundries to miss their targets. “We still believe that tablets and smart phones will continue to drive demand, including NAND. The forecasts may have gotten ahead of the shipments,” Archer said.