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Posts Tagged ‘NMOS’

Leti’s CoolCube 3D Transistor Stacking Improves with Qualcomm Help

Wednesday, April 27th, 2016

By Ed Korczynski, Sr. Technical Editor

As previously covered by Solid State Technology CEA-Leti in France has been developing monolithic transistor stacking based on laser re-crystallization of active silicon in upper layers called “CoolCube” (TM). Leading mobile chip supplier Qualcomm has been working with Leti on CoolCube R&D since late 2013, and based on preliminary results have opted to continue collaborating with the goal of building a complete ecosystem that takes the technology from design to fabrication.

“The Qualcomm Technologies and Leti teams have demonstrated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.” As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs to accelerate adoption.

Olivier Faynot, micro-electronic component section manager of CEA-Leti, in an exclusive interview with Solid State Technology and SemiMD explained, “Today we have a strong focus on CMOS over CMOS integration, and this is the primary integration that we are pushing. What we see today is the integration of NMOS over PMOS is interesting and suitable for new material incorporation such as III-V and germanium.”

Table: Critical thermal budget steps summary in a planar FDSOI integration and CoolCube process for top FET in 3DVLSI. (Source: VLSI Symposium 2015)

The Table shows that CMOS over CMOS integration has met transistor performance goals with low-temperature processes, such that the top transistors have at least 90% of the performance compared to the bottom. Faynot says that recent results for transistors are meeting specification, while there is still work to be done on inter-tier metal connections. For advanced ICs there is a lot of interconnect routing congestion around the contacts and the metal-1 level, so inter-tier connection (formerly termed the more generic “local interconnect”) levels are needed to route some gates at the bottom level for connection to the top level.

“The main focus now is on the thermal budget for the integration of the inter-tier level,” explained Faynot. “To do this, we are not just working on the processing but also working closely with the designers. For example, depending on the material chosen for the metal inter-tier there will be different limits on the metal link lengths.” Tungsten is relatively more stable than copper, but with higher electrical resistance for inherently lower limits on line lengths. Additional details on such process-design co-dependencies will be disclosed during the 2016 VLSI Technology Symposium, chaired by Raj Jammy.

When the industry decides to integrate III-V and Ge alternate-channel materials in CMOS, the different processing conditions for each should make NMOS over PMOS CoolCube a relatively easy performance extension. “Three-fives and germanium are basically materials with low thermal budgets, so they would be most compatible with CoolCube processing,” reminded Faynot. “To me, this kind of technology would be very interesting for mobile applications, because it would achieve a circuit where the length of the wires would be shortened. We would expect to save in area, and have less of a trade-off between power-consumption and speed.”

“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological development in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”

—E.K.

Solid Doping for Bulk FinFETs

Monday, January 5th, 2015

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By Ed Korczynski, Sr. Technical Editor

In another example of the old one-liner that “all that is old is new again,” the old technique of solid-source doping is being used by Intel for a critical process step in so-called “14nm node” finFET manufacturing. In the 7th presentation in the 3rd session of this year’s IEDM, a late news paper written by 52 co-authors from Intel titled “A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588m2 SRAM Cell Size” disclosed that solid source doping was used under the fins.

As reported by Dick James of Chipworks in his blog coverage of IEDM this year, the fins have a more vertical profile compared to the prior “22nm node” and are merely 8nm wide (Fig. 1). Since Intel is still using bulk silicon wafers instead of silicon-on-insulator (SOI), to prevent leakage through the substrate these 8nm fins required a new process to make punch-through stopper junctions, and the new sub-fin doping technique uses solid glass sources. Idsat is claimed to improve by 15% for NMOS and 41% for PMOS over the prior node, and Idlin by 30% for NMOS and 38% for PMOS.

FIGURE: Intel Corp’s “14nm node” finFETs show (in the left SEM) 8nm wide and 42nm high fins in cross-section, below which are located the punch-through stopper junctions. (Source: IEDM 2014, Late News 3.7)

Solid glass sources of boron (B) and phosphorous (P) dopants have been used for decades in the industry. In a typical application, a lithographically defined silicon-nitride hard-mask protects areas from a blanket deposition in a tube furnace of an amorphous layer containing the desired dopant. Additional annealing before stripping off the dopant layer allows for an additional degree of freedom in activating dopants and forming junctions.

In recent years, On Semiconductor published how solid-source doping on the sidewalls of Vertical DMOS transistors enable a highly phosphorous doped path for the drain current to be brought back to the silicon surface. The company shows that phosphorous-oxy-chloride (POCl) and phospho-silicate glass (PSG) sources can both be used to form heavily doped junctions 1-2 microns deep.

The challenge for solid-source doping of 8nm wide silicon fins is how to scale processes that were developed for 1-2 microns to be able to form repeatable junctions 1-2 nm in scale. Self-aligned lithographic techniques could be used to mask the tops of fins, and various glass sources could be used. It is likely that ultra-fast annealing is needed to form stable ultra-shallow junctions.

Intel is notoriously protective of process Intellectual Property (IP) and so has almost certainly ensured that any equipment and materials suppliers who work on the solid-source doping process sign Non-Disclosure Agreements (NDA) with amendments that forbid acknowledging signing the NDA itself, so it is pointless to directly ask for any further details at this point. However, slides from John Borland’s recent presentation at the NCCAVS Junction Technology Users Group meeting provide a great overview of the publicly available information on finFET junction formation, and include the following:

…higher dopant activation can be realized at low temperatures if the junction is amorphous and recrystalized by using SPE (solid phase epitaxy) recrystalization of the junction as also shown in the data by Intel.

Also seen at IEDM this year in the 7th presentation of the Advanced Process Modules section, Taiwanese researchers—National Nano Device Laboratories, National Chiao Tung University, and National Cheng Kung University—joined with Californian consultants—Current Scientific, Evans Analytical Group—to show “A Novel Junctionless FinFET Structure with Sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing.” They claim an ideal subthreshold swing (~60 mV/dec) at a high doping level. Poly-Si n & p JLFinFETs (W/L=10/20 nm) with SDP experimentally exhibit superior gate control (Ion/Ioff >10E6) and improved device variation.

—E.K.

Germanium Junctions for CMOS

Tuesday, November 25th, 2014

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By Ed Korczynski, Sr. Technical Editor, Solid State Technology and SemiMD

It is nearly certain that alternate channel materials with higher mobilities will be needed to replace silicon (Si) in future CMOS ICs. The best PMOS channels are made with germanium (Ge), while there are many possible elements and compounds in R&D competition to form the NMOS channel, in part because of difficulties in forming stable n-junctions in Ge. If the industry can do NMOS with Ge then the integration with Ge PMOS would be much simpler than having to try to integrate a compound semiconductor such as gallium-arsenide or indium-phosphide.

In considering Ge channels in future devices, we must anticipate that they will be part of finFET structures. Both bulk-silicon and silicon-on-insulator (SOI) wafers will be used to build 3D finFET device structures for future CMOS ICs. Ultra-Shallow Junctions (USJ) will be needed to make contacts to channels that are nanoscale.

John Borland is a renowned expert in junction-formation technology, and now a principle with Advanced Integrated Photonics. In a Junction Formation side-conference at SEMICON West 2014, Borland presented a summary of data that had first been shown by co-author Paul Konkola at the 2014 International Conference on Ion Implant Technology. Their work on “Implant Dopant Activation Comparison Between Silicon and Germanium” provides valuable insights into the intrinsic differences between the two semiconducting materials.

P-type implants into Ge showed an interesting self-activation (seen as a decrease in of p-type dopant after implant, especially for monomer B as the dose increases.  Using 4-Point-Probe (4PP) to measure sheet-resistance (Rs), the 5E14/cm2 B-implant Rs was 190Ω/□ and at higher implant dose of 5E15/cm2 Rs was 120Ω/□. B requires temperatures >600°C for full activation in PMOS Ge channels, and generally results in minimal dopant diffusion for USJ.

Figure 1 shows a comparison between P, As, and Sb implanted dopants at 1E16/cm2 into both a Si wafer and 1µm Ge-epilayer on Si after various anneals. The sheet-resistance values for all three n-type dopants were always lower in Ge than in Si over the 625-900°C RTA range by about 5x for P and 10x for As and Sb. Another experiment to study the results for co-implants of P+Sb, P+C, and P+F using a Si-cap layer did not show any enhanced n-type dopant activation.

Fig.1: Sheet-resistance (Rs) versus RTA temperatures for P, As, and Sb implanted dopants into Ge and Si. (Source: Borland)

Prof. Saraswat of Stanford University showed in 2005—at the spring Materials Research Society meeting— that n-type activation in Ge is inherently difficult. In that same year, Borland was the lead author of an article in Solid State Technology (July 2005, p.45) entited, “Meeting challenges for engineering the gate stack”, in which the authors advocated for using a Si-cap for P implant to enable high temperature n-type dopant activation with minimal diffusion for shallow n+ Ge junctions that can be used for Ge nMOS. Now, almost 10 year later, Borland is able to show that it can be done.

Ge Channel Integration and Metrology

Nano-scale Ge channels wrapped around 3D fin structures will be difficult to form before they can be implanted. However, whether formed in a Replacement Metal Gate (RMG) or epitaxial-etchback process, one commonality is that Ge channels will need abrupt junctions to fit into shrunk device structures. Also, as device structures have continued to shrink, the junction formation challenges between “planar” devices and 3D finFET have converged since the “2D” structures now have nano-scale 3D topography.

Adam Brand, senior director of transistor technology in the Advanced Product Technology Development group of Applied Materials, explained that, “Heated beamline implants are best when the priority is precise dose and energy control without lattice damage. Plasma doping (PLAD) is best when the priority is to deliver a high dose and conformal implant.”

Ehud Tzuri, director strategic marketing in the Process Diagnostic and Metrology group at Applied Materials reminds us that control of the Ge material quality, as specified by data on the count and lengths of stacking-faults and other crystalline dislocations, could be done by X-Ray Diffraction (XRD) or by some new disruptive technology. Cross-section Transmission Electron Microscopy (X-TEM) is the definitive technology for looking at nanoscale material quality, but since it is expensive and the sample must be destroyed it cannot be used for process control.

Figure 2 shows X-TEM results for 1 µm thick Ge epi-layers after 625°C and 900°C RTA. Due to the intrinsic lattice mis-match between Ge and Si there will always be some defects at the surface, as indicated by arrows in the figure. However, stacking faults are clearly seen in the lower RTA sample, while the 900°C anneal shows no stacking-faults and so should result in superior integrated device performance.

Fig. 2: Cross-section TEM of 1µm Ge-epi after 625°C and 900°C RTA, showing great reduction in stacking-faults with the higher annealing temperature. (Source: Borland)

Borland explains that the stacking-faults in Ge channels on finFETs would protrude to the surface, and so could not be mitigated by the use of the “Aspect-Ratio Trapping” (ART) integration trick that has been investigated by imec. However, the use of a silicon-oxide cap allows for the use of 900°C RTA which is hot enough to anneal out the defects in the crystal.

Brand provides an example of why integration challenges of Ge channels include subtle considerations, “The most important consideration for USJ in the FinFET era is to scale down the channel body width to improve electrostatics. Germanium has a higher semiconductor dielectric constant than silicon so a slightly lower body width will be needed to reach the same gate length due to the capacitive coupling.”

Junction formation in Ge channels will be one of the nanoscale materials engineering challenges for future CMOS finFETs. Either XRD or some other metrology technology will be needed for control. Integration will include the need to control the materials on the top and the bottom surfaces of channels to ensure that dopant atoms activate without diffusing away. The remaining challenge is to develop the shortest RTA process possible to minimize all diffusions.

— E. K.

Today’s Top Reliability Challenges

Friday, March 1st, 2013

By Pete Singer

BTS, BTI, soft errors, dielectric breakdown and other reliability challenges will be addressed at the upcoming International Reliability Physics Symposium.

A double challenge faces today’s reliability engineers. They not only must understand the physics behind a complex set of mechanisms, such as bias temperature instability (BTI), but they must accurately simulate those mechanisms through modeling to predict device performance over time and estimated end-of-life.

These challenges will be front and center at the upcoming International Reliability Physics Symposium (IRPS), to be held April 14-18, 2013 at the Hyatt Regency Monterey Resort & Spa in Monterey, CA. The conference begins with tutorials on Sunday that run through Monday afternoon (40% of attendees are first time attendees). A plenary session on Monday afternoon after the tutorials is a “Year in Review” where experts highlight work published over the last year. Tuesday morning starts with a keynote by Berkeley’s Chenming Hu who will talk about compact modeling as well as tri-gate scaled reliability challenges. Krishnan said that compact modeling is one of the main themes of this year’s conference. “There has been a lot of work on how do we take reliability into the circuits and how do we model, not only at the SPICE level, but from a compact modeling perspective,” he said. The Compact Modeling Council will have a meeting immediately following IRPS at the same location. Tuesday’s keynote is followed by 19 sessions in three tracks, with a panel session, workshop and a combined poster session and buffet at Chateau Julien wine estate on Wednesday evening.

In terms of the overall reliability concerns now facing the industry, Krishnan said the number one thing people are worried about is the tri-gate finFET. “Our devices have been planar but now all of the sudden you have three sides to it. How do you reject the heat from a finFET?” he asks. “The second concern is basically electromigration. How do we scale EM?” The third main challenge lies in gallium nitride and HEMT structures. “What is the reliability of these GaN FETs in the field when you have some of these trapping effects that go on?” Krishnan asks. “The switch is good on day one but it slowly degrades over time. That’s why you’re seeing a lot on GaN FETs.”

A few examples that will be presented at this year’s IRPS will serve to highlight the reliability issues facing the industry.

Reliability in memories

Researchers from Mila Polytechnic, Micron and Intel will present a paper titled “Resolving Discrete Emission Events: a New Perspective for Detrapping Investigation in NAND Flash Memories.” Charlie Slayman, IRPS Vice Technical Program Chair, said that researchers looked at the effects of individual discrete traps in the tunnel oxide for 30nm NAND flash. “Looking at the threshold voltage over time, you can actually see the threshold voltage change in discrete quantized steps. They’ve analyzed this and determined these are individual traps in the device that are trapping and detrapping. This will have an impact on future flash technologies where single electron and defects become increasingly important,” Slayman said.
In a second paper on resistive RAM, authors are from Minatec and coauthors from the Center for Semiconductor Components at the University of Campinas Brazil and the department of electrical engineering at Stanford studied the retention time — the ability of a resistive RAM device to maintain its resistance state. The RAM consists of two metal electrodes and a hafnium oxide between those, where the hafnium oxide acts as a variable resistor. The authors look at the use of different metal materials. In one case they use platinum for the electrode, and in a second example they use a TiN-Ti to sandwich the hafnium oxide. They showed that the Pt/Pt electrode device loses its on-state resistance sooner than the TiN/Ti device. “They attribute the phenomenon to oxygen interstitials in the HfO2, and TiN-Ti’s ability to basically getter those interstitials and pin them at the surface,” Slayman said. This is illustrated in FIGURE 1.

Figure 1. Atomistic structure of HfO2 with an Oi intersitials leading the the recombination of Oi+Vo in Pt/Pt during reset (left). Atomistic structure of Ti awith an Oi interstitial creating more Vo in HfO2 (right).

A third paper on memory focuses on flash, specifically erratic bit classification in flash devices used in automotive applications. The authors studied error correction code and redundant addresses, both of which are widely used in flash as well as SRAM and DRAM memory. “What’s new with this paper is the authors have classified these erratic or bad bits,” Slayman said. FIGURE 2 shows three different types of erratic bits and their behavior over time. “In the first case, they are looking at the read current of one type of erratic bit where it will periodically spike to a higher read current. Then there’s another type of erratic bit they observed where about half the time, it’s in a low read current state and the other half of the time it’s in a high read current state. Then they have a third class of erratic bits where it’s just going back and forth constantly between the high read state and the low read state,” Slaymain explained.

Figure 2. Examples of different erratic bit signatures (left). Normal and erract states are highlighted for clarity. Erratic bits percentage per signature classification in delay time cycling experiments are shown on the right.

Typically, redundant address repair would be used when these bad bits are created, after so many read-write cycles, but that can be an expensive fix. “For a certain class of bad bits — such as the erratic bits on the top of Fig. 3, that are most of the time good and only infrequently bad — don’t bother using redundant address, just use your error correction code and that’s sufficient,” Slayman said. “Save your redundant addresses for the really bad erratic bits.” The authors demonstrated that they can save 35% of their redundancy space by using this classification scheme.

FinFET concerns

At the device level, Giuseppe Larosa, IRPS Technical Program Chair, said the focus in squarely on FinFETs. “For future nodes, 14nm and down to 10nm, FinFETs will be the device design of choice,” he said.

Larosa said one of the key questions people ask is how BTI is actually scaling when we go to finFETs. “Key information is coming from Intel, suggesting that NBTI seems to be an issue because it’s increasing with finFET scaling.” At IRPS, Intel will present a comparison of 32nm planar technology to a 22nm finFET technology, as shown in FIGURE 3 (32 in red and 22nm in blue). “You can see they can manage to really reduce the PBTI but the NBTI is actually getting worse with scaling,” he said.

Figure 3. 22nm BTI is comparable to 32nm. NMOS is significantly improved due to gate optimization and WF scaling. The second item on the list for finFETs is self-heating. "Self-heating is always there," said Larosa. "Anytime you drive current through a channel you produce some self-heating. But if you have a bulk technology, the self-heating will just move away down into the bulk. But in finFETs, because it's a three-dimensional structure, this self-heating is a bottleneck in scaling down."

Another Intel paper talks about the effect of self-heating in accelerating aging, not only at the level of the device in terms of finFETS, but also in terms of metal wires that are sitting on top of the finFET. “You may have some impact on electromigration in the metal wires. You can have enhanced electromigration simply because the self-heating of the finFET can locally increase the temperature in the metal wires above,” Larosa explained. “A key issue here is how to calibrate the self-heating to make sure that you have a good understanding of the local temperature of the structure, and then how to take that into account in your models that predict end-of-life aging, specifically finFETs and metal lines,” he said.

Figure 4. Self-heat manifests as a sensitivity to the fin or gate count in switching aging degradation. Here, switching conditions are accelerated to enhance the sensitivity.

FIGURE 4 shows how self-heating at the device level is affecting aging of a given FET: It’s a function of the number of fins and the number of active lines per transistor. “It looks like through optimization of the gate stack with appropriate oxide scaling and metal gate work function tuning and so on, you can achieve reliability similar to previous nodes,” Larosa said.
Another reliability concern to be discussed at IRPS: High-k dielectrics. “There are two aspects of high k dielectrics that people have to face,” Larosa said. “BTI is again a concern with continued scaling. Contrary to nitride oxides, high-k bring a higher sensitivity to the NFET devices to PBTI. This is mostly due to the fact that the high-k material can be sensitive to electron trap activation or generation, producing PBTI effects that you will not see in standard nitride oxide technologies.”
At IRPS, GLOBALFOUNDRIES will present the first large-scale stochastic BTI (particularly PBTI) study in metal gate/high-k technology confirming fundamental BTI area scaling trends derived from conventional SiO2 technologies, and IBM will report on TDDB in high-k, and how it will lead to more accurate models. “Without this model you cannot be confident in predicting end of life, and having this type of simulation can help in making a projection that will be relevant for product level of circuit level reliability,” Larosa said.


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