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Posts Tagged ‘nanowires’

Solid State Watch: June 19-25, 2015

Friday, June 26th, 2015
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Scouting report for materials at end of the road: 2013 ITRS

Monday, May 12th, 2014

Ed Korczynski, Sr. Technical Editor, SST/SemiMD

The IC fabrication industry is approaching the end of the road for device miniaturization, with both atomic and economic limits looming on the horizon. New materials are widely considered as key to the future of profitable innovation in ICs, so everyone from process engineers to business pundits needs to examine the Emerging Research Materials (ERM) chapter of the just published 2013 edition of the International Technology Roadmap for Semiconductors (ITRS).

The 2013 ITRS covers both near-term (2014-2020) and long-term (2020 onward) perspectives on what materials and processes would be desired to build ideal ICs (Fig. 1, Table ERM15). However, to properly understand the information in the current edition we need to consider the changes in the IC fab industry since 1992 when the first edition of the ITRS’s predecessor was published as the U.S. National Technology Roadmap for Semiconductors (NTRS).

Fig. 1

Twenty-two years ago, the industry had dozens of fabs working on next-generation technology, and with lithographic scaling dominating innovation there was broad consensus on gradual materials evolutions. Today, the industry has 3 logic fabs and about as many memory lines pushing processes to smaller geometries, and each fab may use significantly different revolutionary materials. The result today is that there is little consensus on direction for new materials, and at best we can quantify the relative benefits of choosing one or another of the many options available.

In fact, with just a few players left in the game, there is much to lose for any one player to disclose strategic plans such as the use of revolutionary materials. Mark Thirsk, managing partner with specialty materials analysts Linx Consulting, commented, “We built our business based on anonymizing and generalizing the world, and then predicting the future based on big categorical buckets. But now there are a very few number of people pushing the boundaries and we’re being asked to model specific fab processes such as those for Intel or TSMC.”

For all of the above reasons, the current ITRS might be better understood as a scouting report that quantifies the roughness of the terrain when our current roads end. Exotic materials such as graphene and indium-gallium-phosphide may be used as alternate materials for the Si channels in transistors, novel stacks of atomic-layers may be used as electrical contacts, and spintronics and single-electron devices may one day replace DRAM and Flash chips for solid-state memory chips. However,  “significant challenges” exist in integrating any of these new technologies into high-volume manufacturing.

In the near-term, Cu wires clad with various metal barriers are projected to provide the best overall performance for on-chip interconnects.  As stated in the 2013 Executive Summary, “Unfortunately no new breakthroughs are reported for interconnections since no viable materials with resistivity below copper exist. However, progress in manipulation of edgeless wrapped materials (e.g., carbon nanotubes, graphene combinations etc.) offer the promise of ‘ballistic conductors,’ which may emerge in the next decade.”

Specialty Materials Suppliers

Fig. 2

Figure 2 (Figure ERM5) shows the inherent complexity involved in the stages of developing a new chemical precursor for use in commercial IC production. The chapter summarizes the intrinsic difficulty of atomic-scale R&D for future chips as follows:

A critical ERM factor for improving emerging devices, interconnects, and package technologies is the ability to characterize and control embedded interface properties. As features approach the nanometer scale, fundamental thermodynamic stability considerations and fluctuations may limit the ability to fabricate materials with tight dimensional distributions and controlled useful material properties.

In addition to daunting technical issues with pre-cursor R&D, the business model for chemical suppliers is being strained by industry consolidation and by dimensional shrinks. Consolidation means that each fab has unique pre-cursor requirements, so there may be just one customer for a requested chemistry and no ability to get a return on the investment if the customer decides to use a different approach.

Shrinks down to atomic dimensions means that just milliliters instead of liters of chemistry may be needed. For example, atomic-layer deposition (ALD) precursor R&D requires expertise and investment in molecular- and chemical-engineering, and so significant sunk costs to create any specialty molecule in research quantities. “We’ll have an explosion of precursors required based on proprietary IP held by different companies,” reminds Thirsk. “The people who are being asked to develop the supply-chain of ever increasing specifications are simultaneously being squeezed on margin and volumes.”

For materials such as Co, Ru, La, and Ti-alloys to be used in fabs we need to develop more than just deposition and metrology steps. We will also likely require atomic-level processes for cleaning and etch/CMP, which can trigger a need for yet another custom material solution.

Established chemical suppliers—such as Air Liquide, Dow, DuPont, Linde, Praxair, and SAFC—run international businesses serving many industries. IC manufacturing is just a small portion of their businesses, and they can afford to simply walk-away from the industry if the ROI seems unattractive. “We’re finding more and more that, for example in wet cleaning chemistry, the top line of the market is flat,” cautioned Thirsk. “You can find some specialty chemistries that provide better profits, but the dynamics of the market are such that there’s reduced volume and reduced profitability. So where will the innovation come from?”

Alternate Channel Materials

With finFETs and SOI now both capable of running in fully-depleted mode, alternative materials to strained silicon are being extensively explored to provide higher MOSFET performance at reduced power. Examples include III-V semiconductors, Ge, graphene, carbon nanotubes, and other semiconductor nanowires (NW). To achieve complimentary MOS high performance, co-integration of different materials (i.e. III-V and Ge) on Si may be necessary. Significant materials issues such as defect reduction, interface chemistry, metal contact resistivity, and process integration must be addressed before such improvements can be achieved.

Nano-wire transistors

Top down fabricated nanowires (NW) are one-dimensional structures that can be derived from two-dimensional finFETs. Patterned and etched <5nm Si NW have been reported to have room temperature quantum oscillatory behavior with back-gate voltage with a peak mobility approaching ∼900 cm2/Vs. Despite extensive R&D, grown Si NW demonstrate no performance improvements over patterned-and-etched NW, and controlled growth in desired locations remains extraordinarily challenging. Overall, significant challenges must be overcome for NW to be integrated in high density, particularly when targeting laterally placed NW with surround gates and low resistance contacts.

—E.K.

Research Alert: April 29, 2014

Tuesday, April 29th, 2014

Graphene not all good

In a first-of-its-kind study of how a material some think could transform the electronics industry moves in water, researchers at the University of California, Riverside Bourns College of Engineering found graphene oxide nanoparticles are very mobile in lakes or streams and therefore likely to cause negative environmental impacts if released.

Graphene oxide nanoparticles are an oxidized form of graphene, a single layer of carbon atoms prized for its strength, conductivity and flexibility. Applications for graphene include everything from cell phones and tablet computers to biomedical devices and solar panels.

The use of graphene and other carbon-based nanomaterials, such as carbon nanotubes, are growing rapidly. At the same time, recent studies have suggested graphene oxide may be toxic to humans.

As production of these nanomaterials increase, it is important for regulators, such as the Environmental Protection Agency, to understand their potential environmental impacts, said Jacob D. Lanphere, a UC Riverside graduate student who co-authored a just-published paper about graphene oxide nanoparticles transport in ground and surface water environments.

“The situation today is similar to where we were with chemicals and pharmaceuticals 30 years ago,” Lanphere said. “We just don’t know much about what happens when these engineered nanomaterials get into the ground or water. So we have to be proactive so we have the data available to promote sustainable applications of this technology in the future.”

The paper co-authored by Lanphere, “Stability and Transport of Graphene Oxide Nanoparticles in Groundwater and Surface Water,” was published in a special issue of the journal Environmental Engineering Science.

Other authors were: Sharon L. Walker, an associate professor and the John Babbage Chair in Environmental Engineering at UC Riverside; Brandon Rogers and Corey Luth, both undergraduate students working in Walker’s lab; and Carl H. Bolster, a research hydrologist with the U.S. Department of Agriculture in Bowling Green, Ky.

Walker’s lab is one of only a few in the country studying the environmental impact of graphene oxide. The research that led to the Environmental Engineering Science paper focused on understanding graphene oxide nanoparticles’ stability, or how well they hold together, and movement in groundwater versus surface water.

The researchers found significant differences.

In groundwater, which typically has a higher degree of hardness and a lower concentration of natural organic matter, the graphene oxide nanoparticles tended to become less stable and eventually settle out or be removed in subsurface environments.

In surface waters, where there is more organic material and less hardness, the nanoparticles remained stable and moved farther, especially in the subsurface layers of the water bodies.

The researchers also found that graphene oxide nanoparticles, despite being nearly flat, as opposed to spherical, like many other engineered nanoparticles, follow the same theories of stability and transport.

How to create nanowires only 3 atoms wide with an electron beam

Junhao Lin, a Vanderbilt University Ph.D. student and visiting scientist at Oak Ridge National Laboratory (ORNL), has found a way to use a finely focused beam of electrons to create some of the smallest wires ever made. The flexible metallic wires are only three atoms wide: One thousandth the width of the microscopic wires used to connect the transistors in today’s integrated circuits.

According to his advisor Sokrates Pantelides, University Distinguished Professor of Physics and Engineering at Vanderbilt University, and his collaborators at ORNL, the technique represents an exciting new way to manipulate matter at the nanoscale and should give a boost to efforts to create electronic circuits out of atomic monolayers, the thinnest possible form factor for solid objects.

“Junhao took this project and really ran with it,” said Pantelides.

Lin made the tiny wires from a special family of semiconducting materials that naturally form monolayers. These materials, called transition-metal dichalcogenides (TMDCs), are made by combining the metals molybdenum or tungsten with either sulfur or selenium. The best-known member of the family is molybdenum disulfide, a common mineral that is used as a solid lubricant.

Atomic monolayers are the object of considerable scientific interest these days because they tend to have a number of remarkable qualities, such as exceptional strength and flexibility, transparency and high electron mobility. This interest was sparked in 2004 by the discovery of an easy way to create graphene, an atomic-scale honeycomb lattice of carbon atoms that has exhibited a number of record-breaking properties, including strength, electricity and heat conduction. Despite graphene’s superlative properties, experts have had trouble converting them into useful devices, a process materials scientists call functionalization. So researchers have turned to other monolayer materials like the TMDCs.

Other research groups have already created functioning transistors and flash memory gates out of TMDC materials. So the discovery of how to make wires provides the means for interconnecting these basic elements. Next to the transistors, wiring is one of the most important parts of an integrated circuit. Although today’s integrated circuits (chips) are the size of a thumbnail, they contain more than 20 miles of copper wiring.

“This will likely stimulate a huge research interest in monolayer circuit design,” Lin said. “Because this technique uses electron irradiation, it can in principle be applicable to any kind of electron-based instrument, such as electron-beam lithography.”

One of the intriguing properties of monolayer circuitry is its toughness and flexibility. It is too early to predict what kinds of applications it will produce, but “If you let your imagination go, you can envision tablets and television displays that are as thin as a sheet of paper that you can roll up and stuff in your pocket or purse,” Pantelides commented.

In addition, Lin envisions that the new technique could make it possible to create three-dimensional circuits by stacking monolayers “like Lego blocks” and using electron beams to fabricate the wires that connect the stacked layers.

The nanowire fabrication was carried out at ORNL in the microscopy group that was headed until recently by Stephen J. Pennycook, as part of an ongoing Vanderbilt-ORNL collaboration that combines microscopy and theory to study complex materials systems. Junhao is a graduate student who pursues both theory and electron microscopy in his doctoral research. His primary microscopy mentor has been ORNL Wigner Fellow Wu Zhou.

“Junhao used a scanning transmission electron microscope (STEM) that is capable of focusing a beam of electrons down to a width of half an angstrom (about half the size of an atom) and aims this beam with exquisite precision,” Zhou said.

Graphene only as strong as weakest link

There is no disputing graphene is strong. But new research by Rice University and the Georgia Institute of Technology should prompt manufacturers to look a little deeper as they consider the miracle material for applications.

The atom-thick sheet of carbon discovered this century is touted not just for its electrical properties but also for its physical strength and flexibility. The bonds between carbon atoms are well known as the strongest in nature, so a perfect sheet of graphene should withstand just about anything. Reinforcing composite materials is among the material’s potential applications.

But materials scientists know perfection is hard to achieve. Researchers Jun Lou at Rice and Ting Zhu at Georgia Tech have measured the fracture toughness of imperfect graphene for the first time and found it to be somewhat brittle. While it’s still very useful, graphene is really only as strong as its weakest link, which they determined to be “substantially lower” than the intrinsic strength of graphene.

“Graphene has exceptional physical properties, but to use it in real applications, we have to understand the useful strength of large-area graphene, which is controlled by the fracture toughness,” Zhu said.

The researchers reported in the journal Nature Communications the results of tests in which they physically pulled graphene apart to see how much force it would take. Specifically, they wanted to see if graphene follows the century-old Griffith theory that quantifies the useful strength of brittle materials.

It does, Lou said. “Remarkably, in this case, thermodynamic energy still rules,” he said.

Imperfections in graphene drastically lessen its strength – with an upper limit of about 100 gigapascals (GPa) for perfect graphene previously measured by nanoindentation – according to physical testing at Rice and molecular dynamics simulations at Georgia Tech. That’s important for engineers to understand as they think about using graphene for flexible electronics, composite material and other applications in which stresses on microscopic flaws could lead to failure.

The Griffith criterion developed by a British engineer during World War I describes the relationship between the size of a crack in a material and the force required to make that crack grow. Ultimately, A.A. Griffith hoped to understand why brittle materials fail.

Graphene, it turns out, is no different from the glass fibers Griffith tested.

“Everybody thinks the carbon-carbon bond is the strongest bond in nature, so the material must be very good,” Lou said. “But that’s not true anymore, once you have those defects. The larger the sheet, the higher the probability of defects. That’s well known in the ceramic community.”

A defect can be as small as an atom missing from the hexagonal lattice of graphene. But for a real-world test, the researchers had to make a defect of their own – a pre-crack – they could actually see. “We know there will be pinholes and other defects in graphene,” he said. “The pre-crack overshadows those defects to become the weakest spot, so I know exactly where the fracture will happen when we pull it.

“The material resistance to the crack growth – the fracture toughness – is what we’re measuring here, and that’s a very important engineering property,” he said.

Just setting up the experiment required several years of work to overcome technical difficulties, Lou said. To suspend it on a tiny cantilever spring stage similar to an atomic force microscopy (AFM) probe, a graphene sheet had to be clean and dry so it would adhere (via van der Waals force) to the stage without compromising the stage movement necessary for the testing. Once mounted, the researchers used a focused ion beam to cut a pre-crack less than 10 percent of the width into the microns-wide section of suspended graphene. Then they pulled the graphene in half, measuring the force required.

While the Rice team was working on the experiment, Zhu and his team performed computer simulations to understand the entire fracture process.

“We can directly simulate the whole deformation process by tracking the motion and displacement with atomic-scale resolution in fairly large samples so our results can be directly correlated with the experiment,” said Zhu. “The modeling is tightly coupled with the experiments.”

The combination of modeling and experiment provides a level of detail that allowed the researchers to better understand the fracture process – and the tradeoff between toughness and strength in the graphene. What the scientists have learned in the research points out the importance of fabricating high-quality graphene sheets without defects, which could set the stage for fracture.

“Understanding the tradeoff between strength and toughness provides important insights for the future utilization of graphene in structural and functional applications,” Zhu added. “This research provides a foundational framework for further study of the mechanical properties of graphene.”

Lou said the techniques they used should work for any two-dimensional material. “It’s important to understand how defects will affect the handling, processing and manufacture of these materials,” he said. “Our work should open up new directions for testing the mechanical properties of 2-D materials.”

A Review of Recent Advances in Electronic Devices

Wednesday, October 10th, 2012

By Pete Singer

Highlights from recent and upcoming conferences point to a bright future for traditional and emerging electronics, based on silicon, flexible substrates, graphene and nanowires.

The FinFET has grabbed the limelight when it comes to next-generation electronics, and further advances continue to be made, particularly by Intel. At the upcoming International Electron Devices Meeting (IEDM)in December, the company plans to show how they have developed a complete platform for system-on-chip (SoC). But that’s just one of the exciting announcements to come from IEDM and other conferences, such as the VLSI Symposium held in June.

Tremendous advancements have been made in building advanced circuits on flexible substrates, for example, which could some day lead to roll-to-roll processing of ICs. To date, flexible circuits have offered limited performance because plastic substrates aren’t compatible with the high temperatures and harsh processes needed to make high-performance CMOS devices. At IEDM, for the first time, a way around this will be unveiled. IBM researchers will demonstrate high-performance state-of-the-art CMOS circuits, including SRAM memory and ring oscillators on a flexible plastic substrate.
IBM used extremely thin silicon on insulator (ETSOI) devices, with a body thickness of just 60 angstroms. IBM built them on silicon and then used a simple, low-cost room-temperature process called controlled spalling. Then they transferred them to flexible plastic tape.

The devices had gate lengths of <30nm and gate pitch of 100nm. The ring oscillators had a stage delay of just 16ps at 0.9V, believed to be the best reported performance for a flexible circuit.

imec, the Belgium-based consortium, also recently announced that it has integrated an ultra-thin, flexible chip with bendable and stretchable interconnects into a package that adapts dynamically to curving and bending surfaces. The resulting circuitry can be embedded in medical and lifestyle applications where user comfort and unobtrusiveness is key, such as wearable health monitors or smart clothing.

New flavors of FinFETS

Multiple-gate transistors, such as the FinFET (or “trigate” transistors as known by Intel) provide superior on/off control, enabling high drive currents to be achieved at a lower supply voltage than otherwise. At IEDM, Intel will discuss how it developed several FinFET “families” of high-speed, low-standby-power and high-voltage-tolerant devices, combined with state-of-the-art interconnects and RF/mixed-signal features for a wide range of SoC applications.

The high-speed logic transistors have subthreshold leakages ranging from 100nA/m to 1nA/m, while the low-power versions feature leakage of < 50pA/m yet have drive currents 50% higher than 32nm planar (traditional technology) devices. The process also yields high-voltage transistors (1.8V or 3.3V) for analog circuits, I/O, legacy designs and other applications. They feature the highest reported I/O device drive currents for an SoC technology (NMOS/PMOS=0.92/0.8mA/m at 1.8V). The trigate technology platform also features eight to 11 layers of low-k and ultra-low-k carbon-doped oxide (CDO) interconnect at tight pitches for different applications; many analog/mixed-signal features; and three different SRAM bit cells, spanning high-density/low-leakage (0.092m2), low voltage (0.108m2) and high-performance (0.130m2).

ETSOI

Another exciting development in the transistor world is extremely thin SOI (ETSOI) technology, which is quickly emerging as a viable device architecture for continued CMOS scaling to 22nm and beyond. It offers superior short-channel control and low device variability with undoped channels. At the IEDM, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device (Figure 3). They integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. A novel STI-last process makes the hybrid architecture possible. The researchers built a ring oscillator circuit to benchmark performance, and the hybrid planar devices enabled the fastest ring oscillator ever reported, with a delay of only 11.2ps/stage at 0.7V, even better than FinFETs.

Future memories

While conventional charge-based memory is approaching fundamental scaling limits, several so-called “emerging memories” have migrated from laboratory samples to integrated products. Among various emerging memory technologies, MRAM (magnetoresistive random access memory) has been making impressive progress, ahead of other emerging memories, and has demonstrated the capability to be a successor to DRAM or SRAM. MRAM data is stored via magnetic moments. Parallel or anti-parallel magnetic moments in MRAM stacks present the “0″ or “1″ state. In earlier generations of MRAM, these states were switched by current-induced magnetic field but that is an obstacle for scaling. The invention of ST (spin-torque) MRAM, which is switched by injecting spin-polarized tunneling current, removes the scaling limitation. At IEDM, in an invited paper, researchers from Everspin Technologies will describe how they built the largest functional ST-MRAM circuit ever built, a 64Mb device with good electrical characteristics. The work shows that MRAM technology is fast approaching commercialization.

Earlier this year, at the VLSI Technology Symposium (Honolulu, Hawaii), imec presented significant improvements in performance and reliability for a type of non-volatile called resistive RAM (RRAM).

RRAM is a promising concept for future non-volatile memories because of its high speed, low energy operation, superior scalability, and compatibility with CMOS technology. Its operation relies on the voltage controlled resistance change of a conductive filament in the dielectric of a Metal/Insulator/Metal (MIM) stack. RRAM systems based on HfO2 have been demonstrated to have excellent scaling capabilities (area <10x10nm) and strong reliability due to efficient voltage-controlled management of oxygen motion in the stack during switching.

Progress in more conventional memory technology also continues, particularly in 3D memories. At IEDM, the first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers. They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction and improves manufacturability. The new architecture also enables the use of a novel “staircase” bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75nm, 64 cells per string and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional sub-20nm 2D NAND, but it can provide 1 Tb of memory if further scaled to 25nm feature sizes. At that size the Macronix device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density.

Graphene, MoS and nanowires

No discussion of emerging electronics would be complete without an update on graphene, and an exciting alternative. Graphene is seen as a potential replacement for silicon in future transistors because it has an exceptional set of properties (high current density, mobility and saturation velocity). However, transistors made of graphene cannot be turned off because graphene has almost no band gap. Researchers have begun to investigate a new 2D material molybdenum sulfide (MoS) which has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly. At IEDM, an MIT-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter). The transistors demonstrated record MoS mobility (>190cm2/Vs), an ultra-high on/off current ratio of 108, record current density (~20A/m) and saturation, and the first GHz RF performance from MoS.
Another important development to be unveiled at IEDM: The phenomenon of ambipolar conduction (the ability to switch between N- or P-type), which has been observed in some nanoscale transistors made from silicon, carbon and graphene. A team led by researchers from the Swiss Federal Institute of Technology in Lausanne (EPFL) built gate-all-around ambipolar Si nanowire FETs in a vertically stacked configuration on an SOI substrate. A “polarity gate” attached to the ends of the nanowires is used to switch their polarity dynamically between the N and P states, while a control gate in the middle turns them on or off. The devices showed an excellent on/off current ratio of 106 and subthreshold slope of 70mV/dec. The researchers built a logic gate to show the technique’s usefulness for future logic design.


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