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Posts Tagged ‘multiple patterning’

What’s the Next-Gen Litho Tech? Maybe All of Them

Thursday, February 25th, 2016

By Jeff Dorsch, Contributing Editor

The annual SPIE Advanced Lithography symposium in San Jose, Calif., hasn’t offered a clear winner in the next-generation lithography race. It’s becoming clearer, however, that 193i immersion and extreme-ultraviolet lithography will co-exist in the future, while directed self-assembly, nanoimprint lithography, and maybe even electron-beam direct-write technology will fit into the picture, too.

At the same time, plasma deposition and etching processes are assuming a greater interdependence with 193i, especially when it comes to multiple patterning, such as self-aligned double patterning, self-aligned quadruple patterning, and self-aligned octuple patterning (yes, there is such a thing!).

“We’ve got to go down to the sub-nanometer level,” Richard Gottscho, Lam Research’s executive vice president of global products, said Monday morning in his plenary presentation at the conference. “We must reduce the variability in multiple patterning,” he added.

Gottscho touted the benefits of atomic level processing in continuing to shrink IC dimensions. Atomic level deposition has been in volume production for a decade or more, he noted, and atomic level etching is emerging as an increasingly useful technology.

When it comes to EUV, “it’s a matter of when, not if,” the Lam executive commented. “EUV will be complementary with 193i.”

Anthony Yen, director of nanopatterning technology in the Infrastructure Division of Taiwan Semiconductor Manufacturing, followed Gottscho in the plenary session. “The fat lady hasn’t sung yet, but she’s on the stage,” he said of EUV.

Harry Levinson, senior director of GlobalFoundries, gave the opening plenary presentation, with the topic of “Evolution in the Concentration of Activities in Lithography.” He was asked after his presentation, “When is the end?” Levinson replied, “We’re definitely not going to get sub-atomic.”

With that limit in mind, dozens of papers were presented this week on what may happen before the semiconductor industry hits the sub-atomic wall.

There were seven conferences within the symposium, on specific subjects, along with a day of classes, an interactive poster session, and a two-day exhibition.

The Alternative Lithographic Technologies conference was heavy on directed self-assembly and nanoimprint lithography papers, while also offering glimpses at patterning with tilted ion implantation and multiphoton laser ablation lithography.

“Patterning is the battleground,” said David Fried, Coventor’s chief technology officer, semiconductor, in an interview at the SPIE conference. He described directed self-assembly as “an enabler for optical lithography.”

Mattan Kamon of Coventor presented a paper on Wednesday afternoon on “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node.”

DSA could be used in conjunction with SAQP or LELELELE, according to Fried. While some lithography experts remain leery or skeptical about using DSA in high-volume manufacturing, the Coventor CTO is a proponent of the technology’s potential.

“Unit process models in DSA are not far-fetched,” he said. “I think they’re pretty close.  The challenges of EUV are well understood. DSA challenges are a little less clear. There’s no ‘one solution fits all’ with DSA.” Fried added, “There are places where DSA can still win.”

Franklin Kalk, executive vice president of technology for Toppan Photomasks, is open to the idea of DSA and imprint lithography joining EUV and immersion in the lithography mix. “It will be some combination,” he said in an interview, while adding, “It’s a dog’s breakfast of technologies. Don’t ever count anything out.”

Richard Wise, Lam’s technical managing director in the company’s Patterning, Global Products Groups CTO Office, said EUV, when ready, will likely be complementary with multipatterning for 7 nanometer.

Self-aligning quadruple patterning, for example, was once considered “insanity” in the industry, yet it is a proven production technology now, he said.

While EUV technology is “very focused on one company,” ASML Holding, there is a consensus at SPIE that EUV’s moment is at hand, Wise said. Intel’s endorsement of the technology and dedication to advancing it speaks volumes of EUV’s potential, he asserted.

“Lam’s always excelled in lot-to-lot control,” an area of significant concern, Wise said, especially with all of this week’s talk about process variability.

What will be the final verdict on the future of lithography technology? Stay tuned.

Overlay Metrology Suite for Multiple Patterning

Tuesday, August 26th, 2014

By Ed Korczynski, Sr. Technical Editor

Today, KLA-Tencor Corporation (NASDAQ: KLAC) released two metrology tools and an upgraded data analysis system that can reduce overlay error by 25% when using multi-patterning in leading-edge IC fabs. By taking additional data and using feed-forward control loops, the integrated solution dynamically adjusts the exposures in lithographic steppers to improve both overlay and critical dimension (CD) results in high-volume manufacturing (HVM). The suite of tools has passed beta-site evaluations with fab customers.

“Feed-forward has been used at gate CD to control variations, mostly controlling the Z-dimension of deposition and etch. But this is using feed-forward to control the 2D aspect of overlay.” explained Ady Levy, KLA-Tencor fellow, in an exclusive interview with Solid State Technology and SemiMD. “With the absence of traditional lithography scaling, customers are developing 3D structures that are using other parts of the fab.”

Figure 1 shows an analysis of the origin of patterning errors for Litho-Etch-Litho-Etch (LELE) double-patterning, indicating that traditional lithography processes account for just ~40% of the errors. Most multi-patterning errors originate with the deposition and etching and chemical-mechanical planarization (CMP) of films, inducing wafer-shape variations and thickness non-uniformities.

Fig. 1

The company’s WaferSight™ Patterned Wafer Geometry (PWG) measurement tool is an extension of the WaferSight line to measure bow and warp and other surface non-uniformities on unpatterned wafers, with the added ability to measure both sides to provide data on thickness variations. By incorporating industry-unique vertical wafer hold to minimize gravitational distortion and a sampling density of 3.5 million data points per wafer, the new tool produces highly accurate wafer shape data. “By feeding forward this information we can then correct the exposure on the scanner and correct for the induced overlay error due to stress from a prior process step,” elaborated Levy.

Brunner et al. (Optical Microlithography XXVII, Proc. of SPIE, Vol. 9052, 90520U, 2014) from IBM recently showed the quantified benefits of using PWG feed-forward (PWG-FF) information in stepper exposures to correct for across-wafer stress variation. Stress Monitor Wafers showed overlay errors dominated by wafer distortion effects, with six-times greater distribution of errors compared to distortion-free wafers. Table 1 compares standard linear alignment with High Order Wafer Alignment (HOWA) and with PWG-FF alignment, the latter provides the best results without requiring the slower processing of HOWA.

Proprietary model-based metrology allows the LMS IPRO6 to accurately measure reticle registration for on-device pattern features, as well as standard registration marks for significantly higher sampling. With faster measurement time than its predecessor, the LMS IPRO6 supports measuring the increased number of reticles associated with innovative multi-patterning techniques. The LMS IPRO6 enables generation of pattern-dependent registration error data that improves feedback to the e-beam mask writer, and can be fed forward to the fab’s lithography module for feature-optimized scanner corrections that improve wafer-level patterning.

The K-T Analyzer 9.0 is the latest version of the company’s platform that enables advanced, run-time data analysis for a wide range of metrology system types. Though the company fields a wide portfolio of products, KLA-Tencor doesn’t provide all inspection and metrology tools needed to control a commercial HVM fab line, and so the company provides software loaders to allow data from other tools to be integrated. The data analysis platform upgrade includes in-line methods for calculating scanner corrections per exposure on an on-product, lot-by-lot basis that maintains high accuracy without requiring full wafer measurement data—a production-capable control technique that can reduce pattern overlay error. In addition, the platform includes new scanner fleet management, scanner data analysis, and scanner alignment optimization capabilities.

All of this allows commercial HVM fabs to push the limits of patterning resolution for complex next-generation logic ICs. “Within the lithography module, our Archer™ 500 overlay and SpectraShape™ 9000 CD advanced metrology systems identify and monitor patterning errors,” said Ahmad Khan, group vice president of KLA-Tencor’s Parametric Solutions Group. “Extending beyond the lithography cell, our new WaferSight PWG and LMS IPRO6 systems isolate additional process- or reticle-related sources of patterning errors. These fab-wide, comprehensive measurements, supported by K-T Analyzer 9.0’s flexible data analysis, expand the process window and enable improved production patterning control for our customers’ leading-edge devices.”

—E.K.