by Ed Korczynski
Resistance-change Random Access Memory (RRAM or ReRAM) devices continue to be developed at labs and fabs around the world, as seen by more than 40 papers at the spring Materials Research Society (MRS) spring meeting which was held April 25-29 in San Francisco, California. RRAMs are based on resistive switching in metal oxides, such as titantia and niobia, that show memristor properties. With single-digit nanosecond switching-speeds and 10-year non-volatile data retention, RRAMs may represent the future of solid-state memory after DRAM and Flash devices eventually reach scaling limits below 22nm half-pitch.
Technically, the other devices competing with RRAM for the future of memory are themselves based on changes in resistance. Phase-change memory (PCM) using GST material switches between low- and high-resistance states, but requires large drive currents to heat the material to effect the phase-change. Spin-transfer-torque RAM (STT-RAM) is also read as a change in resistance, but the cell size is relatively large. RRAM devices built using cross-point arrays could provide the smallest, fastest, leanest, and cheapest non-volatile memory chips.
Between oral presentations and posters, the Spring 2011 MRS Meeting showed many different groups using different switching materials for RRAMs:
8 – TiO
7 – NiO
6 – Zn0:metal
4 – SiO:Cu
3 – HfO:metal
3 – TMO:metal
3 – polymers
2 – TaO
2 – SrTiO
1 – CuO
1 – HfSiO
1 – WO
1 – solid electrolyte
42 + 11 more novel materials in session Q10
= 53 total RRAM presentations.
HP Labs RRAM Update
Stan Williams’ group at HP Labs has led the world in memristor and RRAM R&D using the titania family of materials as the switch since 2006. They claim that their champion device switches in <2ns, and has world-record endurance of >1.2E10 cycles. Stan Williams provided a keynote address to an MRS workshop last year, in which he explained how his group finally discovered that the conducting channel consists of a 1-2nm thin TiO2 tunnel barrier adjacent to a ~30nm thick “magneli-phase” Ti4O7 layer. Modulating the width of the tunnel barrier through diffusion of oxygen-vacancies controls the electrical resistance of the stack.
This year, HP Labs updated their titania work by reporting on two different electroforming mechanisms seen in the same 50nm × 50nm crossbar memristive device. A “soft” electroforming step uses <140µAmp at ~5V to create a high-resistance mode, while a “hard” electroforming step uses ~250µAmp at ~9V to create a low resistance mode. The two switching modes possessed opposite switching polarities that shared a metastable intermediate resistance state. The two modes can be explained by two switching layers at the top- and bottom-electrode interfaces:
- intermediate state, the bottom layer is ON with conducting channels made of both oxygen-vacancies and charge-traps, while the top layer consists of a tunnel gap;
- OFF state, both layers consist of tunnel gaps; and
- ON state, the top layer is ON with conducting channels made of oxygen-vacancies, while the bottom layer consists of a tunnel gap.
J. Joshua (Jianhua) Yang, provided an update on HP Labs’s RRAM work by surprisingly stating that titanium-oxides have stability issues which may limit device lifetimes, but that tantalum-oxides are free of such issue. The titania family seems to show issues getting beyond 100-1000 cycles, due to excessive heating inside the switch material due to the tendency to apply overvoltage. The two phases of titania will react with each other during heating, so the ON/OFF resistance differences are not so stable. “You need stability, and larger oxygen stability in the materials,” explained Yang. Presumably, the world-record cycling performance using titania was achieved using careful limits on overvoltage.
To improve lifetime with overvoltage margin, HP now uses a tantalum-oxide switching layer, a platinum bottom-electrode, and a tantalum top-electrode. The company claims that this system should be scalable to <5nm, the switching speed is merely 5ns, and the resistance state should be stable for 10 years. TaOx as deposited is amorphous, and even after heating steps it may retain some amorphous character.
RRAM Electroforming Avoidance
The ability to create functional RRAMs without electroforming would provide a significant cost and yield advantage in manufacturing. Though there is still debate as to the exact nature of the solid-state ion-diffusion mechanism(s) responsible for the change in resistance, it is clear that proper stacks of nano-scale oxides and sub-oxides are needed. Consequently, once trial-and-error has identified an ideal materials stack, it is likely that a wafer-scale process flow will be found to create the desired stack without the need for electroforming. For example, annealing in a reducing ambient or solid-phase gettering techniques may be used to adjust the stoichiometry of thin-films.
Using a tungsten-plug from a 90nm node DRAM process flow as one electrode, researchers from Research Center Juelich (with funding from Intel) used TiO2 thickness of 25nm and a Pt/Ti top electrode to make inherently electroforming-free RRAMs (Session Q8.4). Initially the devices were found to be in an intermediate state, and can be SET with positive bias voltage to the low resistance state (LRS). Without bias the intermediate state undergoes a RESET process to a high resistance state (HRS). Under negative voltage bias both processes can be reversed and the device returns into the intermediate state. This flipping of the SET and RESET process from positive to negative bias voltage polarity and vice versa can repeatedly be adjusted in one device. This versatile switching scenario is possible due to the use of the low-workfunction Ti and W electrodes which result in low barriers to the oxide.
The Juelich process flow is as follows:
- Plasma etch to clean the W plug,
- Reactive sputter TiO2 (300W, 46sccm AR, 17 sccm O2), and
- PVD of top-electrode.
The top-electrode was 30nm Pt with an optional 5nm layer of Ti or W below. “As long as there is a Pt/TiO2 interface we need forming,” explained Rainer Bruchhaus of Juelich. However, when using either W or Ti as a barrier between the Pt and TiO2 (while maintaining W as bottom electrode) they see no need for electroforming. In all cases, the voltage range is limited to +- 1V.
Much of the global interest in RRAM structures is due to the ability of cross-point memory architectures to be shrunk far more easily than other device structures. The process flow to make cross-point arrays is particularly attractive from an overlay perspective, since the top- and bottom-electrodes are perpendicular to each other and the switching material is patterned along with the top-electrode.
The world record for the smallest resistive memory element is currently held by the National Nano Device Laboratories (NNDL) in Taiwan, which showed a 9nm half-pitch functional RRAM at IEDM last December (Paper #19.1, “9nm Half-Pitch Functional Resistive Memory Cell with <1 µA Programming Current Using Thermally Oxidized Sub-Stochiometric WOx Film,” C. Ho et al, National Nano Device Laboratories, Taiwan/University of California at Berkeley). It features the lowest reported programming current to date of just <1µA using tungsten-oxide, compared to ~20mA for phase-change memories. The device was built using nano-injection lithography which employs a chemical reaction activated with a finely controlled electron beam to deposit a hard-mask for etching, but could have used Nano-imprint Lithography (NIL) or other patterning to form the array.
For more details on the physics of these devices, Applied Physics A, Vol.A102, No.4 is a special issue on “Memristive and Resistive Devices and Systems,” and is now available for free download as individual PDFs.