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Posts Tagged ‘MRAM’

Emerging Memory Types Headed for Volumes

Wednesday, July 18th, 2018

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By David Lammers

After decades of R&D, two emerging memory types – the phase change memory-based 3D Xpoint, co-developed by Intel and Micron, and the embedded spin-torque transfer magnetic RAM (e-MRAM) from several foundries – are now coming to the market. One point of interest is that neither memory type relies on the charge-based SRAM and DRAM memory technologies that increasingly face difficult scaling challenges. Another is that both have inherent performance advantages that could extend their uses for decades to come.

3D XPoint is a storage class memory (SCM) based on phase-change that fits in between fast DRAM and non-volatile NAND; it is currently available in both SSDs and sampling in a DIMM form factor. David Kanter, an analyst at Real World Technologies (San Francisco) said the Optane SSDs are selling now but the DIMMs are shaping up to be “an early 2019 story” in terms of real adoption. “People are very excited about the DIMMs, including customers, software developers, the whole computer ecosystem. There is a lot of software development going on that is required to take advantage of it, and a lot of system companies are saying they can’t wait. They are telling Intel ‘give me the hardware.’”

“Intel is taking the long view” when it comes to 3D XPoint (the individual devices) and Optane (the SSDs and DIMMs), Kanter said. “This is a new technology and it is not a trivial thing to bring it to the market. It is a testament to Intel that they are taking their time to properly develop the ecosystem.”

However, Kanter said there is not enough public information about 3D XPoint DIMMs, including performance, price, power consumption, and other metrics. Companies that sell enterprise database systems, such as IBM, Microsoft, Oracle, SAP, and others, are willing to pay high prices for a storage-class memory solution that will improve their performance.The Optane DIMMs, according to Intel, are well-suited to “large-capacity in-memory database solutions.”

According to the Intel Web site, Optane DC persistent memory “is sampling today and will ship for revenue to select customers later this year, with broad availability in 2019.” It can be placed on a DDR4 module alongside DRAM, and matched up with next-generation Xeon processors. Intel is offering developers remote access to systems equipped with Optane memory for software development and testing.

Octane DIMM reaches ‘broad availability’ in 2019

Speaking at the Symposium on VLSI Technology in Honolulu, Gary Tressler, a distinguished engineer at IBM Systems, said “the reliability of 3D NAND impacts the enterprise,” and predicted that the Optane storage class memory will serve to improve enterprise-class systems in terms of reliability and performance.

The DRAM scaling picture is not particularly bright. Tressler said “it could be four years before we go beyond the 16-gigabit size in terms of DRAM density.” DRAM companies are eking out scaling improvements of 1nm increments,” an indication of the physical limitations facing the established DRAM makers.

Al Fazio, a senior fellow at Intel who participated in the memory-related evening panel at the VLSI symposia, and said that the early adopters of the Optane technology have seen significant benefits: one IT manager told Fazio that by adding a layer of Optane SSD-based memory he was able to rebuild a database in seconds versus 17 minutes previously. Fazio said he takes particular pride in the fact that, because of Optane, some doctors are now able to immediately read the results of magnetic resonance imaging (MRI) tests.

“An MRI now takes two minutes instead of 40 minutes to render,” Fazio said, adding that a second-generation of 3D Xpoint is being developed which he said draws upon “materials improvements” to enhance performance.

Chris Petti, a senior director of advanced technology at Western Digital, said DRAM pricing has been “flat for the last five to seven years,” making it more expensive to simply add more DRAM to overcome the latency gap between DRAM and flash. “DRAM is not scaling so there are a lot of opportunities for a new technology” such as Optane or the fast NAND technologies, he said. Samsung is working on a single-bit-per-cell form of Fast NAND.

In a Monday short course on emerging memory technologies at the Symposium on VLSI Circuits, Petti said the drawback to phase change memories (PCMs), such as 3D XPoint, is the relatively high write-energy-per-bit, which he estimated at 460 pJ/bit, compared with 250 pJ/bit for standard NAND (based on product spec sheets). In terms of cost, latency, and endurance, Petti judged the PCM memories to be in the “acceptable” range. While the price is five to six times the price-per-bit of standard NAND, Petti noted that the speed improves “because PCM (phase change memory) is inherently faster than charge storage.”

Source: Chris Petti, Western Digital, short course presentation at 2018 Symposium on VLSI Circuits

Phase-change materials, such as Ge2Sb2Te5, change between two different atomic structures, each of which has a different electronic state. A crystalline structure allows electrons to flow while an amorphous structure blocks the flow. The two states are changed by heating the PCM bit electrically.

Philip Wong, a Stanford University professor, said the available literature on PCM materials shows that they can be extremely fast; the latencies at the SSD and DIMM levels are largely governed by “protocols.” In 2016, a team of Stanford researchers said the fundamental properties of phase-change materials could be as much as a thousand times faster than DRAM.

In a keynote speech at the VLSI symposia, Scott DeBoer, executive vice president of technology development at Micron (Boise, Idaho), said “clearly the most successful of the emerging memories is 3D XPoint, where the technology performance has been proven and volume production is underway. 3D XPoint performance and density are midway between DRAM and NAND, which offers opportunities to greatly enhance system-level performance by augmenting existing memory technologies or even directly replacing them in some applications.”

Currently, the 3D XPoint products are made at a fab in Lehigh, Utah. The initial technology stores 128Gb per die across two stacked memory layers. Future generations can either add more memory layers or use lithographic pitch scaling to increase die capacity, according to Micron.

DeBoer noted that “significant system-level enablement is required to exploit the full value of 3D XPoint memory, and this ongoing effort will take time to fully mature.”

eMRAM Race Begins by Major Foundries

Magnetic RAM technology has been under serious development for three decades, resolving significant hurdles along the way with breakthroughs in MgO magnetic materials and device architecture. Everspin Technology has been shipping discrete MRAM devices for nearly a decade, and the three major foundries are readying embedded MRAM for SoCs, automotive ICs, and other products. The initial target is to replace NOR-type flash on devices, largely due to the large charge pumps required to program NOR devices which add multiple mask layers.

GlobalFoundries, which manufactures the Everspin discrete devices, has qualified eMRAM for its 22nm FD-SOI process, called 22FDX. TSMC also has eMRAM plans.

At the Symposium on VLSI Technology, Samsung Foundry (Giheung, Korea) senior manager Yong Kyu Lee described an embedded STT-MRAM in a 28-nm FDSOI logic process, aimed at high-speed industrial MCU and IoT applications.

Interestingly, Lee said compared with the bulk (non-SOI) 28-nm process, the FD-SOI technology “has superior RF performance, low power, and better analog characteristics than 28-nm bulk and 14-nm FinFET CMOS.” Lee indicated that the FD-SOI-based eMRAM would be production-ready later this year.

Samsung ported its STT perpendicular-MTJ (magnetic tunnel junction) eMRAM technology from its 28-nm bulk to its FD-SOI CMOS process. The company offers the eMRAM as a module, complementing an RF module. The “merged embedded STT MRAM and RF-CMOS process is compatible to the existing logic process, enabling reuse of IP,” he said.

Looking forward to the day when MRAM could complement or replace SRAM, Lee said “even though we have not included data in this paper, our MTJ shows a potential for storage working memory due to high endurance (>1E10) and fast writing (<30ns).

Beyond Embedded to Last Level Cache

As foundries and their customers gain confidence in eMRAM’s retention, power consumption, and reliability, it will begin to replace NOR flash at the 40-nm, 28-nm, and smaller nodes. However, future engineering improvements are needed to tackle the SRAM-replacement.

SRAM scaling is proving increasingly difficult, both in terms of the minimum voltages required and the size of the six-transistor-based bits. MRAM researchers are in hot pursuit of the ability to use replace some of the SRAM on processors with Last Level Cache (LLC) iterations of magnetic memory. These LLC MRAMs would be fabricated at the 7nm, 5nm, or beyond nodes.

Mahendra Pakala, senior director of memory and materials at the Applied Materials Advanced Product Technology Development group, said for eMRAM the main challenges now are achieving high yields with less shorting between the magnetic tunnel junctions (MTJs). “The big foundries have been working through those problems, and embedded MRAM is getting closer to reality, ramping up sometime this year,” he said.

For LLC applications, STT-MRAM has approached SRAM and DRAM performance levels for small sample sizes. At the VLSI symposium, researchers from Applied Materials, Qualcomm, Samsung, and TDK-Headway, all presented work on SRAM cache-type MRAM devices with high performance, tight pitches, and relatively low write currents.

Applied’s VLSI symposium presentation was by Lin Xue, who said the LLC-type MRAM performance is largely controlled by the quality of the PVD-deposited layers in the MTJ, while yields are governed by the ability to etch the MTJ pillars efficiently. Etching is extremely challenging for the tight pitches required for SRAM replacement, since the tight-pitch MTJ pillars must be etched without redepositing material on the sidewalls.

Caption: Lin Xue, et al, Applied Materials presentation at 2018 Symposium on VLSI Technology

Deposition is also difficult. The MTJ structures contain multiple stacks of cobalt and platinum, and the thickness of the multilayers must be reduced to meet the 7nm node requirements.  Any roughness in the interfaces creates secondary effects which reduce perpendicular magnetic anisotropy (PMA). “The performance is coming from the interface, essentially. If you don’t make the interface sharp, you don’t end up with the expected improvement in PMA,” Pakala said.

Applied has optimized a PVD process for deposition of the 15-plus layers of many different materials required for the magnetic tunnel junctions. Pakala said the PVD technology can sputter more than 10 different materials. The Endura-based system uses a multi-cathode approach, enabling each chamber to have up to five targets. With a system of seven chambers, companies can deposit the required variety of materials and, if desired, increase throughput by doubling up on the targets.

The system would include a metrology capability, and because the materials are easily oxidized, the entire system operates at vacuum levels beyond the normal 10E-8 Torr level. For MRAM deposition, operating at 10 to minus 9 or even 10 to minus 10 Torr levels may be required.

“When we start talking about the 7 and 5 nanometer nodes for SRAM cache replacement, the cell size and distances between the bits becomes very small, less than 100 nm from one MTJ to another. When we get to such small distances, there are etching issues, mainly redepositing on the sidewalls. The challenge is: How do we etch at reduced pitch without shorting?” Pakala said.

“Integrated thermal treatment and metrology to measure the thicknesses, all of which has to be done at extremely low vacuum, are major requirements,” he said.

“At this point it is not a question of the basic physics. For MRAM, it is, as they say, ‘just engineering’ from here on out,” he said.

GlobalFoundries Turns the Corner

Friday, September 29th, 2017

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By David Lammers

Claiming that GlobalFoundries “is a different company than two years ago,” executives said the foundry’s strategies are starting to pay off in emerging markets such as 5G wireless, automotive, and high-performance processors.

CEO Sanjay Jha, speaking at the GlobalFoundries Technology Conference, held in Santa Clara, Calif. recently, said that to succeed in the foundry segment requires that customers “have confidence that they are going to get their wafers at the right time and with the right quality. That has taken time, but we are there.”

CEO Sanjay Jha: “differentiated” processes are key.

Innovation is another essential requirement for success, Jha said, arguing that R&D dollars must include spending on “differentiated” approaches. Alain Mutricy, senior vice president of product development, acknowledged that only recently have customers turned to GlobalFoundries as more than just a second-source to TSMC. For the first few years, “most companies used us to keep (wafer) prices down,” he said, while noting GlobalFoundries bears some responsibility for that by not investing nearly enough, early on, in IP libraries and EDA tool development.

Founded in March 2009 as a spinout of the manufacturing arm of Advanced Micro Devices, Global Foundries’ Abu Dhabi-based owner soon acquired Singapore’s Chartered Semiconductor in January 2010, and further expanded through the July 2015 acquisition of IBM Microelectronics. It is now engaged in building what Jha said will be the largest wafer fab in China, in Chengdu, capable of processing a million wafers a year. The Chengdu fab, operated by GlobalFoundries but with investments from the local government, will begin with 180nm and 130nm products now fabbed in Singapore, and then add 22FDX IC production to meet demand from Chinese customers.

While the road to profitability has been a hard one, Len Jelinek, chief technology analyst at HIS Markit, said GlobalFoundries is now “cash flow positive,” with the flagship Malta, N.Y. fab “essentially full” at an estimated 40,000 wafer starts per month. That is a big turnaround from four years ago, he said.

Malta fab’s capacity doubling

Nathan Brookwood, longtime microprocessor watcher at Insight64, said while AMD no longer has an ownership stake in GlobalFoundries, it does have wafer supply agreements with the foundry. The fact that AMD’s Zen-based microprocessors and newest graphics chips are all made on the 14nm Finfet process at Fab 8 “means that AMD is now actually using the wafer supply it is committed to taking. That helps both companies.”

Andrea Lati, director of market research at VLSI Research, said while TSMC “is clearly a very well-run company that is marching ahead,” GlobalFoundries also is making progress. Again, AMD’s success is a large part of that, Lati said, noting that “AMD is definitely doing very well for the last couple of years, and has good prospects, along with Nvidia, in the graphics side.”

In a telephone interview, Tom Caulfield, senior vice president and general manager of the GlobalFoundries’ Malta fab, said “we are continually adding capacity in 14nm as we get a window on to the demand from our customers. In 2016 and 2017 we made additional investments.”

While not putting a specific number on Malta’s capacity, Caulfield said that if the beginning of 2016 is taken as a baseline, by the end of 2018 the wafer capacity at Malta’s Fab 8 will have more than doubled.

“AMD refreshed its entire portfolio with 14nm, exclusively made here at Malta, and we are chasing more demand than we planned on. AMD’s success is a proxy for our success. We are in this hand in hand,” Caulfield said.

Asked if a new fab was being considered at Malta, Caulfield said “At some point we will need more brick and mortar. Eventually we will run out of space, but we still have some time in front of us.

FDX in the wings

Scotten Jones, who runs a semiconductor cost modeling consultancy, IC Knowledge LLC, said competition is also heating up at the 28nm node, once controlled almost exclusively by TSMC. As GlobalFoundries, Samsung — and more recently, SMIC and UMC — have ironed out their own 28nm processes, the profitability of TSMC’s 28nm business has tightened, Jones said.

The competitive spotlight is now on the 22FDX SOI-based process developed by GlobalFoundries, buttressed by an embedded 22nm eMRAM capability developed along with MRAM pioneer Everspin Technologies.

Gary Patton, chief technology officer at GlobalFoundries, said the SOI-based 22nm node supports forward biasing, while the 12nm FDX technology will support both forward and back-biasing, to either boost performance or conserve power. Patton said the 12FDX process will provide 26 percent more performance and 47 percent less power consumption than the 22FDX process, with prototypes expected in the second half of 2018 and volume production beginning in 2019.

CTO Gary Patton: Technology development boosted by IBM engineers.

Patton said “maybe we haven’t done enough” to explain the differences between the 14nm FinFet technology and the SOI-based FDX technologies. The FinFET transistors have enough drive current to drive signals across fairly large die sizes, while the FDX technology is best suited to die sizes of 150 sq. mm and smaller, he said.

Jones said his cost analysis shows that the design costs for the planar FDX chips are much less expensive than for FinFETs, which require “some fairly expensive EDA tools.” That combines with a much smaller mask count, due to multi-patterning.

Patton said the 22FDX designs require 40 percent fewer masks that comparable 14nm FinFET-based designs. “With the SOI technology customers have the option of using body biasing, which has been used in the industry for the past three or four years. We can operate at .4 Volts, and customers are putting RF on the same chip as digital.”

Asked if he thought the FDX processes would gain traction in the marketplace, Jones answered in the affirmative. “I think it will find its place. It is still early. These kinds of new technologies take time to get established,” Jones said.

Jha said two companies have developed products based on 22FDX, Dream Chip Technologies, an advanced driver assistance system (ADAS) supplier, which last February said it has completed a computer vision SoC based on the 22FDX process, and Ineda Systems, which seeks to integrate RF and digital capabilities on its 22FDX-based processors, targeted at the Internet of Things market.

Mutricy said 70 companies purchased the 22FDX foundation IP provided by Invecas for the 22FDX process, with 18 tapeouts on track for production next year.

Patton said the addition of 500 technologists from IBM’s microelectronics division has aided the technology development operation. “GlobalFoundries is absolutely a different company than it was just two years ago,” Patton said at the GTC event.

MRAM Takes Center Stage at IEDM 2016

Monday, December 12th, 2016

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By Dave Lammers, Contributing Editor

The IEDM 2016 conference, held in early December in San Francisco, was somewhat of a coming-out party for magneto-resistive memory (MRAM). The MRAM presentations at IEDM were complemented by a special MRAM-focused poster session – organized by the IEEE Magnetics Society in cooperation with the IEEE Electron Devices Society (EDS) – with 33 posters and a lively crowd.

And in the opening keynote speech of the 62nd International Electron Devices Meeting, Seok-hee Lee, executive vice president at SK Hynix (Seoul), set the stage by saying that the race is on between DRAM and emerging memories such as MRAM. “Originally, people thought that DRAM scaling would stop. Then engineers in the DRAM and NAND worlds worked hard and pushed out the end further in the future,” he said.

While cautioning that MRAM bit cells are larger than in DRAM and thus more more costly, Lee said MRAM has “very strong potential in embedded memory.”

SK Hynix is not the only company with a full-blown MRAM development effort underway. Samsung, which earlier bought MRAM startup Grandis and which has a materials-related research relationship with IBM, attracted a standing-room-only crowd to its MRAM paper at IEDM. TSMC is working with TDK on its program, and Sony is using 300mm wafers to build high-performance MRAMs for startup Avalanche Technology.

And one knowledgeable source said “the biggest processor company also has purchased a lot of equipment” for its MRAM development effort.

Dave Eggleston, vice president of emerging memory at GlobalFoundries, said he believes GlobalFoundries is the furthest along on the MRAM optimization curve, partly due to its technology and manufacturing partnership with Everspin Technologies (Chandler, Ariz.). Everspin has been working on MRAM for more than 20 years, and has shipped nearly 60 million discrete MRAMs, largely to the cache buffering and industrial markets.

GlobalFoundries has announced plans to use embedded STT-MRAM in its 22FDX platform, which uses fully-depleted SOI technology, as early as 2018.

Future versions of MRAM– such as spin orbit torque (SOT) MRAM and Voltage Controlled MRAM — could compete with SRAM and DRAM. Analysts said today’s spin-transfer torque STT-MRAM – referring to the torque that arises from the transfer of electron spins to the free magnetic layer — is vying for commercial adoption as ever-faster processors need higher performance memory subsystems.

STT-MRAM is fast enough to fit in as a new memory layer below the processor and the SRAM-based L1/L2 cache layers, and above DRAM and storage-level NAND flash layers, said Gary Bronner, vice president of research at Rambus Inc.

With good data retention and speed, and medium density, MRAM “may have advantages in the lower-level caches” of systems which have large amounts of on-chip SRAM, Bronner said, due in part to MRAM’s smaller cell size than six-transistor SRAM. While DRAM in the sub-20nm nodes faces cost issues as its moves to more complex capacitor structures, Bronner said that “thus far STT-MRAM) is not cheaper than DRAM.”

IBM researchers, which pioneered the spin-transfer torque approach to MRAM, are working on a high-performance MRAM technology which could be used in servers.

As of now, MRAM density is limited largely by the size of the transistors required to drive sufficient current to the magnetic tunnel junction (MTJ) to flip its magnetic orientation. Dan Edelstein, an IBM fellow working on MRAM development at IBM Research, said “it is a tall order for MRAM to replace DRAM. But MRAM could be used in system-level memory architectures and as an embedded memory technology.”

PVD and etch challenges

Edelstein, who was a key figure in developing copper interconnects at IBM some twenty years ago, said MRAM only requires a few extra mask layers to be integrated into the BEOL in logic. But there remain major challenges in improving the throughput of the PVD deposition steps required to deposit the complex material stack and to control the interfacial layers.

The PVD steps must deposit approximately 30 layers and control them to Angstrom-level precision. Deposition must occur under very low base pressure, and in oxygen- and water-vapor free environments. While tool vendors are working on productization of 300mm MRAM deposition tools, Edelstein said keeping particles under control and minimizing the maintenance and chamber cleaning are all challenging.

Etching the complex materials stack is even harder. Chemical RIE is not practical for MRAMs at this point, and using ion beam etching (IBE) presents challenges in terms of avoiding re-deposition of material sputtered off during the IBE etch steps for the high-aspect-ratio MTJs.

For the tool vendors, MRAMs present challenges as companies go from R&D to high-volume manufacturing, Edelstein said.

A Samsung MRAM researcher, Y.J. Song, briefly described IBE challenges during an IEDM presentation describing an embedded STT-MRAM with a respectable 8-Mbit density and a cell size of .0364 sq. micron. “We worked to optimize the contact etching,” using IBE etch during the patterning steps, he said. The short fail rate was reduced, while keeping the processing temperature at less than 350°C, Song said.

Samsung embedded an STT-MRAM module in the copper back end of the line (BEOL) of a 28nm logic process. (Source: Samsung presentation at IEDM 2016).

Many of the presentations at IEDM described improvements in key parameters, such as the tunnel magnetic resistance (TMR), cell size, data retention, and read error rates at high temperatures or low operating voltages.

An SK Hynix presentation described a 4-Gbit STT-MRAM optimized as a stand-alone, high-density memory. “There still are reliability issues for high-density MRAM memory,” said SK Hynix’s S.-W. Chung. The industry needs to boost the TMR “as high as possible” and work on improving the “not sufficiently long” retention times.

At high temperatures, error rates tend to rise, a concern in certain applications. And since devices are subjected to brief periods of high temperatures during reflow soldering, that issue must be dealt with as well, detailed by a Bosch presentation at IEDM.

Cleans and encapsulation important

Gouri Sankar Kar, who is coordinating the MRAM research program at the Imec consortium (Leuven, Belgium), said one challenge is to reduce the cell size and pitch without damaging the magnetic properties of the magnetic tunnel junction. For the 28nm logic node, embedded MRAM would be in the range of a 200nm pitch and 45nm critical dimensions (CDs). At the IEDM poster session, Imec presented an 8nm cell size STT-MRAM that could intersect the 10nm logic node, with the MRAM pitch in the 100nm range. GlobalFoundries, Micron, Qualcomm, Sony and TSMC are among the participants in the Imec MRAM effort.

Kar said in addition to the etch challenges, post-patterning treatment and the encapsulation liner can have a major impact on MTJ materials selection. “Some metals can be cleaned immediately, and some not. For the materials stack, patterning (litho and etch) and clean optimization are crucial.”

“Chemical etch (RIE) is not really possible at this stage. All the tool vendors are working on physical sputter etch (IBE) where they can limit damage. But I would say all the major tool vendors at this point have good tools,” Kar said.

To reach volume manufacturing, tool vendors need to improve the tool up-time and reduce the maintenance cycles. There is a “tail bits” relationship between the rate of bit failures and the health of the chambers that still needs improvement. “The cleanup steps after etching are very, very critical” to the overall effort to improving the cost effectiveness of MRAM, Kar said, adding that he is “very positive” about the future of MRAM technology.

A complete flow at AMAT

Applied Materials is among the equipment companies participating in the Imec program, with TEL and Canon-Anelva also heavily involved. Beyond that, Applied has developed a complete MRAM manufacturing flow at the company’s Dan Maydan Center in Santa Clara, and presented its cooperative work with Qualcomm on MRAM development at IEDM.

In an interview, Er-Xuan Ping, the Applied Materials managing director in charge of memory and materials technologies, said about 20 different layers, including about ten different materials, must be deposited to create the magnetic tunnel junctions. As recently as a few years ago, throughput of this materials stack was “extremely slow,” he said. But now Applied’s multi-cathode PVD tool, specially developed for MRAM deposition, can deposit 5 Angstrom films in just a few seconds. Throughput is approaching 20 wafers per hour.

Applied Materials “basically created a brand-new PVD chamber” for STT-MRAM, and he said the tool has a new e-chuck, optimized chamber walls and a multi-cathode design.

The MRAM-optimized PVD tool does not have an official name yet, and Ping said he refers to it as multi-cathode PVD. With MRAM requiring deposition of so many different metals and other materials, the Applied tool does not require the wafer to be moved in and out, increasing efficiency. The shape and structure of the chamber wall, Ping said, allow absorption of downstream plasma material so that it doesn’t come back as particles.

For etch, Applied has worked to create etching processes that result in very low bit failure rates, but at relatively relaxed pitches in the 130-200nm range. “We have developed new etch technologies so we don’t think etch will be a limiting factor. But etch is still challenging, especially for cells with 50nm and smaller cell sizes. We are still in unknown territory there,” said Ping.

Jürgen Langer, R&D manager at Singulus Technology (Frankfurt, Germany), said Singulus has developed a production-optimized PVD tool which can deposit “30 material layers in the Angstrom range. We can get 20 wafers per hour throughputs, so I would say this is not a beta tool, it is for production.”

Jürgen Langer, R&D manager, presented a poster on MRAM deposition from Singulus Technology (Frankfurt, Germany).

Where does it fit?

Once the production challenges of making MRAM are ironed out, the question remains: Where will MRAM fit in the systems of tomorrow?

Tom Coughlin, a data storage consultant based in Atascadero, Calif., said embedded MRAM “could have a very important effect for industrial and consumer devices. MRAM could be part of the memory cache layers, providing power advantages over other non-volatile devices.” And with its ability to power on and power off without expending energy, MRAM could reduce overall power consumption in smart phones, cutting in to the SRAM and NOR sectors.

“MRAM definitely has a niche, replacing some DRAM and SRAM. It may replace NOR. Flash will continue for mass storage, and then there is the 3D Crosspoint from Intel. I do believe MRAM has a solid basis for being part of that menagerie. We are almost in a Cambrian explosion in memory these days,” Coughlin said.


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