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Innovations at 7nm to Keep Moore’s Law Alive

Thursday, January 19th, 2017


By Dave Lammers, Contributing Editor

Despite fears that Moore’s Law improvements are imperiled, the innovations set to come in at the 7nm node this year and next may disprove the naysayers. EUV lithography is likely to gain a toehold at the 7nm node, competing with multi-patterning and, if all goes well, shortening manufacturing cycles. Cobalt may replace tungsten in an effort to reduce resistance-induced delays at the contacts, a major challenge with finFET transistors, experts said.

While the industry did see a slowdown in Moore’s Law cost reductions when double patterning became necessary several years ago, Scotten Jones, who runs a semiconductor consultancy focused on cost analysis, said Intel and the leading foundries are back on track in terms of node-to-node cost improvements.

Speaking at the recent SEMI Industry Strategy Symposium (ISS), Jones said his cost modeling backs up claims made by Intel, GlobalFoundries, and others that their leading-edge processes deliver on die costs. Cost improvements stalled at TSMC for the16nm node due to multi-patterning, Jones said. “That pause at TSMC fooled a lot of people. The reality now may surprise those people who said Moore’s Law was dead. I don’t believe that, and many technologists don’t believe that either,” he said.

As Intel has adopted a roughly 2.5-year cadence for its more-aggressive node scaling, Jones said “the foundries are now neck and neck with Intel on density.” Intel has reached best-ever yield levels with its finFET-based process nodes, and the foundries also report reaching similar yield levels for their FinFET processes. “It is hard, working up the learning curve, but these companies have shown we can get there,” he said.

IC Knowledge cost models show the chip industry is succeeding in scaling density and costs. (Source: Scotten Jones presentation at 2017 SEMI ISS)

TSMC, spurred by its contract with Apple to supply the main iPhone processors, is expected to be first to ship its 7nm products late this year, though its design rules (contacted poly pitch and minimum metal pitch) are somewhat close to Intel’s 10nm node.

While TSMC and GlobalFoundries are expected to start 7nm production using double and quadruple patterning, they may bring in EUV lithography later. TSMC has said publicly it plans to exercise EUV in parallel with 193i manufacturing for the 7nm node. Samsung has put its stake in the ground to use EUV rather than quadruple patterning in 2018 for critical layers of its 7nm process. Jones, president of IC Knowledge LLC, said Intel will have the most aggressive CPP and MPP pitches for its 7nm technology, and is likely to use EUV in 2019-2020 to push its metal pitches to the minimum possible with EUV scanners.

EUV progress at imec

In an interview at the 62nd International Electron Devices Meeting (IEDM) in San Francisco in early December, An Steegen, the senior vice president of process technology at Imec (Leuven, Belgium), said Imec researchers are using an ASML NXE 3300B scanner with 0.3 NA optics and an 80-Watt power supply to pattern about 50 wafers per hour.

“The stability on the tool, the up time, has improved quite a lot, to 55 percent. In the best weeks we go well above 70 percent. That is where we are at today. The next step is a 125-Watt power supply, which should start rolling out in the field, and then 250 Watts.”

Steegen said progress is being made in metal-containing EUV resists, and in development of pellicles “which can withstand hydrogen in the chamber.”

If those challenges can be met, EUV would enable single patterning for vias and several metal layers in the middle of the line (MOL), using cut masks to print the metal line ends. “For six or seven thin wires and vias, at the full (7nm node) 32nm pitch, you can do it with a single exposure by going to EUV. The capability is there,” Steegen said.

TSMC’s 7nm development manager, S.Y. Wu, speaking at IEDM, said quadruple patterning and etch (4P4E) will be required for critical layers until EUV reaches sufficient maturity. “EUV is under development (at TSMC), and we will use 7nm as the test vehicle.”

Huiming Bu was peppered with questions following a presentation of the IBM Alliance 7nm technology at IEDM.

Huiming Bu, who presented the IBM Alliance 7nm paper at IEDM, said “EUV delivers significant depth of field (DoF) improvement” compared with the self-aligned quadruple (SAQP) required for the metal lines with immersion scanners.

A main advantage for EUV compared with multi-patterning is that designs would spend fewer days in the fabs. Speaking at ISS, Gary Patton, the chief technology officer at GlobalFoundries, said EUV could result in 30-day reductions in fab cycle times, compared with multiple patterning with 193nm immersion scanners, based on 1.5 days of cycle time per mask layer.

Moreover, EUV patterns would produce less variation in electrical performance and enable tighter process parameters, Patton said.

Since designers have become accustomed to using several colors to identify multi-patterning layers for the 14nm node, the use of double and quadruple patterning at the 7nm node would not present extraordinary design challenges. Moving from multi-patterning to EUV will be largely transparent to design teams as foundries move from multi-patterning to EUV for critical layers.

Interconnect resistance challenges

As interconnects scale and become more narrow, signals can slow down as electrons get caught up in the metal grain boundaries. Jones estimates that as much as 85 percent of parasitic capacitance is in the contacts.

For the main interconnects, nearly two decades ago, the industry began a switch from aluminum to copper. Tungsten has been used for the contacts, vias, and other metal lines near the transistor, partly out of concerns that copper atoms would “poison” the nearby transistors.

Tungsten worked well, partly because the bi-level liner – tantalum nitride at the interface with the inter-level dielectric (ILD) and tantalum at the metal lines – was successful at protecting against electromigration. The TaN-Ta liner is needed because the fluorine-based CVD processes can attack the silicon. For tungsten contacts, Ti serves to getter oxygen, and TiN – which has high resistance — serves as an oxygen and fluorine barrier.

However, as contacts and MOL lines shrunk, the thickness of the liner began to equal the tungsten metal thicknesses.

Dan Edelstein, an IBM fellow who led development of IBM’s industry-leading copper interconnect process, said a “pinch point” has developed for FinFETs at the point where contacts meet the middle-of-the-line (MOL) interconnects.

“With cobalt, there is no fluorine in the deposition process. There is a little bit of barrier, which can be either electroplated or deposited by CVD, and which can be polished by CMP. Cobalt is fairly inert; it is a known fab-friendly metal,” Edelstein said, due to its longstanding use as a silicide material.

As the industry evaluated cobalt, Edelstein said researchers have found that cobalt “doesn’t present a risk to the device. People have been dropping it in, and while there are still some bugs that need to be worked out, it is not that hard to do. And it gives a big change in performance,” he said.

Annealing advantages to Cobalt

Contacts are a “pinch point” and the industry may switch to cobalt (Source: Applied Materials)

An Applied Materials senior director, Mike Chudzik, writing on the company’s blog, said the annealing step during contact formation also favors cobalt: “It’s not just the deposition step for the bulk fill involved – there is annealing as well. Co has a higher thermal budget making it possible to anneal, which provides a superior, less granular fill with no seams and thus lowers overall resistance and improves yield,” Chudzik explained.

Increasing the volume of material in the contact and getting more current through is critical at the 7nm node. “Pretty much every chipmaker is working aggressively to alleviate this issue. They understand if it’s not resolved then it won’t matter what else is done with the device to try and boost performance,” Chudzik said.

Prof. Koike strikes again

Innovations underway at a Japanese university aim to provide a liner between the cobalt contact fill material and the adjacent materials. At a Sunday short course preceding the IEDM, Reza Arghavani of Lam Research said that by creating an alloy of cobalt and approximately 10 percent titanium, “magical things happen” at the interfaces for the contact, M0 and M1 layers.

The idea for adding titanium arose from Prof. Junichi Koike at Tohoku University, the materials scientist who earlier developed a manganese-copper solution for improved copper interconnects. For contacts and MOL, the Co-Ti liner prevents diffusion into the spacer oxide, Arghavani said. “There is no (resistance) penalty for the liner, and it is thermally stable, up to 400 to 500 degrees C. It is a very promising material, and we are working on it. W (tungsten) is being pushed as far as it can go, but cobalt is being actively pursued,” he said.

Stressor changes ahead

Presentations at the 2016 IEDM by the IBM Alliance (IBM, GlobalFoundries, and Samsung) described the use of a stress relaxed buffer (SRB) layer to induce stress, but that technique requires solutions for the defects introduced in the silicon layer above it. As a result of that learning process, SRB stress techniques may not come into the industry until the 5 nm node, or a second-generation 7nm node.

Technology analyst Dick James, based in Ottawa, said over the past decade companies have pushed silicon-germanium stressors for the PFET transistors about as far as practical.

“The stress mechanisms have changed since Intel started using SiGe at the 90nm node. Now, companies are a bit mysterious, and nobody is saying what they are doing. They can’t do tensile nitride anymore at the NFET; there is precious little room to put linear stress into the channel,” he said.

The SRB technique, James said, is “viable, but it depends on controlling the defects.” He noted that Samsung researchers presented work on defects at the IEDM in December. “That was clearly a research paper, and adding an SRB in production volumes is different than doing it in an R&D lab.”

James noted that scaling by itself helps maintain stress levels, even as the space for the stressor atoms becomes smaller. “If companies shorten the gate length and keep the same stress as before, the stress per nanometer at least maintains itself.”

Huiming Bu, the IBM researcher, was optimistic, saying that the IBM Alliance work succeeded at adding both compressive and tensile strain. The SRB/SSRW approach used by the IBM Alliance was “able to preserve a majority – 75 percent – of the stress on the substrate.”

Jones, the IC Knowledge analyst, said another area of intense interest in research is high-mobility channels, including the use of SiGe channel materials in the PMOS FinFETS.

He also noted that for the NMOS finFETs, “introducing tensile stress in fins is very challenging, with lots of integration issues.” Jones said using an SRB layer is a promising path, but added: “My point here is: Will it be implemented at 7 nm? My guess is no.”

Putting it in a package

Steegen said innovation is increasingly being done by the system vendors, as they figure out how to combine different ICs in new types of packages that improve overall performance.

System companies, faced with rising costs for leading-edge silicon, are figuring out “how to add functionality, by using packaging, SOC partitioning and then putting them together in the package to deliver the logic, cache, and IOs with the right tradeoffs,” she said.

Rhines Expounds on the Deconsolidation of the Semiconductor Industry

Wednesday, April 27th, 2016


By Jeff Dorsch, Contributing Editor

“By 2020, we are all going to work for the same company,” Wally Rhines, chairman and chief executive officer of Mentor Graphics, said Tuesday morning (April 26) in his keynote presentation at Mentor’s U2U user conference in Santa Clara, Calif.

Taking “Merger Mania” as his theme, the veteran electronic design automation and semiconductor executive reviewed the merger-and-acquisition activity of 2015, some of which is extending into this year. Rhines noted that several of the big acquiring companies in last year’s wave of industry consolidation had names beginning with the letter “M,” while some of the acquired chip enterprises had names beginning with the letter “A.” That, he joked, was the genesis of “M&A” in 2015.

On a more serious note, the Mentor CEO challenged the conventional wisdom that the industry experienced unprecedented deal-making and combination in 2015. The number of deals involved, 30, wasn’t a record, he said. It was the “magnitude” of valuations in those transactions, with a number of multibillion-dollar acquisitions, he added.

The top 10 semiconductor suppliers in the world have changed dramatically since the 1950s, as the industry has transitioned from germanium transistors to silicon-based integrated circuits made with a bipolar process, metal-oxide-semiconductor memory chips, memories/microprocessors, and system-on-a-chip devices, according to Rhines.

The industry market share of the top 50 chip companies has actually declined for many years, through 2014, he noted. “We’re still on a deconsolidation path,” Rhines asserted. “The dynamics of the industry change.”

While the industry was selling 50 percent of its chips for computing applications a decade ago, and 25 percent for communications, the trend has lately shifted, with communications overtaking computers as the leading application, although the line between communications and computing is getting blurrier, Rhines noted.

“Why the acceleration in mergers?” Rhines wondered. The chief factors generally credited are economies of scale, financial leverage, and regulatory/government mandates, he listed.

Despite all the combinations over the years, there is scant evidence that mergers always mean higher profit margins, compared with revenue figures, Rhines said. “There is no correlation between size and profits,” he noted. “It’s not an automatic formula for success. Maybe scale isn’t the answer.”

A more compelling reason for the wave of mergers is “very cheap money,” with historically low rates on corporate loans, Rhines noted. Tax advantages, especially on tax-inversion deals, seem to be fading as an incentive to merge, as the federal government is making it more difficult for large corporations to move their headquarters out of the United States and minimize their tax obligations to the U.S., according to Rhines.

That brings in the consideration of regulations and government mandates. China is engaged in a five-year program to create “greater self-sufficiency” for its domestic semiconductor industry, the Mentor CEO said. Instead of directly subsidizing the growth of semiconductor manufacturers and chip-related suppliers, China’s central government is taking equity stakes in private-equity firms that are making investments in the semiconductor industry, sometimes seeking to acquire companies in the U.S. and around the world, or to take an ownership stake in key companies.

Research and development spending by semiconductor companies goes up and down depending on industry revenue, yet it generally remains flat as a percentage of revenue – typically around 14 percent of revenue, according to Rhines.

Still, “long-term interest rates can’t stay low forever,” he concluded. “Merger mania will be limited.”

In an interview following his keynote, Rhines expounded on the theme of the learning curve – a concept that encompasses Moore’s Law and other observations of technological change. In addition to talking about the learning curve in his keynote, Rhines also wrote about in a recent blog post.

Moore’s Law presents a “limited set of knobs to turn,” he observed. For years, “the most productive thing to do is shrink” the dimensions of ICs, he said. While the demise of Moore’s Law has long been predicted, “the cost per switch/transistor will always be going down,” he added. “You will always see an improvement.”

The Internet of Things is widely touted as the next market to boost the fortunes of the semiconductor industry. IoT could force the industry to “improve enough to enable another application, like wireless,” Rhines said.

In general, the industry is facing substantial manufacturing challenges in getting down to the 16/14-nanometer process node and smaller dimensions. “Every generation has a new physics problem to solve,” Rhines observed. “Complexity grows.”

Chip designers and manufacturers are now dealing with electromigration issues and thermal problems, he noted. EDA is taking on these challenges while also pivoting to the wider considerations of system design, rather than chip or board design, Rhines said.

“Forty percent of our revenue comes from system design,” the Mentor CEO said. Designing systems for automotive vehicles, military/aerospace systems, medical equipment, and other areas represents a $2.5 trillion market in total, compared with about $350 billion for semiconductors, on an annual basis.

Faced with declining revenue and profitability in the 2016 fiscal year, Mentor Graphics offered a voluntary early retirement program for veteran employees, and dozens of them took the buyout benefits, Rhines noted. This represented “a forcible evolution of the company,” he said. “We were going to lose a significant amount of corporate learning.”

While somewhere between 110 and about 200 employees took early retirement, Mentor actually increased its headcount last year, from 5,558 full-time positions as of January 31, 2015, to around 5,700 positions on January 31, 2016.

What about retirement for Rhines, who will celebrate his 70th birthday in November of this year? “I haven’t actually thought about it,” he said in the interview. While carefully noting, “I serve at the will of the board,” Rhines added, “I’m not looking for another job.” He still has the “energy level” for all those red-eye flights to meet with customers, he said. “I don’t play golf,” Rhines commented. “I like a lot of pressure, crises. I love the relationships I have with customers, employees.”

The Rhines keynote was followed Tuesday morning by a keynote from Zach Shelby, vice president of marketing for the Internet of Things at ARM Holdings, who spoke on “Driving Beyond IoT.”

Shelby noted the history of computing, communications, and networking in recent decades. “It takes an ecosystem,” he asserted. ARM, he said, is not just a fabless semiconductor company; “we’re silicon-less,” he said, since ARM is involved in developing and licensing technology for other companies to use. The IC design company works with operators of cloud services, network operators, system integrators and end-users around the world, according to Shelby.

The industry trend is going “from embedded to connected, reaching millions of developers,” he said.

While some see automotive vehicles as “expensive mobile phones,” Shelby said, “They’re becoming autonomous drones.” He added, “The auto is the ultimate intelligent connected device.”

Rhines and Shelby later participated in an afternoon panel session titled “Ripple or Tidal Wave: What’s Driving the Next Wave of Innovation and Semiconductor Revenue?” Also on the panel were James Hogan of Vista Ventures, Brad Howe of Altera, and Kelvin Low of Samsung Semiconductor.

Are We At an Inflection Point with Silicon Scaling and Homogeneous ICs?

Wednesday, October 15th, 2014


By Bill Martin, President and VP of Engg, E-System Design

In the late 1940’s, three physicists (Bardeen, Brattain and Shockley) invented the first transistor and were later awarded the Nobel Prize in 1956 (Figure 1).  Texas Instruments commercialized the integrate silicon transistor (IC) in 1954 revolutionizing consumer products.  The IC invention and commercialization came at a perfect point in history1,2.

During 1950-1970s, the US population grew by 33% (Figure 2), income grew 170% and disposable spending increased 259% (Figure 3).  Disposable income was aided by increasing income but also by significant changes to our marginal tax rates.  (Figure 4).  Consumer demand for better IC based products and their spending $s provided a perfect Petri dish to hone a new technology requiring new processes (silicon, packaging and pcb); supply chains and high tech marketing for future IC based technologies3,4.

In this period, Moore’s Law was ‘coined’ and quickly drove and guided silicon manufacturers to prove their processing prowess. It also drove product companies and their marketing staffs to harness the guaranteed 2x density, improved performance and less expensive next generation silicon technology within their products.  Like an atomic clock, the market expected and received the new capabilities every 18-24 months.

The IC treadmill was at full speed replacing older, larger, slower, higher maintenance products with ICs.  As ‘they’ conquered existing products, new uses from the significant (medical devices), to the trivial (musical greeting cards) were developed to capture the growing disposable income.  In the early days, it was cheap to create any type of product to test market acceptance.

Since the 1970’s the environment has significantly improved:

US population is over 330 million, annual income is over $50K, disposable spending is approaching 50% and the tax rates continue to fall.  In addition, the entire world, 7 billion strong and growing, many wanting to have the latest products.  Today’s product success benchmark has elevated to a million or more units purchased during a product’s life span.  Some very well designed and marketed products attain this volume on the initial day of sale (iPhone)!

Cracks in the foundation:  Inflection omen?

But there were cracks in the foundation starting to appear.   More resources, more time and additional physical effects that had to be analyzed and resolved.  But engineers are very good at solving these issues that arise with each new generation.  One aspect that has not been addressed and is racing out of control is a design’s silicon mask costs.  Masks allow silicon foundries to build up ICs one layer at a time and define all geometries required for an IC to work.  Each physical layer may require 1 or 2 masks.  Until the mid 1990’s, mask costs were manageable.  But as the industry continued to drive toward smaller geometries, 90nm silicon mask costs passed $1M per design5.  Process engineers had accomplished their goals of producing smaller geometries but this caused an escalation in the required number of masks per layer and the finer geometries increased the cost to create and inspect each mask.  Both factors led to a geometric impact on mask costs.  Once past the $1M per mask set, the next process’ mask prices quickly escalated to $3-4M for a 65nm set.  This is just for the masks and does not include other product development costs, wafer/assembly/test manufacturing costs, marketing or sales costs.  Quick math:  a product with 1 million units of sales that contains one 65 nm integrate circuit will attribute $3-4 dollars to pay back ONLY the mask set expense.   FPGA, as a design platform, is one solution but this assumes that your design can be implemented in an FPGA.  Many high volume parts still want a dedicated, non-FPGA solution due to per unit costs.  Think what the end product’s sale’s price must be for a decent return on investment (ROI).  Economics used to be a friend of silicon linear scaling but we might be at the economic inflection point for linear scaling.  A recent SemiWiki post by Paul McLellan highlights the complexity and change required to continue the silicon scaling6:

“The problem with double patterning is that it is possible to design layouts that cannot be split into two masks…
To make things worse, this is not a local phenomenon…
The introduction of both multi-patterning and FinFETs has a huge impact …

the entire place and route flow needs to be completely revamped.”

Economics drive the inflection

Will all these technology issues get resolved?  Scientists and engineers have conquered most of what they focus on (flying, space, ocean, medical, etc).  In time, all of the technical issues can be resolved but what will be the cost to use these ‘solutions’?  Economics on the product development side (development vs. revenues generated) will cause many product developers to search for alternative solutions or cancel projects that are ROI infeasible.

Moore’s Law V1.0 was based upon manufacturing unit learning curves.  Each doubling of volume helped decrease the costs to produce the next unit by improving yields.  Improving yields allowed designers to create larger die with more transistors and functionality but at a higher cost (at least they could get >0% yield).  But this higher cost drove product companies to search for the next generation silicon node that shrunk the die to improve costs:  a perfect circular system re-enforcing itself.

Time for Moore’s Law 2.0 (Figure 6:  More than Moore modified)

Changing to another solution requires persistence, energy and small successes to gain inertia for Moore’s Law 2.0.   Packaging becomes the focus on Moore’s Law 2.0:  2.5D and 3D allow the mixing and matching of many building blocks into miniaturized systems.  Blocks already designed, proven with known histories, costs and suppliers:  significantly reducing risks and development costs.

Homogeneous silicon will never be able to integrate all into a single piece of silicon but must always be available.   Too many compromises in the homogeneous processing will reduce the effectiveness of a given function (ie AMS/RF or memory or MEMS or…) and the cost of:  tools, masks and processing complexity will quickly cancel any products looking for a positive ROI.

Maybe not a secret any longer….

Secrets are hard to keep when more and more people start to talk.  In recent months, increasing articles and press releases discuss companies that are exploring and/or using 2.5/3D packaging for impressive gains.   Many of these efforts have been hidden for either keeping a competitive edge or for fear of public failure.  But like many trends, once a trend gains momentum, it is difficult to stop.  Moore’s Law V1.0 is a perfect example.

If your company is on the Moore’s Law V2.0 bandwagon, continue to re-examine old thoughts with a fresh perspective.

If your company is not investigating Moore’s Law V2.0, you might want to ask why not?


1 First transistor picture. and


3 “100 Years of U.S. Consumer Spending”, U.S. Departments of Labor and Statistics, May 2006.

4 Annenberg Learner website:

5 C.R. Helms, Past President & CEO International SEMATECH, “Semiconductor Technology Research, Development, & Manufacturing:  Status, Challenges, & Solutions” p16,, 2003.

6 Place & Route with FinFETs and Double Patterning, Paul McLellan, Sept 29, 2014,

Wrap-up: SEMI’s Strategic Materials Conference

Tuesday, October 7th, 2014

SEMI’s Strategic Materials Conference was held September 30-October 1, 2014, in Santa Clara, CA at the Biltmore hotel.

By Karey Holland, Techcet Group

The 2014 Strategic Materials Conference was very well attended.  There were people from several of the leading IC makers as well as suppliers of equipment and materials to the fabs.  Unfortunately, the audio and video systems were not stellar, so we had to endure some ear shattering system noise, and any light image was not visible on the screens.  Otherwise, the venue was good.  Throughout the conference, several themes were repeated.

Focus on the stability we hope for in post 2013 times, but concern about volatility and uncertainty of the world economics, esp. the recession-like growth numbers in Europe and Japan expected for the next few years. While forecasters (Gartner, IC Insights, VLSI Research, Linx, Techcet Group and others) anticipate IC wafer starts growing at ≥6% CAGR over the next 5 years, there is concern that any number of geo political world problems could throw us back into a global recession.  Attendees had a greater concern than the presenters over the possibility of a future recession, and that the impact would be greater to IC industry now due to the entrenchment of mobile platforms.

Focus on cost of lithography as a driver for increased cost of leading edge MCUs/MPUs … with current nodes, multi-patterning requires many more expose/develop/dep/etch steps than EUV, but EUV has not yet met the requirements for manufacturing implementation.  It is likely that EUV will first be used for only a few critical layers.  DSA (directed self-assembly) may be used also for a few selected critical layers, but issues of defects will likely keep it from use in many layers.

Focus on the expected (and currently numerous options) for advanced devices and implications for materials.  This includes advanced packaging technologies.

450mm wafers may continue to slip, if the other large IC makers (e.g. TSMC, Samsung, GlobalFoundries) don’t agree with Intel on first implementation date/node. Collaboration across the entire ecosystem was stressed for 450mm to become a reality.

Below are things I found particularly interesting in the presentations and/or at the end of day panel discussions.

The key note presentation, “Materials Innovation for the Digital 6th Sense Era,” was by Matt Nowak of Qualcomm.  He discussed both the vision of the Internet of Things (IoT), the required IC devices (including analog & sensors) and implications to materials (and cost to manufacture) from these new IC devices; a perfect start to SMC 2014.  Qualcomm defines the Digital 6th Sense Era is “the augmentation of human ability”, or as Sue Davis put it “intelligent data based extension of our 5 senses ==>to a 6th“. Essentially this is where the ability of the IoT/IoE data feedback can act as our 6th sense by capturing data about one & one’s environment which results in  prediction/information being shared based on data collection and/or user selections regarding the environment around us (or about us, e.g., tele-health).”  Because the smartphone is the “most pervasive platform ever” (US Android users average 106 Apps launched/day), it can serve as a remote connection to the IoT world … be that monitoring our health, schedules, honey-do lists, and improving our understanding and enjoyment of the world around us.  For advanced logic one might expect, lithography for advanced ICs (quad patterning vs EUV) were discussed as key cost drivers.  Other required/expected advanced materials include high mobility channel materials and thin barrier metals (likely Co). Beyond CMOS, new structures and materials may be required to support sensors (bio, chemical, fluidic), nano batteries, piezo, thermal, and solar harvesters.

Mark Thirsk, Linx-Consulting, reviewed IC growth and lack thereof for past years, and observed that 2014 will be “first good year in 8 years” (since 2006), and forecast 6-8% CAGR for the next few years – strongly dependent on the success of the IoT.  IC market growth since 2010 correlates strongly to GDP since 2010, and thus regional GDP differences (e.g. the current European recession) are reflected in IC demand.  Technology challenges & opportunities in for the next 5+ years include advanced logic (3D NAND, and new memory method after 2018), numerous AL (atomic layer) processes, 3D / advanced packaging, patterning efficiency, and complexity.  The electronic materials landscape is changing: the supply chain is merging, and there are new entrants (esp. from Korea, Taiwan & China) in advanced materials such as photoresists. Interestingly, China appears to be focusing more on investing in fabless than fabs.

Duncan Meldrum, Hilltop Economics, said that the current subdued market growth (3% 2013-16) is due to more fiscal responsible people. China & Asia are growing 4 to 7.7%, US & Latin America about 2.1 to 3.1, Euro <2%, and Japan ~1.5%.  The tax increase in Japan is having a very negative impact. He expects the US to see a 5% year over year improvement (very good news) with our investments finally growing in 2nd half of 2014.  He anticipates healthy, but not stellar consumer spending through 2016.

Patrick Ho, Stifel Nicolas, initially discussed that for companies that follow Moore’s Law, that it is increasingly Fab capital intensity (Capex) with addition of FinFETs, new materials (e.g. High k), 3D NAND, and Multi-Patterning (from delayed EUV).  One can assume this will continue to be the case as CMOS devices moves from Si channel to replacement channel filled with SiGe, Ge, or III-V and memories move to new technologies such as ReRAM, STTRAM, etc.  His observation is that only Intel is pulling for 450mm, and if TSMC & Samsung don’t exert more pull, 450mm may not happen (esp. in light of the negative impact to equipment revenue per square inch of silicon).  The top 4 OEMs (ASML, KLA-T, Lam, AMAT) are large enough to push back on the top 3 IC makers, and that consolidation is continuing.  Patrick noted that all 4 top OEMs have dividends, and he anticipates that they will eventually get better valuations.  He showed a nice list of companies he thinks are acquisition candidates (CMC, Nanometrics, Nikon, Nova, Axcelis, Rudolph, Veeco, FormFactor, and Ultratech).  Other comments:  Moore’s law lives, but is under stress.  Innovation w/ or w/o EUV will bring industry back to Moore’s Law.  Changing landscape will help economics of leading players.

Ross Kozarsky, who leads Lux Research’s advanced materials team, discussed the longer range materials he investigates such as graphene, 3D printing, and Meta-materials. Graphene film sheets are of interest for transparent conductive materials (e.g. touchscreens), possibly moving to FETs & sensors.  3D printing has been around 30 yrs; today it’s used mostly for prototyping, but manufacturing use makes sense and could really increase total growth.  Multifunctional and multi-materials printers will be needed.  Autonomous cars are now a big growth opportunity, opening great opportunity for chemical and material companies to innovate.

Geraud Duboix, IBM Almaden, develops porous low k materials for interconnect passivation and their integration (esp. plasma damage).  In the 0.65 to 0.1um timeframe, interconnect RC delay was slowing devices even though the transistors were getting faster, and thus began the drive for lower k insulators.  The ITRS has been showing the need for lower k since its inception, but it also has pushed out the date of the more aggressive low ks.  Initially to achieve lower k, C and F were added to SiO2 to break-up network structure.  Today, they are driving low k down by adding porosity.  Once a big concern, Geraud said that ULK mechanical properties are now no longer a concern with UV treatment, the lowest k being integrated is 2.3-2.4, and new low k materials are emerging. Geraud is working on porous low k materials, to achieve lower k, and larger pores deliver lower k.  He discussed the various pore-sizes in evaluation, the importance of porogens (material in the low k deposition that is later removed to create pores) and methods being used to seal the created pores (especially before conformal barrier metal deposition).  Interestingly, he commented that creating and sealing the larger pores is somewhat easier, although he’s being asked to work on the smaller pores for now.  During the panel discussion Mansour Moinpour (Intel) asked why Geraud was working on smaller pores that are more difficult to fill. Geraud responded that for the designers insulators with 2.0 or 1.8 k would be too big a change and they want 2.4 and 2.2 first.

Todd Younkin, from Intel’s central research (components) novel materials group, discussed that the industry will continue CMOS Scaling through 7nm. As stated by others, lithography is a challenge and using several methods to accomplish patterning, while productivity and pattern placement (alignment) are concerns.  Intel is working on devices with channels of higher mobility materials that Si (III-V or MoS2) as well as beyond CMOS (e.g., GAA) devices.  Todd said that early in device research development, Intel works to make sure manufacturing should be capable of meeting cost expectations. These include the cost of multi-patterning versus EUV, ultra-low k interconnect materials, etc.

Angela Franklin, of TriQuint (recently renamed Qorvo) discussed the challenges of supply management (and unlike others, she projects well when talking, so we could avoid the audio system problems … thanks Angela!).  Angela educated the audience about Qorvo devices (some look more like MEMS with permanent epoxy “cavity” structures that resonate w/ the RF) which are significantly different from the leading edge logic and non-volatile most of us follow.  Unlike the device manufactures that use Si, Qorvo uses smaller substrates of III-V and GaN.  Many films are already on the substrates when purchased.  The fab process is very solvent intensive, and only 1/3 aqueous.  Unlike others, Qorvo uses significant eBeam lithography with up to 28 different resists and many negative resists, as well as metal lift-off (my first job at IBM >30 yrs ago).

Prof. Philip Wong of Stanford gave his typical dynamic and mind-stretching presentation. His discussion was focused on the single digit nodes, and the possible new channel materials for logic (III-V or 2D MoS2, MoSe2, WSe2, WTe2 or ??) and possible new devices, including carbon nanotube FET (CNFET), STTRAM, CBRAM, ReRAM (using HfOx, TaOx, TiOx).  He said that memory chips will hold 32Tbits.  He then smiled and said “none of this before the next 10 years”.  He showed some exciting interleaved memory and logic ideas using a base of 2D or 3D FETs, topped by STTRAM, then 2D or 3D FETs, and then 3D RRAM.  Because the interconnects of the bottom device are present, all processing for the others must be at low temperature (<400C).

Discussion Panel.  When asked about collaboration with materials suppliers, Intel and IBM research had significantly different responses.  Intel invests dollars and works with graduate students on advanced projects and hopefully a “lucky accident” brings advances.  IBM research mentioned that legal issues often get in the way of collaboration with suppliers.

Notes for SMC Day 2 2014 Blog

Tim Hendry, from Intel’s supply management team started off day 2.  A large concern he brought up was what he described as the widening connections between fab, material suppliers, and sub-suppliers.  He then discussed the concerns and possible ways to improve connections, as well as the importance of metrology and verification of chemical quality.  Unfortunately, some of the sub-suppliers are very big chemical companies that have difficulty getting excited about the low volume materials used to make ICs.  He finished up by saying that Intel is focused on controlling the costs of manufacturing that require close partnerships with materials suppliers. Intel is driving for unprecedented collaboration among the materials and sub tier suppliers to achieve cost, performance and defect targets.  The cost of packaging and shipping materials globally is driving investigation into new operating models to cut costs.

Dennis Hausmann of LamRC/NVLS discussed ALD/CVD in more details than others.  For Each CVD/ALD step, an average of $2-$3/wafer is added to manufacturing cost, while only about $1/wafer of this is for chemistry+power+exhaust management.  He reviewed at least 4 versions of ALD tools (furnaces to single wafer) and said that there is a “right ALD tool” for the right deposition job.  He said that single wafer tools with proper development can meet same throughput as batch furnaces.  However, if you look at the development cost, single wafer tools are much better in cost.  For depositions that improve with plasma ALD, single wafer tools also make sense.  An important observation by Dennis was that for ALD, sometimes it is the unknown contaminant that “makes it go”.  This is something that has been observed in the past of copper plating chemistries, as well as some CMP slurries.

James ONeil, CTO Entegris had an interesting title, which should fit most suppliers “Accelerating yield in a disruptive environment”.  James emphasized that suppliers need meaningful process discussions, insights & collaboration with their customers.

Adrienne Pierce of Edwards introduced SCIS collaboration to most of us.  This is a supply chain collaboration working group.  Some topics are tracing defects origins and BKMs for specific process (e.g. ALD).

There were then two parallel sessions; one on advanced memories and the other on 3D packaging.  In the memory session, Norma Sosa of IBM talked about PCRAM (phase change memory, which Micron has been shipping for a few years now), Mark Raynor, Matheson, discussed RRAM for Non-Volatile, and Suresh Upa, SanDisk, discussed packaging implications.

After the breakout, we had presentations from four materials supplier companies.  The four same very similar things.  Dave Bern of Dow Chemical discussed using the “right tool” for collaboration and the importance of making sure suppliers agree to work in areas that fit their “core competencies”.  Wayne Mitchel of Air Products noted that ICs are only 2% of GDP.  He agreed with Dave Bern that suppliers should only agree to work (partner) with customer on areas within expertise, otherwise it takes too much time and money to execute successfully. Jean Marc Girard, Air Liquide discussed the numerous risks of supply chain, from the sub-supplier, the environment (e.g. earthquakes), and materials stability (or lack thereof). Kevin O’Shea of SAFC Hitech emphasized that taking materials from a catalog of low volume and ramping to IC manufacturing needs is not trivial, and may also not be consistent with the materials manufacturer (the sub-supplier, or company that is “primary” in the materials).

The day 2 Panel discussion had more audience participation.  Some discussions I found particularly interesting are discussed below.

Tim (Intel) said the gap is getting wider between Intel, suppliers, sub-suppliers (esp. customs for IC industry). The large sub-supplier that doesn’t have an interest in moving forward – there is no motivation to increase metrology, metrics, etc.  The shrinking sub-supplier base isn’t good for our industry – reduction in cost per bit comes from shrinks and reuse of capital, not only lower cost materials..

Kurt Carlson said that sub suppliers don’t think IC fabrication is the best industry – the IC industry wants more and more, yet wants to pay less and less.  It’s not worth it to us (good sub-suppliers leave because it’s too costly for the small volumes).

Jean Marc said they don’t want to duplicate development costs, if they don’t need to; they would rather use universities and share on things like toxicology.

Dave said it costs millions of dollars to test materials, like EUV.

Mansour Moinpour asked about collaboration on liquid particle, GCMS, and similar – can we have joint & consistent measurements across the industry?  James Entegris responded that end user need to be drivers.  Jean Marc suggested that maybe SEMI standards could drive a standard of industrial analytics.

The value of roadmaps was very different to the various participants, however the idea of regulatory alignment and a roadmap related to this was generally thought to be useful.

The question of cost and logistics … there are some materials that require shipping a lot of water, which adds cost.  Intel said that they are getting into more cost sensitive mobile market and they may be driven to this rather than exact materials copy in near future.  Tim said the Intel CEO is “hell bent” that Intel will make money in the mobile market.  “Intel will pull it off.”

Research Alert: August 12, 2014

Tuesday, August 12th, 2014

SRC, UC Davis explore new materials and device structures to develop next-generation “Race Track Memory” technologies

University of California, Davis researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, are exploring new materials and device structures to develop next-generation memory technologies.

The research promises to help data storage companies advance their technologies with predicted benefits including increased speed, lower costs, higher capacity, more reliability and improved energy efficiency compared to today’s magnetic hard disk drive and solid state random access memory (RAM) solutions.

Conducted by UC Davis’ Takamura Research Group that has extensive experience in the growth and characterization of complex oxide thin films, heterostructures and nanostructures, the research involves leveraging complex oxides to manipulate magnetic domain walls within the wires of semiconductor memory devices at nanoscale dimensions. This work utilized sophisticated facilities available through the network of Department of Energy-funded national laboratories at the Center for Nanophase Materials Sciences, Oak Ridge National Laboratory and the Advanced Light Source, Lawrence Berkeley National Laboratory.

“We were inspired by the ‘Race Track Memory’ developed at IBM and believe complex oxides have the potential to provide additional degrees of freedom that may enable more efficient and reliable manipulation of magnetic domain walls,” said Yayoi Takamura, Associate Professor, Department of Chemical Engineering and Materials Science, UC Davis.

Existing magnetic hard disk drive and solid state RAM solutions store data either based on the magnetic or electronic state of the storage medium. Hard disk drives provide a lower cost solution for ultra-dense storage, but are relatively slow and suffer reliability issues due to the movement of mechanical parts. Solid state solutions, such as Flash memory for long-term storage and DRAM for short-term storage, offer higher access speeds, but can store fewer bits per unit area and are significantly more costly per bit of data stored.

An alternative technology that may address both of these shortcomings is based on the manipulation of magnetic domain walls, regions that separate two magnetic regions. This technology, originally proposed by IBM researchers and named ‘Race Track Memory,’ is where the UC Davis work picked up.

Notre Dame paper offers insights into a new class of semiconducting materials

A new paper by University of Notre Dame researchers describes their investigations of the fundamental optical properties of a new class of semiconducting materials known as organic-inorganic “hybrid” perovskites.

The research was conducted at the Notre Dame Radiation Laboratory by Joseph Manser, a doctoral student in chemical and biomolecular engineering, under the direction of Prashant Kamat, Rev. John A. Zahm Professor of Science. The findings appear in a paper in the August 10 edition of the journal Nature Photonics.

The term “perovskites” refers to the structural order these materials adopt upon drying and assembling in the solid state.

“Hybrid perovskites have recently demonstrated exceptional performance in solid-state thin film solar cells, with light-to-electricity conversion efficiencies approaching nearly 20 percent,” Manser said. “Though currently only at the laboratory scale, this efficiency rivals that of commercial solar cells based on polycrystalline silicon. More importantly, these materials are extremely easy and cheap to process, with much of the device fabrication carried out using coating and or printing techniques that are amenable to mass production. This is in stark contrast to most commercial photovoltaic technologies that require extremely high purity materials, especially for silicon solar cells, and energy-intensive, high-temperature processing.”

Manser points out that although the performance of perovskite solar cells has risen dramatically in only a few short years, the scientific community does not yet fully know how these unique materials interact with light on a fundamental level.

Manser and Kamat used a powerful technique known as “transient absorption pump-probe spectroscopy” to examine the events that occur trillions of a second after light absorption in the hybrid methylammonium lead iodide, a relevant material for solar applications. They analyzed both the relaxation pathway and spectral broadening in photoexcited hybrid methylammonium lead iodide and found that the excited state is primarily composed of separate and distinct electrons and holes known as “free carriers.”

“The fact that these separated species are present intrinsically in photoexcited hybrid methylammonium lead iodide provides a vital insight into the basic operation of perovskite solar cells,” Manser said. “Since the electron and hole are equal and opposite in charge, they often exist in a bound or unseparated form known as an ‘exciton.’ Most next-generation’ photovoltaics based on low-temperature, solution-processable materials are unable to perform the function of separating these bound species without intimate contact with another material that can extract one of the charges. ”

This separation process siphons energy within the light absorbing layer and restricts the device architecture to one of highly interfacial surface area. As a result, the overall effectiveness of the solar cell is reduced.

Pairing old technologies with new for next-generation electronic devices

UCL scientists have discovered a new method to efficiently generate and control currents based on the magnetic nature of electrons in semiconducting materials, offering a radical way to develop a new generation of electronic devices.

One promising approach to developing new technologies is to exploit the electron’s tiny magnetic moment, or ‘spin’. Electrons have two properties – charge and spin – and although current technologies use charge, it is thought that spin-based technologies have the potential to outperform the ‘charge’-based technology of semiconductors for the storage and process of information.

In order to utilise electron spins for electronics, or ‘spintronics’, the method of electrically generating and detecting spins needs to be efficient so the devices can process the spin information with low-power consumption. One way to achieve this is by the spin-Hall effect, which is being researched by scientists who are keen to understand the mechanisms of the effect, but also which materials optimise its efficiency. If research into this effect is successful, it will open the door to new technologies.

The spin-Hall effect helps generate ‘spin currents’ which enable spin information transfer without the flow of electric charge currents. Unlike other concepts that harness electrons, spin current can transfer information without causing heat from the electric charge, which is a serious problem for current semiconductor devices. Effective use of spins generated by the spin-Hall effect can also revolutionise spin-based memory applications.

The study published in Nature Materials shows how applying an electric field in a common semiconductor material can dramatically increase the efficiency of the spin-Hall effect which is key for generating and detecting spin from an electrical input.

The scientists reported a 40-times-larger effect than previously achieved in semiconductor materials, with the largest value measured comparable to a record high value of the spin-Hall effect observed in heavy metals such as Platinum. This demonstrates that future spintronics might not need to rely on expensive, rare, heavy metals for efficiency, but relatively cheap materials can be used to process spin information with low-power consumption.

As there are limited amounts of natural resources in the earth and prices of materials are progressively going up, scientists are looking for more accessible materials with which to develop future sustainable technologies, potentially based on electron spin rather than charge. Added to this, the miniaturization approach of current semiconductor technology will see a point when the trend, predicted by Moore’s law, will come to an end because transistors are as small as atoms and cannot be shrunk any further. To address this, fundamentally new concepts for electronics will be needed to produce commercially viable alternatives which meet demands for ever-growing computing power.

Blog review July 21, 2014

Monday, July 21st, 2014

Matthew Hogan, a Product Marketing Manager for Calibre Design Solutions at Mentor Graphics, blogs that SoC Reliability Verification Doesn’t Just Happen, You Know. He says the best way to verify multi-IP, multiple power domain SoCs, is with the Unified Power Format (UPF), which enables a repeatable, comprehensive, and efficient design verification methodology, using industry standards, at the transistor level.

Dick James, Senior Technology Analyst, Chipworks, has a TSMC-fabbed 20-nm part in-house, and is looking forward to the analysis results. Wondering what changes TSMC has made from the 28-nm process, Dick says he expects mostly a shrink of the latter process, with no change to the materials of the high-k stack, though maybe to the sequence.

Ed Korczynski continues his theme of “Moore’s Law is Dead” with a third installment that looks at when that might happen. He says that at ~4nm pitch we run out of room “at the bottom,” after patterning costs explode at 45nm pitch.

Vivek Bakshi, EUV Litho, Inc. blogs about The 2014 EUVL Workshop which was held late last month amid some positive highlights and lots of R&D updates. The keynote talks this year were from Intel, Gigaphoton and Toshiba.

In his 201st Insights from The Leading Edge (IFTLE) blog post, Phil Garrou takes a look at some of the presentations at this year’s ConFab. Subramani Kengeri, Vice President, Advanced Technology Architecture for GlobalFoundries discussed the techno-economics of the semiconductor industry. Gary Patton, VP of IBM Semiconductor Research & Development Center addressed “Semiconductor Technology: Trends, Challenges, & Opportunities.” Adrian Maynes, 450C program manager, discussed the “450mm Transition Toward Sustainability: Facility & Infrastructure Requirements.”

Zvi Or-Bach, President and CEO of MonolithIC 3D Inc., blogs that over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

Blog review July 14, 2014

Monday, July 14th, 2014

Ed Korzynski blogs that Moore’s Law is dead – including what and when in the first two parts of a four part series that reference an interview with Gordon Moore and the “so-called” Moore’s Law (by Moore himself).

Pete Singer also blogs on continued scaling, as discussed by IBM’s Gary Patton at The ConFab in June. Patton said scaling will continue but the industry needs to address costs in addition to continued technology innovation.

Many of the developments in the semiconductor industry have stemmed from the continued progress in lithography. However, with the persistent uncertainty of extreme ultraviolet EUV for future-generation patterning, the industry has developed techniques such as self-alignment double patterning (SADP) to extend optical lithography. In a video produced by SPIETV, Chris Bencher of Applied Materials Office of the Chief Technology Officer, reviews the evolution of SADP and looks to its future.

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu. Adele Hars reports.

The 5th annual Suss Technology Forum was recently held at SEMICON West focused on trends in 3DIC and WLP. Phil Garrou reports in his latest blog.

Qualcomm: Scaling down is not cost-economic anymore – so we are looking at true monolithic 3D

Monday, June 16th, 2014

By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

Over the course of three major industry conferences (VLSI 2013, IEDM 2013 and DAC 2014), executives of Qualcomm voiced a call for monolithic 3D “to extend the semiconductor roadmap way beyond the 2D scaling” as part of their keynote presentations.

Karim Arabi, Qualcomm VP of Engineering, voiced the strongest support and provided many details of monolithic 3D’s role, in his keynote at this year’s DAC. A good summary was posted at the Tech Design Forums site under the title “3D and EDA need to make up for Moore’s Law, says Qualcomm.” In this blog, I’ll highlight some of the very interesting quotes from Arabi’s keynote: “Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase. One of the biggest problems is cost. We are very cost sensitive. Moore’s Law has been great. Now, although we are still scaling down, it’s not cost-economic anymore”

Qualcomm is not the only fabless company voicing its concern with cost. Early in 2013 Nvidia said it is “deeply unhappy” and executives of Broadcom followed suite. The following chart, presented by ARM, illustrates it nicely.

But it seems that the problem is even more severe than that. In our blog Moore’s Law has stopped at 28nm we examined the expected increase of SoC cost due to poor scaling of embedded SRAM (eSRAM). We should note that the chart above, like many others, is about the cost per transistor associated with dimensional scaling. Escalating lithography cost causes escalating wafer cost, which neutralizes the 2X transistor density increases.

Yet eSRAM scales far less than 2X and, accordingly, for most SOCs, scaling would be even more costly. This issue has been confirmed again with the recent VLSI 2014 paper “10-nm Platform Technology Featuring FinFET on Bulk and SOI” by Samsung, IBM, STMicroelectronics, GLOBALFOUNDRIES and UMC. They presented that the size of their 10nm bitcell is 0.053 µm², which is only 25 percent smaller than the 0.07 µm² reported for 14nm bitcell size. One should expect that an additional area penalty would occur for effective use in large memory blocks, as reported even for 14nm, which could bring the effective SRAM scaling to only about 15 percent, a long way from the 50 percent required to neutralize the escalating wafer costs.

However, cost is not the only issue that forced Qualcomm to consider monolithic 3D. Quoting Arabi:

“Interconnect RC is inching up as we go to deeper technology. That is a major problem because designs are becoming interconnect-dominated. Something has to be done about interconnect. What needs to be done is monolithic three-dimensional ICs. Through-silicon vias and micro bumps are useful where you need I/Os … But they are not really solving the interconnect issue I’m talking about … So we are looking at true monolithic 3D. You have normal vias between different stacks. Then interconnect lengths will be smaller than with 2D. If we can connect between layers the delay becomes smaller.”

The interconnect issue was also addressed at IEDM 2013 by Geoffrey Yeap, Qualcomm VP of Technology, in his invited talk:

“As performance mismatch between transistors and interconnects continue to increase, designs have become interconnect-limited. Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.”

Yeap provided the following chart for the growing gap between transistor delay and interconnect delay:

Arabi DAC 2014 keynote was also reported on Cadence’s website, which provides our final Arabi quote for this blog: Qualcomm is looking at “monolithic” 3D-ICs that use normal vias between stacked dies. This can provide a one-process-node advantage along with a 30 percent power savings, 40 percent performance gain, and 5-10 percent cost savings.

Clearly, monolithic 3D integration has a very important role in the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S conference is scheduled for October 6-9, 2014 at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3DIC, and researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

Applied Materials – Tokyo Electron Merger Hastens EDA Changes

Monday, September 30th, 2013

Paradoxically, the merger of equipment manufacturers AMAT and TEL may shrink the Electronic Design Automation (EDA) tool market while improving IP security.

In the last several days, much has been written about the proposed merger of Applied Materials (AMAT) and Tokyo Electron (TEL). Desired by both, this merger would create a company worth $29B that would be the largest semiconductor equipment company in the world by sales. In comparison, the EDA tool market is roughly valued at $1.1B.

This merger of capital equipment giants represents an ongoing consolidation of the semiconductor supply chain, from chip/component developers through the IDM/foundries and manufacturing space. One reason for this consolidation is the increasingly high costs of making chips smaller and smaller – e.g., at the leading edge process nodes.

At first glance, it would appear that the merger will have little impact on the world of semiconductor intellectual property (IP). Still, one of the stated goals of the merged companies is to extract costs, “from all layers of the supply chain,” according to a recent report from Canaccord Genuity’s analyst Josh Baribeau (see, “Size Matters: Our First Take on AMAT’s Proposed Merger with Tel.”)

While admittedly far down on the supply chain relative to capital equipment, the Electronic Design Automation (EDA) tool market – heavy dependent on design and verification IP – might feel the effects of this merger in several ways.

First, equipment manufactures use EDA tools and related processes to qualify new manufacturing systems. For example, last year Applied Materials supplied critical film properties (new materials) and device characterization data from its advanced process systems to Synopsys. This allowed the EDA vendor to create more accurate chip design and verification models.

Such new materials and processes are necessary to keep Moore’s Law on track, in contrast to the ever increasing lithographic costs at lower and lower nodes. Several new technologies and process node shrinks are also driving up the cost of manufacturing leading edge chips – such things as 3D NAND devices, 450mm wafers, finFET structures, stacked dies and more.

Still, the cost of EDA tools are low in relationship to other costs. According to long-time EDA analyst Gary Smith, the cost of EDA tools is analogous to lunch money. The real costs in SoC development are related to the cost of engineers to do the design. Greater level of chip design-verification tool automation will reduce these costs, as will, “the reuse of software, the reuse of verifiable design IP, and by reducing SoC core blocks below the typical five blocks.” (see, “Gary Smith’s Sunday Night, Pre-DAC Forecast”)

It may well be that consolidation by the equipment manufactures will result in accelerated consolidation of the lower part of the semiconductor supply chain, e.g., EDA tool vendors. Judging from the furry of acquisitions in the EDA community over the last several years, this scenario is hardly surprising.

On the other hand, this merger of equipment giants might be a good thing for the development of soft IP standards. As Warren Savage pointed out a few months ago (see, “Long Standards, Twinkie IP, Macro Trends, and Patent Trolls“), the semiconductor equipment companies need to approve any IP design standards since it will be their systems that must read the soft IP.

Consolidation of the equipment market should mean fewer companies that need to approve any such standards, thus (in theory) hastening the approval process.

Will the end result of the AMAT and TEL merger mean further consolidation of EDA tools and hence the IP markets? Will the merger lead to greater IP protection at the lower process nodes? The answer will probably be revealed in the next installment of Moore’s Law, i.e., the next process node advancement.

450mm in 2017: It’s Coming

Monday, May 27th, 2013

By Pete Singer

The switch to 450mm will likely be the largest, most expensive retooling the semiconductor industry has ever experienced. 450mm fabs, which will give an unbeatable competitive advantage to the largest semiconductor manufacturers, are likely to cost $10 billion and come on-line in 2017, with production ramp in 2018.
Unprecedented technical challenges still need to be overcome, but work is well underway at an R&D center in upstate New York, at the Global 450mm Consortium, G450C. Paul Farrar Jr., the G450C General Manager, recently spoke on the current status of activities, key milestones and schedules during a webcast produced by Solid State Technology.
“At this point, we have contracts with 12 major suppliers, and we have tools that are being delivered to the consortium starting in April and continuing through 2015,” Farrar said.
The G450C team now has over 60 engineers and assignees from the member companies. The goal is to have more than 150 engineers by 2014, with approximately 60 supplier engineers on site. “2013 and early 2014 will be about getting tools installed and up and running. Then the integration and unit process scientists will continue from there,” Farrar said.
Farrar said G450C has commitments for 112 process levels. For 45 processes, two suppliers are developing products (which equates to 90 process levels). A few have three suppliers, and about 10 process steps have one supplier. Farrar said that he sees 300mm and 450mm development continuing simultaneously. “We certainly know that for the next six or seven years, the industry will be developing and bringing capability to both 300mm and 450mm. A key goal here is to make sure that we do not slow down the scaling required for Moore’s Law to go from say 20nm to 15 to 12 to 10, etc. versus the cost reduction you get from going to a larger wafer size. We need to both of these things simultaneously as an industry,” he said. “A rough target is to get to 10nm, and then in 2016 we want to be ready for IC makers to make their decisions on when they will ramp to 450mm.”

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