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Comfortable Consumer EEG Headset Shown by Imec and Holst Centre

Thursday, August 27th, 2015


By Ed Korczynski, Sr. Technical Editor

A new wireless electroencephalogram (EEG) headset that is comfortable while providing medical-grade data acquisition has been shown by the partnership of imec, the Holst Centre, and the Industrial Design Engineering (IDE) department of TU Delft. The 3D-printed low-volume product enables early research and self-monitoring of emotions and mood in daily life situations using a smartphone application. Consumer applications include games that monitor relaxation and/or concentration, and medical applications that help with sleep disorders and treatment of Attention Deficit Hyperactivity Disorder (ADHD).

Figure 1 shows the new headset with novel elastic electrode arrays in an elegant uni-body assembly to optimize both comfort and signal quality. The electronics package in the middle of the headset fits on the back of the user’s neck. Each electrode is a small array of elastic polymer fingers which allow for dry contact—without needing a conductive liquid or gel—to skin for long-term comfortable use.

Figure1: Comfortable EEG headset developed by imec and Holst Centre and TU Delft in 2015, providing medical-quality data tracing of emotions and mood in daily life situations using a smartphone application. (Source: imec)

“Leveraging imec’s strong background in EEG sensing, dry polymer and active electrodes, miniaturized and low-power data acquisition, and low-power wireless interfaces to smartphones, we were able to focus on the ergonomics of this project. In doing so, we have successfully realized this unique combination of comfort and effectiveness at the lowest possible cost to the future user,” stated Bernard Grundlehner, EEG system architect at imec.

In 2011, imec and Holst Centre created an 8-channel ultra-low-power analog readout application-specific integrated circuit (ASIC) that consumes only 200µW and features high common mode rejection ratio (CMRR) of 120dB and signal to noise ratio of 25dB on real EEG signals. This ASIC is tuned to high input impedance (1GΩ) for compatibility with the use of dry electrodes. That system—including ASIC, radio, and controller chips— could be integrated in a package of 25mmx35mmx5mm dimensions for easy of integration in headsets, helmets, or other accessories. That system consumes only 3.3mW for continuous recording and wireless transmission of 1 channel—9.2mW for 8 channels—allowing for 1.5 to 4 days of functionality when powered by a 100mAh Li-ion battery.

In 2009, imec and Holst Centre showed off a rough mobile EEG prototype to partners and journalists at the yearly imec Technology Forum. Figure 2 shows that the prototype was bulky and a bit awkward to wear, while the figure does not show that sintered silver/silver-chloride electrodes are very hard such that dry contact to the human scalp tends to be uncomfortable.

Figure2: Ed Korczynski tests an imec EEG headset rough prototype, using uncomfortable hard silver/silver-chloride electrodes, at the 2009 Imec Technology Forum. (Source: Ed Korczynski)

The 2015 model uses new flexible electrodes arrays which are inherently more comfortable than hard silver/silver-chloride electrodes. A team of six master students from IDE of TU Delft led the design optimization of the 3D unibody for the new headset using 3D printing for short-loop prototyping and testing of different shapes for stability and comfort. Iterative tests with users for multiple applications led to this design which is intended for long-term comfortable use by consumers outside of a controlled research environment.

The new EEG headset is manufactured in one piece using 3-D printing, after which the electronic components are placed, connected, and covered by a 3-D-printed rubber inlay. The EEG electrodes are situated at the front of the headset for optimal acquisition of signals related to emotion and mood variations. A mobile app can then tie the user’s emotional state to environmental information such as location, time, agenda, and social context to track possible unconscious effects.


MicroWatt Chips shown at ISSCC

Thursday, March 5th, 2015


By Ed Korczynski, Sr. Technical Editor

With much of future demand for silicon ICs forecasted to be for mobile devices that must conserve battery power, it was natural for much of the focus at the just concluded 2015 International Solid State Circuits Conference (ISSCC) in San Francisco to be on ultra-low-power circuits that run on mere microWatts (µW). From analog to digital logic to radio-frequency (RF) chips and extending to complete system-on-chip (SoC) prototypes, silicon IC functionality is being designed with evolutionary and even revolutionary reductions in the operational power needed.

The figure shows a multi-standard 2.4 GHz radio that was co-developed by imec, Holst Centre, and Renesas using a 40nm node CMOS process. This was detailed in session 13.2 when Y.H. Liu presented “A 3.7mW-RX 4.4mW-TX Fully Integrated Bluetooth Low-Energy/IEEE802.15.4/Proprietary SoC with an ADPLL-Based Fast Frequency Offset Compensation in 40nm CMOS.” It uses a digital-intensive RF architecture tightly integrated with the digital baseband (DBB) and a microcontroller (MCU), and the digital-intensive RF design reduces the analog core area to 1.3mm2, and the DBB/MCU/SRAM occupies an area of 1.1mm2. This is an evolution of a previous 90nm RF front-end design that results in a reduced supply voltage (20 percent), power consumption (25 percent), and chip area (35 percent).

Ultra-low-power multi-standard 2.4 GHz radio compliant with Bluetooth Low Energy and ZigBee, co-developed by imec, Holst Centre, and Renesas. (Source: Renesas)

“From healthcare to smart buildings, ubiquitous wireless sensors connected through cellular devices are becoming widely used in everyday life,” said Harmke De Groot, Department Director at imec. “The radio consumes the majority of the power of the total system and is one of the most critical components to enable these emerging applications. Moreover, a low-cost area-efficient radio design is an important catalyst for developing small sensor applications, seamlessly integrated into the environment. Implementing an ultra-low power radio will increase the autonomy of the sensor device, increase its quality, functionality and performance and enable the reduction of the battery size, resulting in a smaller device, which in case of wearable systems, adds to user’s comfort.”

When most ICs were used in devices and systems that were powered by line current there was no advantage to minimizing power consumption, and so digital CMOS circuits could be designed with billions of transistors switching billions of times each second resulting in sufficient brute-force power to solve most problems. With power-consumption now a vital aspect of much of the demand for future chips, this year’s ISSCC offered the following tutorials on low-power chips:

  • “Ultra Low Power Wireless Systems” by Alison Burdett of Toumaz Group (UK),
  • “Low Power Near-threshold Design” by Dennis Sylvester of University of Michigan, and
  • “Analog Techniques for Low-Power Circuits” by Vadim Ivanov of Texas Instruments.

Then on Thursday the 26th, an entire short course was offered on “Circuit Design in Advanced CMOS Technologies:  How to Design with Lower Supply Voltages.” with lectures on the following:

  • “A Roadmap to Lower Supply Voltages – A System Perspective” by Jan M. Rabaey of UC Berkeley,
  • “Designing Ultra-Low-Voltage Analog and Mixed-Signal Circuits” by Peter Kinget of Columbia University,
  • “ACD Design in Scaled technologies” by Andrea Baschirotto of University of Milan-Bicocca, and
  • “Ultra-Low-Voltage RF Circuits and Transceivers” by Hyunchoi Shin of Kwangwoon University.

µW SoC Blocks

Session 5.10 covered “A 4.7MHz 53µW Fully Differential CMOS Reference Clock Oscillator with -22dB Worst-Case PSNR for Miniaturized SoCs” by J. Lee et al. of the Institute of Microelectronics (Singapore) along with researchers from KAIST and Daegu Gyeongbuk Institute of Science and Technology in Korea. While many SoCs for the IoT are intended for machine-to-machine networks, human interaction will still be needed for many applications so session 6.7 covered “A 2.3mW 11cm-Range Bootstrapped and Correlated-Double-Sampling (BCDS) 3D Touch Sensor for Mobile Devices” by L. Du et. al. from UCLA (California).

As indicated by the low MHz speed of the clock circuit referenced above, the only way that these ICs can consume 1/1000th of the power of mainstream chips is to operate at 1/1000th the speed. Also note that most of these chips will be made using 90nm- and 65nm-node fab processes, instead of today’s leading 22nm- and 14nm-node processes, as evidenced by session 8.3 covered “A 10.6µA/MHz at 16MHz Single-Cycle Non-Volatile Memory-Access Microcontroller with Full State Retention at 108nA in a 90nm Process” by V.K. Singhal et al. from the Kilby Labs of Texas Instruments (Bangalore, India). Session 18.3 covered “A 0.5V 54µW Ultra-Low-Power Recognition Processor with 93.5% Accuracy Geometric Vocabulary Tree and 47.5 Database Compression” by Y. Kim et al. of KAIST (Daejeon, Korea).

In the Low Power Digital sessions it was natural that ARM Cortex chips were the basis for two different presentations on ultra-low power functionality, since ARM cores power most of the world’s mobile processors, and since the RISC architecture of ARM was deliberately evolved for mobile applications. Session 8.1 covered “An 80nW Retention 11.7pJ/Cycle Active Subthreshold ARM Cortex-M0+ Subsystem in 65nm CMOS for WSN Applications” by J. Myers et al. of ARM (Cambridge, UK). In the immediately succeeding session 8.2, W. Lim et al. of the University of Michigan (Ann Arbor) presented on the possibilities for “Batteryless Sub-nW Cortex-M0+ Processor with Dynamic Leakage-Suppression Logic.”

nW Beyond Batteries

Session 5.4 covered “A 32nW Bandgap Reference Voltage Operational from 0.5V Supply for Ultra-Low Power Systems” by A. Shrivastava et al. of PsiKick (Charlottesville, VA). PsiKick’s silicon-proven ultra-low-power wireless sensing devices are based on over 10 years of development of Sub-Threshold (Sub-Vt) devices. They are claimed to operate at 1/100th to 1/1000th of the power budget of other low-power IC sensor platforms, allowing them to be powered without a battery from a variety of harvested energy sources. These SoCs include full sensor analog front-ends, programmable processing and memory, integrated power management, programmable hardware accelerators, and full RF (wireless) communication capabilities across multiple frequencies, all of which can be built with standard CMOS processes using standard EDA tools.

Extremely efficient energy harvesting was also shown by S. Stanzione et al. of Holst Centre/ imec/KU Leuven working with OMRON (Kizugawa, Japan) in session 20.8 “A 500nW Battery-less Integrated Electrostatic Energy Harvester Interface Based on a DC-DC Converter with 60V Maximum Input Voltage and Operating From 1μW Available Power, Including MPPT and Cold Start.” Such energy harvesting chips will power ubiquitous “smarts” embedded into the literal fabric of our lives. Smart clothes, smart cars, and smart houses will all augment our lives in the near future.


The Challenges Of 28nm HKMG

Tuesday, June 26th, 2012

28nm Super Low Power (28nm-SLP) is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. This technology has four Vt’s (high, regular, low and super low) for design flexibility with multi-channel length capability and offers the ultimate in small die size and low cost. Multiple SRAM bit cells for high density and high-performance are available. With the simpler process integration of a “Gate-First” HKMG scheme, 28nm-SLPalso offers the use of an eFuse, which is known to be more competitive and superior than a BEOL copper fuse solution.

To read more, click here.