By Mark LaPedus
It’s the tale of two promising and separate 3D chip architectures. One technology is slowly taking root, while the other one is heating up.

3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and SK Hynix are accelerating their efforts in the arena.

Presently, NAND vendors are on the 2xnm or 1xnm nodes. The prevailing thought was that vendors would scale existing planar NAND at three distinct points down the 1xnm node. Typically, NAND vendors denote those points as 1x, 1y and 1z. Then, after the so-called 1z or 1znm node, planar NAND supposedly would hit the scaling wall, forcing vendors to migrate to 3D NAND.

In fact, 2D NAND will have difficulties scaling beyond 10nm. This is because the critical structure in NAND—the floating gate—is seeing an increase in the dreaded cell-to-cell interference in the word lines.

SanDisk still plans to scale NAND for two more generations until 2016, and then, it will debut 3D NAND. But in what appears to be a switch in strategy, Samsung and SK Hynix plan to develop 2D NAND at the 1x and 1y nodes. Then, “it appears that Samsung is bypassing 1z, similar to SK Hynix,” said Doug Freedman, an analyst with RBC Capital Markets.

Instead of going to 1z, Samsung and Hynix will move directly to 3D NAND. In fact, Samsung will begin sampling parts in the second half of 2013, with production slated for 2014, Freedman said.

“As there is maybe one more shrink left for planar NAND, some manufacturers are making the transition earlier to 3D NAND,” said Greg Wong, an analyst with Forward Insights. “Scaling of planar NAND is nearing its end, and 3D NAND is seen as the way to continue density increases and cost reductions for NAND flash memory.”

With 3D NAND, memory vendors also will move from a costly lithography-centric production environment to a less-expensive etch/deposition flow, said Gill Lee, a senior director and principal member of the technical staff at Applied Materials. “The overall cost of the tools will be cheaper with 3D NAND,” Lee said “This is mainly driven by the difference in the number of critical lithography and double-patterning steps.”

3D NAND contenders
Samsung will bring out 3D NAND first, followed in order by SK Hynix, Toshiba and Micron, Forward Insights’ Wong said. In 3D NAND, Samsung hopes to leapfrog the competition and grab the early profits with its so-called terabit cell array transistor (TCAT) architecture.

In TCAT, NAND layers are stacked using an oxide and nitride deposition process. Then, the nitride is removed by an etch process. Finally, the bit and word lines are created using a tungsten fill. TCAT and other 3D NAND architectures are different than 2.5D/3D stack-die technologies, where devices are stacked and connected using TSVs.

Another NAND vendor, SanDisk, has a different strategy. “SanDisk is planning to remain planar until 2016, while competitors begin to develop and produce 3D (NAND) into the market late this year and early next,” said RBC’s Freedman. “SanDisk’s (3D NAND) solutions are being judiciously developed to cater to the high-performance market. The high-performance side of the market will not be ready to qualify 3D for another two to three years.”

Using 193nm immersion lithography, the SanDisk-Toshiba duo is producing 19nm planar NAND with a 19- x 26-nm cell size. Then, at 1y, SanDisk’s goal is to devise planar NAND with a 19- x 19.5nm cell size, with production slated by the end of this year.

Then, unlike Samsung and SK Hynix, SanDisk will scale planar at 1z. “There is no need to rush into 3D” until it is cost effective, said Ritu Shrivastava, vice president of technology at SanDisk. In reality, 2D NAND will remain the mainstream technology for some time. Over time, 3D NAND will move into high-end applications, like solid-state storage.

By 2016, SanDisk hopes to debut the Bit Cost Scalable (BiCS) technology, a 3D NAND technology that was originally conceived by Toshiba. BiCS makes use of a “punch-and plug” structure. Toshiba has fabricated a prototype 32-Gbit BiCS test array, with a 16-layer memory cell based on 60nm design rules.

The advantage of 3D NAND is that it doesn’t require leading-edge lithography. Going to 3D NAND will present some challenges, namely the development of quality parts with good read/write performance with endurance. “3D NAND will require a different equipment set,” Shrivastava said. “The burden will shift from lithography to deposition and etch.”

3D NAND process challenges
It also will present NAND vendors with some difficult decisions. First, despite their public roadmaps, vendors may be forced to migrate to 3D NAND sooner than later. “Most leading-edge producers are doing 2D NAND manufacturing at the 20nm or 19nm node, which is the last generation of self-aligned double patterning technology,” Applied’s Lee said. “By using self-align double patterning, one can pattern about 19nm or 19.5nm half-pitch.”

But for some time, the problem with 2D NAND has been apparent—it is running out of steam. “With existing planar NAND, there is not much room to squeeze in the materials for the charge-trap flash or the floating-gate,” Lee said.

In theory, NAND hits the wall at 10nm. “In order to scale NAND manufacturing beyond that, the industry must adopt self-aligned quadruple patterning or self-aligned triple pattering,” he said. “That allows for 10nm half-pitch. But doing 10nm half-pitch patterning will be extremely difficult. It will add a lot more process steps, which will increase the cost of manufacturing.”

Clearly, 3D NAND is the future based on two factors: scaling and cost. “If you compare the cost between sub-20nm planar versus 3D NAND, I believe it will be a lot cheaper to build a 3D NAND fab,” he said. “Planar is driven by litho. In 3D NAND, the bit growth is enabled by increasing the number of vertical layers. This has nothing to do with litho.”

3D NAND can be produced using existing 193nm lithography. Other expensive steps, such as self-align double-patterning etch and low-temperature atomic layer-deposition (ALD), are also eliminated. All told, 3D NAND is largely dependent on two technologies: deposition and etch.

The big challenge is to enable high-aspect ratios using new etch techniques. “There are three distinctly new etch processes in 3D NAND,” Lee said. “This includes high-aspect ratio memory hole etch, which did not exist in planar NAND. There is also a high-aspect ratio trench-line etch, which also did not exist in planar. And then another one is a so-called staircase etch. This is a very long process, which has to provide the landing pads for the contacts.”

3D NAND also introduces alternating stack deposition, which defines the vertical stack. In a 32-layer NAND device, for example, the process could involve some 64 layers of deposition, plus some dummy layers. All told, the flow requires some 70 alternating deposition steps. “The existing tools cannot provide such high productivity,” Lee said. “So that involves a new type of chamber design and technology.”

Metrology is also a critical part of the equation. “Nanometrics believes that 3D NAND will use 20% to 25% more OCD tools relative to planar NAND,” said Weston Twigg, an analyst with Pacific Crest Securities.

“In planar NAND, the gate width is defined by lithography,” added Applied’s Lee. “Now, the gate width is defined by deposition. So, the uniformity of PECVD deposition of each layer, and the quality of the films, are very critical. When we deposit several layers, it’s not a big deal. But let’s say we deposit 40, 50 or 70 layers in-situ. That means we have to control the surface of the interface very smoothly from the beginning. Otherwise, we end up with a rough surface on the top, which will not work.”

So far, Micron, Samsung, SanDisk-Toshiba and SK Hynix have yet to discuss the exact specifications for their respective 3D NAND devices. It’s unclear how many layers the initial devices will have, prompting many to ask a simple question: How far will 3D NAND scale? “I see it going for several generations,” Lee said. “But after 3D NAND, the industry will require another breakthrough.”

By Mark LaPedus

For years, the DRAM industry has been engulfed in a downturn. Sadly, vendors have grown accustom to overcapacity, falling ASPs and losses. Now, the tide is turning, at least based on the data from Micron Technology. Micron posted a loss this week, but the company provided some surprising and welcomed news about DRAMs. “Despite a weak PC environment and more DRAM capacity from the revised Inotera agreement, Micron is allocating DRAM to some channel and OEM customers. DRAM capacity continues to go offline or transition to NAND, and Micron envisions no new capacity coming online in either 2013 or 2014. This suggests to us that the recent ASP dynamic is here to stay,” said Hans Mosesmann, an analyst with Raymond James. Another chip analyst, Jagadish Iyer of Piper Jaffray, said: “Micron articulated that DRAM capacity likely remains constrained for the next two years as near-term allocation prevails.”

What about NAND flash? “We expect industry supply to be far more rational than years past. Expect NAND ASP trends to strengthen through 2Q ‘13 with handset ramps pending,” said Doug Freedman, an analyst with RBC Capital Markets. Added Monika Garg, an analyst with Pacific Crest: “During our meetings with semiconductor capital equipment companies last month, all companies highlighted that they have not yet received any NAND capacity orders. These comments lend conviction that we should see strong NAND supply-demand balance in 2013.”

Richard Hill, the former chairman and CEO of Novellus, is back in the news. Hill, an outspoken executive who left Novellus after it was acquired by Lam, is leading a committee of independent directors for troubled Tessera. The committee is refocusing Tessera’s DigitalOptics unit. This follows a move by an investment firm to oust Tessera’s CEO and the board.  This week, the board began a search for a new chief executive to replace Robert A. Young, who was ousted. And Hill is the new chairman.

The Saratoga County Industrial Development Agency has approved about $387 million in sales tax exemptions for GlobalFoundries, according to the Saratogian. The tax breaks are for an R&D center and a proposed fab in New York.

In a blog, an investment site discusses its price estimates for Applied Materials. It also gives a fair and balanced analysis of the company.

RF Micro Devices will phase out manufacturing in its Newton Aycliffe, U.K.-based GaAs pHEMT facility and transition most GaAs manufacturing to its GaAs HBT manufacturing facility in Greensboro, N.C. RFMD will also partner with leading GaAs foundries for additional capacity. The U.K.-based GaAs pHEMT facility had been RFMD’s primary source for cellular switches. However, RFMD has transitioned to higher-performance, lower-cost silicon-on-insulator (SOI) technology for the cellular switch.

North American-based manufacturers of semiconductor equipment posted a book-to-bill ratio of 1.10 in February, according to SEMI. This compares to a ratio of 1.11 in January.

SEMI has released the 4th edition of the International Technology Roadmap for PV (ITRPV), the global collaborative process that informs PV cell, module and system manufacturers, equipment and materials suppliers, and other industry stakeholders on key technology trends in the solar field.

Mentor Graphics and Mercedes-Benz Trucks announced the application of the Mentor Capital software suite to the development of Daimler’s flagship heavy truck, the new Actros.

TEL’s Q3 orders were up 27%, above the firm’s original guidance of “slightly up,” according to Chips and Dips, a blog site.

Golden Gate Capital, a venture capital firm, recently sold its e-beam company, Vistec, to two different companies. In one transaction, Raith recently acquired Vistec’s Gaussian e-beam unit, called Vistec Lithography. Vistec Lithography continues to specialize in conventional direct-write applications in the aerospace and military arena. In a separate move, the Heidenhain Group recently acquired Vistec’s variable shaped beam (VSB) e-beam unit. That operation, Vistec Electron Beam, sells a single-beam e-beam tool based on VSB technology.

Samsung’s new Galaxy S4 smartphone is causing a buzz. In a blog DisplaySearch answered a pressing question: How Did Samsung achieve full HD in the AMOLED display?

Spansion and XMC, a Chinese foundry, announced an expanded partnership to develop and manufacture Spansion’s 32nm NOR flash memory. The agreement expands XMC’s current 300mm manufacturing of Spansion’s 65nm and 45nm flash memory technology.

VLSI Research is raising its 2013 fab tool growth forecast to minus 4.6%. Previously, the 2013 forecast was minus 5.3%. “Memory suppliers are beginning to loosen their purse strings. The orders are technology buys. Capacity expansions are not in the radar. Foundry is cooling due to the pull back by Apple along with some inventory buildups,” according to the firm.

Global PC shipments were expected to decline by 7.7% in the first quarter, according to IDC. However, IDC’s February monthly data suggest that the market could see a drop touching double-digits in the first quarter, according to the firm.

A predicted surge of smaller, lower-priced devices in the tablet market has led IDC to increase its 2013 forecast for the worldwide tablet market to 190.9 million, up from its previous forecast of 172.4 million units.

Samsung catapulted to the top of the optoelectronics supplier ranking in 2012 from 12th place in 2011 after it gained full ownership of Samsung LED, a 50-50 joint venture in light-emitting diodes that was created in 2009 between Samsung Electronics and affiliate Samsung Electro-Mechanics, according to IC Insights.

By Mark LaPedus
Boeing should have chosen a safer type of lithium-ion battery chemistry for its new 787, according to Lux Research. At present, Boeing uses high-energy technology from GS Yuasa that suffers from thermal runaway. It should switch to an alternate type of lithium-ion battery, says the analyst firm.

At this week’s SEMI Industry Strategy Symposium (ISS), Samsung disclosed plans that it will offer 2.5D/3D foundry services. Like TSMC, Samsung will provide a turnkey solution, meaning it will offer the front- and back-end work for customers. “To start with, we will do it all in-house,” said Ana Hunter, vice president of foundry services at Samsung Semiconductor. “If everything comes from the same company, it’s going to save cost (and ensure quality).”

Also at ISS, Intel demonstrated the world’s first patterned 450mm wafer. The wafer was supplied by Sumco and the patterning was conducted on a nano-imprint tool from Molecular Imprints, said Robert Bruck, vice president of the Technology and Manufacturing Group at Intel. Now, the goal is to get “a thousand” wafers out to the equipment companies for 450mm development, he said.

Separately, Intel posted mixed results in the quarter. The chipmaker also issued guidance “for $13 billion in CapEx for 2013 as a meaningful surprise. Now, this includes $2 billion for 450mm development,” said C.J. Muse, an analyst at Barclays. The 450mm CapEx figure is non-equipment related. So, Intel’s real CapEx is $11 billion, flat from 2012 he said.

GlobalFoundries’ recent decision to build a new R&D center will accelerate its efforts to bring technologies from the lab to the fab, according to Ajit Manocha, chief executive of the company, at ISS.

The semiconductor industry is undergoing massive transformation, according to industry leaders speaking at ISS.

At ISS, Bill McClean, president of IC Insights, provided his forecast. The IC market is expected to grow 6% in 2013, following a 2% decline in 2012, he said. CapEx is expected to fall 10% in 2013, following another 10% drop last year, he said.

The Semiconductor Research Corp. (SRC) and the Defense Advanced Research Projects Agency (DARPA) announced that $194 million will be dedicated during the next five years to six university microelectronics research centers to support the continued growth of the U.S. semiconductor industry. The program, dubbed the Semiconductor Technology Advanced Research network (STARnet), includes several industry partners: Applied Materials, GlobalFoundries, IBM, Intel, Micron, Raytheon, Texas Instruments and United Technologies.

Applied Materials has been honored with the 2013 IEEE Corporate Innovation Recognition award for its contributions to PECVD technology for flat panel display manufacturing.

GlobalFoundries announced Alexie Lee, general counsel and executive vice president of legal and corporate affairs, was recognized by The Manufacturing Institute, Deloitte, University of Phoenix, and the Society of Manufacturing Engineers with a Women in Manufacturing STEP (Science, Technology, Engineering and Production) Award.

Troubled Japanese chip maker Renesas continues to restructure. As part of the moves, the company will consolidate more design units and fabs.

Micron Technology has entered into agreements with Nanya to amend their Taiwan DRAM joint venture involving Inotera Memories. Micron is transitioning to purchase all of Inotera’s manufacturing output. Under the prior agreements, Nanya and Micron were obligated to purchase half of Inotera’s output.

Intel’s recent introduction of a new Atom processor platform is designed to target the fast-growing market for low-end smartphones in emerging economies. It represents a shrewd strategy that could allow the company to expand its currently minimal market share in the industry, according to IHS iSuppli.

Worldwide revenues for microprocessors designed for mobile PCs, desktop PCs, and PC servers will grow a mere 1.6% to $40.7 billion in 2013, according to IDC.

By Mark LaPedus
Over the last year, leading-edge silicon foundries announced their new and respective strategies in the emerging 2.5D/3D chip arena. The ink is barely dry and now the foundry landscape is changing.

One new vendor, Tezzaron Semiconductor, is entering the market. The 3D DRAM supplier plans to provide select 2.5D/3D foundry services within its recently acquired fab in Austin, Texas.

In addition, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is tweaking its 2.5D/3D foundry strategy. Last year, TSMC announced a controversial turnkey solution. The company not only provides the front-end steps, but also the back-end work traditionally handled by the IC packaging houses. Now, instead of locking in customers with its front-to-back solution, TSMC is rethinking its position.

“We prefer to do it ourselves,” said Morris Chang, chairman and chief executive of TSMC, in a recent conference call. “We have become more flexible to partner with the OSATs.”

Two other vendors, GlobalFoundries and UMC, are sticking with their collaborative approaches. In that model, the foundries handle the front-end steps, but pass on the back-end work to the IC packaging houses.

Another foundry, IBM, has a slightly different strategy. Still to be seen, however, is what Intel and Samsung will do in the arena. And some of the IC packaging houses have given up the notion of doing fine-pitch interposers and through-silicon vias (TSVs). Instead, the OSATs are looking at doing course-pitch TSVs and interposers.

So, in general, there are two prevailing, leading-edge 2.5D/3D foundry models: TSMC’s turnkey solution and the rival collaborative approach. “I think both models will co-exist,” said David McCann, senior director of technical business operations for packaging and central engineering at GlobalFoundries.

Foundries go 3D
The memory bandwidth gap and resistivity problems in planar devices have fueled the development of 2.5D/3D chips. But advanced chip stacking has several challenges and is still a few years away from mass production. For example, TSMC will not see “significant revenue” in 2.5D/3D until 2015 or 2016, Chang said.

2.5D/3D technology and the associated supply chain are immature. Manufacturing costs are falling, but there is still a perception that the 3D devices will be prohibitively expensive, said Niranjan Kumar, product marketing manager for TSV programs at Applied Materials.

So far, only a few chipmakers have announced 3D chips. In 2010, Samsung rolled out one of the first 3D DRAMs using a 40nm process and TSVs. Then, last year, Samsung and Micron formed a consortium to develop a serial specification for a 3D DRAM technology called the Hybrid Memory Cube (HMC). Micron will sample HMC devices in 2013. Aimed at high-end applications, HMC will stack DRAM arrays on a logic chip. IBM is making the logic chip based on an SOI substrate.

Another 3D DRAM vendor, Tezzaron, recently has begun shipping its initial parts. But other 3D DRAM schemes, such as Wide I/O, have been delayed due to an assortment of technical issues. Still, the industry is making more progress on the 2.5D front. “The 2.5D era has arrived,” said E. Jan Vardaman, president of TechSearch International, a research firm.

To date, Altera, Cisco, IBM, Huawei and Xilinx have talked about or shipped 2.5D devices using interposers. In fact, Xilinx has shipped the Virtex-7 2000T FPGA, a product based on a 28nm process and a 65nm silicon interposer.

The device itself is built and assembled by TSMC, which refers to its 2.5D/3D turnkey solution as “Chip on Wafer on Substrate” (CoWoS). Using CoWoS, TSMC is also building a rival 2.5D FPGA for Altera. In CoWoS, the chip is attached to the substrate to form the final component. TSMC provides front-end manufacturing, TSV formation, interposers, chip-on wafer bonding, backside thinning, dicing and final test.

CoWoS has been given a lukewarm reception by the IC packaging houses, many of which believe that TSMC is taking a chunk of the backend business away from the OSATs. “For some customers, (CoWoS) works well. It doesn’t work for all customers,” Vardaman said.

TSMC has defended CoWoS, saying that the in-house, turnkey solution enables the foundry to ensure the quality of the chips and the production process. TSMC also assumes responsibility for the supply chain. “Technically, it is progressing well,” TSMC’s Chang said. “We are trying to reduce the costs.”

Beyond 2.5D FPGAs, TSMC recently taped out a Wide I/O device. To enable Wide I/O, the company requires DRAM from a third party. Originally, it was working with Elpida, which is being acquired by Micron. Now, TSMC is working with Micron and SK Hynix.

TSMC’s model may fall flat when customers ask for DRAM from Samsung. TSMC and Samsung are foundry competitors. It’s unlikely that Samsung will hand over DRAM wafers, along with its proprietary IP and test data to TSMC.

In some cases, it makes more sense to follow the collaborative model, where there are fewer conflicts. A customer can use its own logic and/or memory or buy it from a third party. The foundries do the front-end processing, while the OSATs collect and assemble the pieces.

With that scenario in mind, TSMC is warming up to the idea of working with OSATs to give customers more flexibility. TSMC also may be fending off its rivals, which are offering a collaborative approach.

More models

Others are moving full speed ahead with their strategies. Earlier this year, GlobalFoundries installed the tools to create 3D TSV devices on its 20nm platform within its fab in New York. It will handle the “via creation” steps. Then, it will hand off the traditional backend steps, such as temporary bonding/debonding, grinding and test, to the OSATs.

The foundry vendor also devised a low-volume, 2.5D line using 65nm interposers within its fab in Singapore. GlobalFoundries’ challenge is to demonstrate a smooth flow and good product yields at a competitive cost. “It’s going well,” said GlobalFoundries’ McCann. “The question is, can we make this collaborative supply chain model a one-to-one solution? We have to prove this to our customers.”

Another vendor, IBM, has been working on 2.5D/3D for years, including a specialized interposer technology. “IBM is working with Sematech to connect analog converter functions in a logic device with an interleaver IC in IBM’s BiCMOS SiGe technology,” said TechSearch’s Vardeman. “Applications are fiber optic telecom, high-performance RF, test equipment and processing for radar systems.”

The new kid on the foundry block is Tezzaron. In October, the company acquired the former SVTC fab in Austin. R&D foundry SVTC, which recently went bankrupt, originally acquired the fab from Sematech. Now, the fab operates under the name of Novati Technologies. Tezzaron is the sole shareholder in Novati. “We are going to become a 3D foundry,” said Robert Patti, chief technology officer at Tezzaron. “What we are trying to do is provide an open platform for 2.5D and 3D integration.”

Asked if Novati will compete against TSMC and GlobalFoundries, Patti said Novati can work with other foundries and will not compete against them. Novati will continue to serve SVTC’s customers. The Austin fab is a 200mm CMOS line, with 200mm/300mm backend capabilities.

As part of the plan, Tezzaron will shut down its current fab in Singapore and transfer the tools to the Austin fab by early 2013. By Q3 of next year, the company hopes to provide 3,000 wafer starts a week in Austin.

In the 2.5D/3D foundry arena, Novati will offer advanced stacking capabilities, TSVs and interposers. It can provide Tezzaron’s 3D DRAMs or procure third-party logic and memory chips. And Novati will offer both a turnkey and collaborative model. “We are willing to do a full turnkey solution,” Patti said. “I am willing to take the pieces and assemble them.”

The company prefers customers to use its so-called FaStack technology, which makes use of a proprietary bonding and tungsten process. Its 2.5D/3D technology is based on a 40nm process. By late 2013, it will offer a 28nm platform.

While the foundry landscape continues to evolve, several IC packaging houses are rethinking their plans. Some time ago, Taiwan’s Advanced Semiconductor Engineering (ASE) was looking at fine-pitch interposers and TSVs in a “via-last” production flow. “We have an interposer technology that we’ve promoted,” said Rich Rice, senior vice president of sales for North America at ASE. “We are not sure about the market acceptance.”

As it turns out, ASE discovered that leading-edge TSV and interposer work belongs in the foundries and not at the OSATs. “I think poking holes in silicon is mostly a foundry business,” he said at a recent event sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).

On the other hand, ASE and STATS are looking at course-pitch interposers and TSVs for niche applications like MEMS and RF. The OSATs will also play a major role in fine-pitch 2.5D/3D by offering the critical backend work.

TSMC and its turnkey model will not take all of the backend business away from the OSATs. TSMC is still going up the learning curve in the backend and may find the work a headache in the long run. “This is something we do day in and day out,” Rice added.

By Mark LaPedus
Gartner released its top five IT predictions for China in 2013 and beyond. In one prediction, Chinese PC maker Lenovo will become the top smartphone vendor in China by 2013. The company’s smartphone market share rose from 1.7 percent in 3Q ‘11 to 14.8% in 3Q ‘12, making it now the No. 2 smartphone brand, ahead of Apple (6.9%) and behind Samsung (16.7%).

The SOI Industry Consortium has organized a symposium that will address the world of fully-depleted SOI. The symposium will be held at the San Francisco Hilton Hotel on Dec. 10, concurrent with the IEDM 2012 Conference.

MagnaChip has expanded its foundry production for Peregrine Semiconductor’s STeP5 UltraCMOS technology, which is used for RF devices. UltraCMOS is an advanced form of silicon-on-insulator technology based on a sapphire substrate.

At the IEEE International Solid-State Circuits Conference (ISSCC), which is in San Francisco from Feb. 17 to 21, 2013, IBM will present a paper on a next-generation processor for its System z mainframe. The processor combines six 5.5 GHz processor cores and two memory chips in a ceramic MCM package. The processor has 2.75 billion transistors on a 598mm2 die. The 32nm chip makes use of a high-k/metal-gate scheme and SOI technology with 15 layers of metal. The chips are placed on a 102-layer MCM with two 192MB L4 cache ICs. This is said to achieve a total MCM bandwidth of 530GB/s.

Also at ISSCC, IBM will describe a 22nm SOI SRAM operating over a wide voltage range of 0.7V to 1.1V. It employs a fine granularity power-gating feature, which reduces bit cell leakage by 37% and also reduces peripheral circuit leakage by 40%.

During the event, AMD will describe a 28nm, 11-metal layer x86 processor. The so-called “Jaguar”quad-core processor runs at up to 1.85 GHz.

Oracle will take ISSCC to introduce its next-generation SPARC T5 processor in 28nm technology with 13 metal layers containing 1.5 billion transistors. The chip integrates 16 3.6 GHz cores and a shared 8MB L3 cache with a 9-port crossbar. Oracle also will demonstrate glueless scaling to 8 sockets, or 128 cores, to deliver a total of 1024 threads in a single system. Its new I/O system architecture enables over 5TB/s bandwidth.

At ISSCC, China’s Loongson Technology will demonstrate its latest 8-core microprocessor, dubbed the Godson-3B1500, based on a MIPS64 instruction set. Fabricated in a 32nm, high-k/metal-gate process with 10 layers of metal, the chip contains 1.14 billion transistors. The processor operates at 1.35 GHz.

On the memory side at ISSCC, SanDisk and Toshiba will present a 32 Gbit ReRAM test chip in a 24nm process with a diode as the selection device. Separately, TSMC will present a cycling-endurance optimization scheme for a 1-Mbit STT-MRAM in 40nm technology with a dynamic load balance circuit. And Micron will present the first ever 128-Gbit, 3-bit-per-cell NAND design using 20nm planar cell technology.

Mentor Graphics announced the availability of a GENIVI 3.0 specification-compliant Linux- based Infotainment product. The solution integrates graphics, communication and multimedia middleware with libraries, system infrastructure and management components on top of Linux. http://www.mentor.com/company/news/mentor-embedded-genivi-3-compliant

TSMC recently approved capital appropriations totaling approximately $2.975 billion for the purpose of expanding advanced process capacity and the construction of a 300mm GigaFab. It also approved R&D capital appropriations and 2013 sustaining capital appropriations totaling approximately $209.5 million. In addition, it approved the subscription of approximately $42.28 million in new shares to be issued by TSMC Solid State Lighting Ltd. in 2013. And finally, it approved the subscription of approximately $21.63 million in new shares to be issued by TSMC Solar Ltd. in 2013.

Creative Technology has entered into an agreement with Intel under which Intel will license certain GPU technology and patents from ZiiLABS, a subsidiary of Creative. Intel will acquire certain engineering resources and assets related to the U.K. subsidiary of ZiiLABS. The deal is worth $50 million.

MIPS Technologies has received an unsolicited and rival proposal from CEVA to acquire all of the outstanding shares of MIPS. This follows MIPS’ proposed patent sale transaction with Bridge Crossing.

Global GDP growth is now expected to expand by an estimated 2.6% in 2012, close to the global recession threshold of 2.5% and well below the long-term average growth rate of 3.5%. However, the forecast for worldwide GDP in 2013 is 3.2% growth, according to IC Insights.

Smartphones will account for a larger share of NAND flash memory usage, as compared to feature phones, according to iSuppli.

Global demand and pricing in October for solar polysilicon fell at the highest rate seen since February, indicating that supply still exceeds demand, according to the IHS Solar Polysilicon Price Index.

By Mark LaPedus
The insatiable thirst for more bandwidth in smartphones, tablets and other devices has prompted an industry standards body to revamp its mobile memory interface roadmap.

As part of the changes, the Joint Electron Devices Engineering Council (JEDEC) has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architecture until 2015.

In the previous roadmap, mobile DRAMs were supposed to follow a simple progression from the conventional LPDDR2 to the LPDDR3 interface standards. Then, in 2013, the mobile industry was originally supposed to make a giant leap to Wide I/O, a 3D technology using through-silicon vias (TSVs).

Now, in JEDEC’s new roadmap, the industry will extend LPDDR3 with a new DRAM interface standard called LPDDR3E. After LPDDR3E, the industry will follow two simultaneous paths with a pair of new standards: LPDDR4 and Wide I/O-2. Devices built around 2D-based LPDDR4 and 3D-enabled Wide I/O-2 are due out in 2015. The first Wide I/O standard is still on JEDEC’s roadmap, but the devices are expected to be limited and mere point products.

The changes in the roadmap reflect the need to address the current and future bandwidth bottleneck issues in mobile devices. It also confirms the industry is still struggling to develop stacked 3D chips due to cost and technical issues. “It will take more time to sort out (3D issues like Wide I/O) than what people originally thought,” said Pat Moran, memory program manager at Qualcomm, at a recent JEDEC event.

The resistivity problems in planar devices have fueled the development of stacked 3D chips, whether those TSVs run through a die or a separate interposer die in so-called 2.5D chips. In either case, stacking is a viable way to circumvent the resistance-capacitance (RC) problems. But advanced chip stacking has a multitude of challenges and is still a few years away from mass production.

The industry is making progress in terms of reducing the manufacturing costs, and the technical hurdles, for 3D chips, said Niranjan Kumar, product marketing manager for TSV programs at Applied Materials. But when the 3D chips actually hit the market, there is still a perception that the cost of devices will be prohibitively expensive, Kumar said.

A brief history of Wide I/O
Not long ago, the big memory houses mainly focused on selling commodity DRAMs for PCs and servers. But for some time, DRAM makers have been engulfed in a prolonged downturn amid a slump for PCs. And the rapid rise of smartphones and tablets has prompted memory makers to put more emphasis on mobile DRAMs, which are specialty DRAMs with low power features.

In a sign of the growing importance of these parts, mobile DRAM represented 26% of all DRAM sales in the second quarter of 2012, compared to 19% in the like period a year ago, and 11% two years ago, according to IHS iSuppli. Average DRAM content in smartphones will expand to 666 megabytes (MB) this year, up from 453MB in 2011 and 202MB in 2010, according to the firm.

“As smartphones become more sophisticated, memory usage in the devices continues to rise, not only to satisfy user wants and needs, but also to accommodate demands made by ever-more powerful processors and increasingly refined LCD screens,” said Clifford Leimbach, an analyst at IHS iSuppli.

To keep up with the bandwidth requirements in portable systems, OEMs have migrated from mobile DRAMs based on the LPDDR1 interface standard to LPDDR2 technology. LPDDR1 has a data rate of 1.6-GB/s, while LPDDR2 runs at 4.3-GB/s.

In 2008, there were fears that LPDDR2 would run out of steam. So, at the time, the industry pushed a 3D architecture called Wide I/O. Wide I/O was a 4-channel scheme with a data rate of 17.2 GB/s. In the original roadmap, the goal was to stack the devices using TSVs.

Then, in 2010, the mobile market turned upside down, when a new class of smartphones and tablets emerged. Suddenly, Wide I/O, which was originally targeted for high-end smartphones, could only address limited mobile applications. “Wide I/O wasn’t going to cover the entire mobile space,” Moran said.

What’s next?
As a result, the industry saw an urgent need to fill a gap between LPDDR2 and Wide I/O. Starting in 2010, JEDEC and its members began to work on 2D-based LPDDR3, an extension of LPDDR2 that operates at speeds up to 12.8-GB/s in a dual channel mode.

Today, Hynix, Micron and Samsung are sampling their respective LPDDR3 mobile DRAMs. Instead of LPDDR3, some OEMs are opting for a low-power version of a desktop DRAM, dubbed DDR3L. OEMs are expected to migrate towards both technologies in 2013.

Needless to say, the industry must go beyond LPDDR3. The explosion of video, games and other technology in the mobile environment is driving the need for 4G LTE networks. “The bandwidth requirements are steep,” said Jung-Yong Choi, senior product planning manager at Samsung. “We need to react quickly.”

In response, JEDEC has unveiled a new, three-step plan. In the first step, the industry has devised LPDDR3E, an extension to LPDDR3 that has a data rate of 17-GB/s in a dual-channel mode at 1.2 volts.

Following LPDDR3E, the industry will follow two simultaneous avenues. It will take another evolutionary and safe path with 2D-based LPDDR4. It also will pursue the more revolutionary path with 3D-based Wide I/O-2. “Both candidates will have their own positions in the mobile industry,” Choi said.

LPDDR4-based mobile DRAMs, which require more space, are aimed at tablets. LPDDR4 will have 25.6-GB/s data rates and operate at 1.1 Volts. LPDDR4 will have 2-channels per die and 8-banks per channel. The LPDDR4 specification is due out by December of 2013. LPDDR4-based mobile DRAMs are expected in the first half of 2015.

Wide I/O-2 has the same specification and product roll out target dates as LPDDR4. Aimed for smartphones, Wide I/O-2 will launch in two phases. The first devices will have a 25.6-GB/s data rate, followed by parts at 51.2-GB/s.

Wide I/O-2 resembles the same architecture as the original Wide I/O scheme. It will stack memory on a logic controller and will connect them using TSVs. Wide I/O-2 will consist of four channels per die, x64 I/Os per channel (25.6-GB/s) and x128 I/Os per channel (51.2-GB/s). However, the industry is still debating the other specifications, such as the number of banks, page sizes, AC/DC parameters, pad order, pin description, addressing and command protocols.

In theory, LPDDR4 will have a power efficiency of 1 Watt at 25.6-GB/s. In terms of power, Wide I/O-2 is expected to be 50% to 60% lower than LPDDR4, Choi said. “Efficiency of CPU frequency could be improved largely by active heat dissipation,” he said.

One question still lingers, though: What ever happened to the original Wide I/O technology? Surprisingly, memory vendors insist the original Wide I/O devices will soon hit the market. If or when Wide I/O appears, the niche-oriented parts will likely be single-die solutions using micro-bumps, and not TSVs.

In fact, when the industry originally pushed for Wide I/O in 2008, it underestimated the challenges in developing 3D technology. The industry still faces many of the same problems today. TSV technology remains immature. It’s unclear how to deal with the thermal issues, and 3D test and the overall supply chain are not yet ready for prime time.

Cost is still a problem, as well. An applications processor based on conventional package-on-package (PoP) technology may run $28 each. If the same device was configured with a Wide I/O scheme, it could cost about $50, according to some experts. The cost of the substrate, coupled with the TSV production process, “eliminates the product margins for consumer applications,” said Pol Marchal, director of R&D at IMEC’s India unit. In fact, the TSV creation process is 40% or more of the total cost for a 3D device, Marchal said.

Applied’s Kumar disagreed, saying that the industry has reduced the cost for the TSV creation process. Many blame high 3D chip costs on the temporary bonding/debonding, test and other process steps.

There are a number of process steps to make a 3D chip. In the via creation process alone, there are five main manufacturing steps: etch, chemical-vapor deposition (CVD), physical-vapor deposition (PVD), electroplating, and chemical mechanical polishing (CMP).

Two years ago, the overall manufacturing cost-of-ownership (COO) for making a 5μ x 50μ TSV was about $150, Kumar said. Today, the COO is about $50, he said. “I think it will continue to drop,” he added.

Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries, recently summarized the situation. “There are many issues we need to work through, such as how do you handle thin wafers once they are shipped, how do you test them and ensure known good dies,” he said. “If those wafers are packaged, that’s not a problem. If they’re not, how do you ensure the known good die? Also, with memory, the key integration is logic plus memory. In that case, the co-design of different die comes into the picture.”

Three pure-play foundries, TSMC, GlobalFoundries and UMC, are expected to be in the top 20 rankings of leading semiconductor suppliers in 2012, according to IC Insights.

In the rankings, Intel is projected to remain in first place in terms of sales in 2012, followed in order by Samsung, TSMC, Qualcomm, TI, Toshiba, Renesas, SK Hynix, Micron, and ST.

The only expected movement with regard to the top 5 spots in the 2012 ranking is that fabless supplier Qualcomm is forecast to register a 30% surge in sales this year and move up three positions to replace TI as the fourth largest semiconductor supplier, according to the firm.

As a result of its performance this year, GlobalFoundries is forecast to replace Elpida and move into the top 20 ranking for the first time, rising from the 21st spot in 2011 to 15th place in 2012, according to the firm. UMC will remain in 20th place. Sales from pure-play foundry GlobalFoundries are forecast to jump by 31% while foundry giant TSMC is expected to show a 17% increase this year, according to IC Insights.

Combined, these three foundries are forecast to log a 16% increase in 2012/2011 sales, quite impressive considering the expected 2% decline in the worldwide semiconductor market this year, according to the firm.

The continued success of the fabless/foundry business model is evident when examining the top 20 semiconductor suppliers ranked by growth rate. The top five performers are expected to include three fabless companies, Qualcomm, Nvidia, and Broadcom, and two pure-play foundries, GlobalFoundries and TSMC, according to the firm.

Illustrating the difficult year faced by the majority of the top 20 semiconductor suppliers, 12 of the top 20 ranked companies are forecast to register a sales decline this year, including 7 of the top 10 largest semiconductor suppliers in the world (#1 Intel, #2 Samsung, #4 TI, #6 Toshiba, #7 Renesas, #8 SK Hynix, and #10 ST).

By Mark LaPedus
The number of high-risk suppliers to the U.S. government, including companies that sold suspect counterfeit products to military and commercial electronics channels, soared by 63% from 2002 to 2011, according to IHS iSuppli.

Consolidation in the fab tool market continues.Brooks Automation has entered into a definitive agreement to acquire Crossing Automation, a rival supplier of fab automation tools. The cash purchase price is $63 million. Crossing, which bought the atmospheric automation portion of Asyst two years ago, has developed several 450mm fab automation sub-systems, such as loadports, sorters and modules.

A technologist from Micron kicked off SEMI’s 2012 Strategic Materials Conference (SMC) with a comprehensive overview of the challenges of electronic materials. At the event, VLSI Research reported on the status of directed self-assembly (DSA) technology. “AZ Electronic Materials showed good progress in DSA,” according to the research firm. “In particular, we’re really excited about DSA. The rate of progress over the last two years has sparked that feeling of déjà vu. It feels like those days of immersion’s emergence, just when it seemed like there was no answer, one emerged.”

Cadence Design Systems has announced the tapeout of a 14nm test chip featuring an ARM Cortex-M0 processor. The test chip is based on IBM‘s finFET process and silicon-on-insulator (SOI) technology. In a blog, Richard Goering provides the “inside story” of the 14nm finFET tapeout at Cadence.

Applied Materials rolled out new PVD and PECVD technologies to enable the next era of ultra-high definition (UHD) televisions and high-pixel density screens for mobile devices. The Applied AKT-PiVot PVD and Applied AKT-PX PECVD film deposition systems provide display manufacturers with a high-performance, cost-effective path to help bring advanced materials to volume production.

Mentor Graphics announced hardware and software solutions to accelerate the verification of PCI Express Generation 3 products.

UMC posted its results and disclosed that is working on a second-source model for TSMC-like processes.

X-FAB Silicon Foundries has increased its share in the German-based MEMS Foundry Itzehoe GmbH (MFI) from 25.5% to 51%. The move reflects X-FAB’s focus on MEMS manufacturing services and technologies.

MagnaChip said revenue for the third quarter of 2012 was $221.9 million, a 9.5% increase compared to $202.6 million for the second quarter of 2012, and a 10.7% increase compared to $200.4 million for the third quarter of 2011.

Apple rolled out new Mac computers that pair an SSD with a conventional HDD. Apple calls this its Fusion Drive, not to be confused with Fusion-io’s products. The SSD Guy weighs in.

ARM Holdings’ long-awaited entry into the 64-bit processor arena could propel the intellectual-property (IP) chip giant into new markets. ARM’s move also drew mixed reviews from analysts, especially regarding the announcement from one of its new licensees-Advanced Micro Devices Inc.

VLSI Research released its new outlook for 2013. The semiconductor equipment market is expected to reach $43.4 billion in 2013, down 4.4% from 2012. VLSI Research’s fab tool forecast calls for minus 14.3% in 2012.

According to NPD DisplaySearch, spending on manufacturing equipment for FPDs is forecast to rise 121% from $3.8 billion in 2012 to $8.3 billion in 2013.

After a strong surge in 2010 from the 2009 downturn and solid growth in 2011, the market for optoelectronics, sensors/actuators, and discrete semiconductors (O-S-D) lost most of its momentum in 2012, says IC Insights.

With Motorola (Google), RIM and Nokia posting operating losses during the third quarter of 2012, Canaccord Genuity technology analyst Michael Walkley estimated that Apple’s 59% of operating profits and Samsung’s 47%, combined to take 106% of all smartphone profits. He said, “Given the current competitive dynamics, we believe Apple and Samsung will maintain dominant value share during Q4/12 with share gains for Apple versus Samsung expected in Q4/12.” Walkley estimated that in 2013, AAPL will sell 193.9 million smartphones, while Samsung will sell 303.6 million, combining for more than 50% of market share. As a reference point, his next highest estimate of smartphone sales was with Huawei, at 47.9 million sales.

By Mark LaPedus

IC makers have been looking at the electric vehicle industry for growth. So whatever happened to the electric car? Toyota has scaled back the sales targets for its electric car. According to Lux Research, the head of Toyota’s vehicle development gave a vote of no confidence for the technology, by saying the “capabilities of electric vehicles do not meet society’s needs.” Meanwhile, Tesla Motors recently lowered its sales targets. Another car maker, Nissan, is offering big discounts on the Leaf because of slow sales. GM’s Chevy Volt has struggled to win customers, even though it’s not purely electric. And Fisker Automotive, which uses the same approach as Chevy, has experienced an assortment of problems.

At the 2012 IEEE International Electron Devices Meeting (IEDM), slated for Dec. 10-12 in San Francisco, Applied Materials and Synopsys are expected to submit a paper entitled, “Is strain engineering scalable in FinFET era? Teaching the old dog some new tricks.” “Strain technology has been a key enabler for improving transistor performance in the past decade. With the industry moving toward a 3-D FinFET structure from a planar MOSFET, the corresponding implications on stressor design needs to be analyzed afresh due to strong orientation dependence of stress enhancements,” according to the IEDM abstract from the companies. “In this work we have tried to address both issues; stressor design for FinFETs and scalability of corresponding stress enhancements. We found that the S/D epi remains an effective and scalable source of strain engineering for FinFETs. Contact and gate metals provide new knobs for engineering strain in FinFETs and remain effective with conservative scaling of contact/gate CD.”

Altatech, a subsidiary of Soitec, has introduced a multi-chamber chemical vapor deposition (CVD) system that enables photovoltaic (PV) cell manufacturers to develop and optimize their solar cell designs using advanced thin-film deposition of amorphous silicon and other materials. By performing all deposition processes within a single system, the new AltaCVD Solarlab tool reduces cycle times and materials consumption in fabricating advanced single-junction, tandem-junction and triple-junction PV cells.

GlobalFoundries is preparing to build a three-story, 565,000-square-foot manufacturing research center, according to a report.

While over-capacity continues to plague the global solar industry, the Taiwan PV industry is operating at high-capacity, according to SEMI.

SVTC Technologies is struggling and has apparently cut workers, according to reports, which added that the R&D foundry is mulling plans to close its sites in Austin, Texas and San Jose.  Multiple sources say SVTC may completely shut down. In an e-mail, SVTC declined to comment on the reports. A spokesman for Oak Hill Capital declined to comment. Oak Hill is an investor in SVTC. In 2007, Cypress sold its R&D fab unit to Oak Hill and Tallwood Venture for approximately $53 million. SVTC became a “lab-to-fab” facility aimed at third-party engineering groups.

As it turns out, Tezzaron Semiconductor has signed a contract to purchase the assets of a semiconductor technology development and wafer fabrication facility in Austin, Texas, previously run by SVTC. Tezzaron will continue the operations of this facility while adding capabilities to assemble its own 3D devices.

Struggling Renesas has obtained a $6 billion bailout from various banks. The chipmaker announced the execution of an agreement of a syndicate loan, with Mizuho, The Bank of Tokyo-Mitsubishi UFJ, Sumitomo Mitsui Trust Bank and Mitsubishi UFJ Trust and Banking Corporation.

Sharp has obtained a syndicated loan as it struggles to find investors.

For its 2012 fiscal year, Micron reported a net loss of $1.03 billion. C.J. Muse, an analyst with Barclays, said: “While Micron was hesitant to provide any speculative commentary around the potential Elpida acquisition, management did note that the deal is expected to close in [the first half of calendar year 2013].”

The JEDEC Solid State Technology Association has announced the initial publication of its Synchronous DDR4 standard.

Intel and its OEM partners unveiled the first wave of new tablets and tablet convertible designs based on Intel processors, including the new Atom Z2760, formerly codenamed “Clover Trail.”

Samsung’s foundry business has been selected by STMicroelectronics to provide it with products at the 32/28nm process node.

X-Fab plans to invest more than $50 million in its MEMS operations over the next three years.

Diodes plans to acquire Power Analog Microelectronics.

Gartner says Windows 8 is a big gamble Microsoft must make to stay relevant.

IC Insights believes that the more profitable foundries will be those that keep at the leading-edge of the process technology roadmap.

The average amount of DRAM in each smartphone shipped worldwide is expected to surge by nearly 50 percent this year, according to iSuppli.

By Mark LaPedus
The NAND flash memory market is entering into a new and painful cycle, a period that will impact suppliers, OEMs and fab tool vendors alike.

For some time, there has been an oversupply and depressed pricing in the NAND market. In mid-2011, Micron, Samsung, SK Hynix and Toshiba put on the brakes in their capital spending plans. And in recent months, NAND suppliers in total have announced plans to cut 150,000 wafer starts per month, or about 12% of the world’s NAND capacity, amid ongoing losses and sluggish demand.

Just as suppliers moved to cut their production, spot shortages of NAND surfaced at some OEMs in early September. Most OEMs are not seeing any shortages, but that could all change. Apple, the world’s largest buyer of NAND, could cause some gyrations in the channels as it ramps up its new iPhone 5.

So what’s the outlook in the fluid and confusing NAND market? Amid a bitter legal battle with Samsung, speculation is rampant throughout the NAND industry about whether Apple will swap suppliers from Samsung to SK Hynix, Toshiba and Micron. If that happens, Samsung would face an oversupply in NAND, while others may see capacity shortfalls.

The outlook is also not so rosy for fab tool vendors, which counted on a big capital spending cycle for NAND. In fact, NAND suppliers are expected to push out their capital spending plans until June of 2013 and perhaps beyond, said Vijay Rakesh, an analyst with Sterne Agee.

The lack of capital spending is expected to create a shortfall in NAND capacity, creating perhaps a long cycle of acute shortages. Presently, there is a capacity glut for NAND. “Demand should catch up with capacity by mid-2013,” said Jim Handy, an analyst with Objective-Analysis. “Then, there could be NAND shortages from then until the middle of 2015.”

In total, suppliers are expected to ship 28.013 billion gigabits of NAND in 2012, which represents a bit growth of 49% over 2011, according to Stern Agee. The figure is lower than the historical averages in terms of bit growth, which ranges from 65% to 85%, according to the firm. In total, suppliers are expected to ship 43.756 billion gigabits of NAND in 2013, which represents a bit growth of 56%, according to Stern Agee.

Boom to bust
NAND has seen its share of boom and bust cycles. Several years ago, NAND vendors witnessed a meteoric rise amid a boom for cell phones, flash cards, USB drives and other products.

Then, over the last two or so years, Micron, Samsung, SK Hynix and Toshiba began to expand their NAND production at a dramatic pace. The goal was to meet the anticipated demand for the next wave of product drivers, such as smartphones, solid-state drives (SSDs), tablets and ultrabooks.

Seeking to drive down product costs, particularly for SSDs, NAND vendors took the lead in process technology. For example, the Toshiba-SanDisk duo has been ramping up parts based on the world’s most advanced process, a 19nm technology.

The bottom fell out of the NAND market in recent times. NAND vendors built up too much fab capacity. Average selling prices (ASPs) for NAND fell by 46% in the first half of 2012. Demand for NAND in smartphones and tablets remains overwhelming, but SSD and ultrabook shipments have been disappointing thus far.

“The adoption of solid-state drives is not ramping as quickly as forecast, and with only a modest increase in the bits per box for mobile devices, we now see NAND bit growth in the range of 60% to 65%,” said Mike Splinter, chairman and chief executive of Applied Materials, during a recent conference call. As a result, NAND vendors in total plan to cut production by roughly 150,000 wafer starts per month “on top of a reduction in their capital spending,” Splinter said.

Based on recent announcements, Toshiba is cutting 30% of its NAND production, Micron is reducing its output by 15%, and SK Hynix and Samsung are each at 10%, said Hans Mosesmann, an analyst with Raymond James. “Using these percentages, this would equate to a 12% reduction in supply,” he said.

NAND vendors expected bit growth of about 70% in 2012, but they have lowered their forecasts to about 45%, said Robert Witkow, president of Westwood Marketing, a research firm. “All manufacturers are regulating bit growth by slowing the transitions of 2xnm to the 1xnm node,” Witkow said. “All manufacturers are slowing their transitions from 64-Gbit to 128-Gbit devices.”

One OEM, OCZ Technology, lowered its quarterly forecast in September, saying it could not obtain enough NAND parts for its SSDs. “My price survey and other feedback I’ve received confirm some tightness (in NAND supply),” Witkow said. “If we have allocation in NAND, which I think is possible in 2012, it will be short-lived. I think the NAND market will ease at the end of October, as production sold for Christmas winds down.”

The average selling price (ASP) outlook is good for consumers, but horrific for suppliers. In September 2010, NAND crossed the $1.00/GB price point. The price dropped to $0.35/GB in May of 2012, according to Objective-Analysis’ Handy. “It hit $0.31/GB in June, but then it went back up to $0.36/GB in August,” Handy said. “The June pricing was below manufacturing costs, which is unsustainable. It could go as low as $0.31/GB again, but not temporarily as it did before. That would be permanent.”

NAND CapEx slows
On the fab tool side of the equation, Applied Materials and others saw a softening in demand for gear in the summer, due in part to sharp declines in foundry and NAND spending. By late August, tool vendors saw a further deterioration in NAND, causing more tool pushouts, according to Applied’s Splinter.

Capital spending will remain anemic in DRAMs. The foundries expanded their 28nm capacities earlier this year. But more recently, foundries put the brakes on spending to digest their new tool buys, Splinter said. In total, fab tool capital spending is expected to reach $30 billion to $33 billion in 2012, down 10% to 20% from 2011, he said. In its original projection, Applied forecasted a flat year in fab tool spending.

There’s good and bad news for fab tool vendors. For example, Samsung, the world’s largest NAND vendor, is cutting some NAND production. But the company also is converting some of its NAND production to system LSI and foundry services. As it turns out, logic is more profitable than NAND.

Samsung still wants to remain the leader in NAND. Last year, for example, the company began ramping up NAND production in Line 16 in Korea. “Samsung has slowed its expansion of Line 16, but it did not cut wafer starts,” said Westwood Marketing’s Witkow.

In Austin, Texas, Samsung has two 300mm fabs, plus a copper metallization facility. One fab is a foundry/logic plant. The fab, dubbed S2, is a foundry plant dedicated for Apple.

The other fab in Austin is currently a NAND facility. Austin represents about 20% of Samsung’s total NAND capacity, according to Barclays Capital. However, Samsung is converting that fab from NAND into a system LSI plant, said Christian Gregor Dieseldorff, an analyst with SEMI. “Ultimately, all of Austin will be converted to system LSI,” Dieseldorff said.

In Korea, Samsung’s main logic/foundry fab is called S1, which is being expanded. Samsung is converting its Line 14 plant in Korea from NAND to 28nm logic capacity. Line 14 is now part of S1, he said.

Meanwhile, Toshiba, the world’s second largest NAND vendor, in June announced plans to cut NAND production by about 30% at its Yokkaichi Operation fab in Mie Prefecture, Japan. At a minimum, this could remove 6% of worldwide NAND supply, according to Barclays Capital.

Micron, the world’s third largest NAND vendor, is re-balancing its capacity. “Micron increased its triple-level-cell (TLC) wafer production slightly, but reduced its multi-level-cell (MLC) slightly in June. My belief is that the move was taken to support the Lexar consumer product builds for Christmas. Micron will likely shift (its production) back to MLC shortly,” said Westwood Marketing’s Witkow.

SK Hynix, the world’s fourth largest NAND vendor, added 10,000 wafer starts at its new M12 fab in Korea. But SK Hynix is also mulling plans to shift its capacity from NAND to DRAM in M12, according to Barclays Capital.