Posts Tagged ‘Micron’
By Jeff Dorsch, Contributing Editor
Jonathan Coors, CEO of the company’s Semiconductor and Medical Group, said Tuesday the Covalent acquisition was “really strategic for us. It enhanced the company as a whole.”
CoorsTek’s Japan market share in engineered ceramics was “relatively small prior to Covalent,” Coors noted. Covalent broadened CoorsTek’s product portfolio in carbons, quartz, and silicon products, according to Coors.
CoorsTek plans to pursue both organic growth in its business and acquisition opportunities as they present themselves, the CoorsTek executive said.
Asked whether privately held CoorsTek may pursue a public offering, Coors said, “We enjoy being private.” That status offers some “regulatory ease,” he noted.
As a private company, CoorsTek is able to engage in a “long-term thought process, while maintaining focus on quarterly performance,” Coors added.
CoorsTek also provides orthopedic implants, such as hip and knee replacements. Medical products present “a demand on quality that is as high (as semiconductor products), if not higher,” Coors noted. There is a “similar supply chain” in the two product lines, he stated.
Coors and other CoorsTek executives are meeting this week with customers to learn “where the market is heading,” Coors said. Such information gleaned at SEMICON West 2015 can point to “the next generation of growth,” he said.
Micron Technology, in the news this week on reports of a rumored takeover bid by Tsinghua Unigroup, is a customer of CoorsTek, according to Coors.
By Jeff Dorsch, Contributing Editor
The presentations at this week’s 3D Architectures in Semiconductor Integration and Packaging conference could be summed up in a famous Facebook status: “It’s complicated.”
They also could be summed up in one word: Progress.
This year has seen tremendous progress in implementation of 3DIC technology, according to speakers at the 11th annual conference, held in Burlingame, Calif. Those who have been touting and tracking 3D chips for years are looking forward to the 2015 introduction of Intel’s Xeon Phi “Knights Landing” processor for high-performance computing, which will incorporate the Hybrid Memory Cube technology in the same package as the CPU.
Activities began Wednesday, December 10, with a preconference symposium on “2.5/3D-IC Design Tools and Flows” and “3D Integration: 3D Process Technology.” Bill Martin of E-System Design kicked off the program with a presentation on path finding, a topic addressed several times over the next two days. He emphasized that preparing for a chip design project, such as choosing the right tools, is as important as the design and implementation phases when it comes to embracing 3DIC technology.
John Ferguson of Mentor Graphics later said there is “an infrastructure problem” in the semiconductor industry when it comes to process design kits (PDKs) for 2.5D and 3D chips. Taiwan Semiconductor Manufacturing has collaborated with Mentor and other leading suppliers of electronic design automation tools to offer PDKs to TSMC foundry customers, yet the next step must be taken to have outsourced semiconductor assembly and test contractors provide packaging PDKs.
Phil Garrou, a senior consultant for Yole Developpement, said 2014 has witnessed significant progress in implementation of 3DIC technology. “We no longer need to prove performance,” he said. “The remaining issue is cost.”
Several speakers addressed the topic of the Internet of Things and how it involves 3DICs on the first day of the conference. Steven Schulz of the Silicon Integration Initiative (Si2) said 3D chip designers should think of their products not as system-on-a-chip devices, but system-on-a-stack.
Yole’s Rozalia Beica said predictions that the Internet of Things market will be worth trillions of dollars in 2022 are “overoptimistic” and that “optimism is higher than current investment.” Yole looks for the market in IoT sensors to be worth $400 billion in 2024, she said.
Samta Bonsal of the GE Software Center spoke on the Industrial Internet. “That world is huge,” she said, and predicted it will have “a bigger impact” than consumer-oriented IoT applications. Gartner says the market for all IoT chips will be worth $7.58 billion in 2015, she noted. The market research firm also forecasts that 8 billion connected devices will be shipped during 2020, encompassing 35 billion semiconductor devices produced on 6 million wafers.
E. Jan Vardaman of TechSearch International presented a lively review of 3DIC technology, past and present. “There’s been a lot of good progress with TSV (through-silicon vias), enabling us to improve the process,” she said. Still, 3DIC has been a long time in coming, noting that Micron Technology began research and development on DRAM stacking a dozen years ago and Xilinx initiated development of a silicon-based interposer to be used with TSVs in 2006, six years before it was able to offer a field-programmable gate array with such technology, manufactured in volume by TSMC.
Dyi-Chung Hu of Unimicron looked past the silicon interposer to the era to using glass for interposers and substrate core materials. Glass has a low coefficient of thermal expansion compared with silicon, he noted, and is very flat. Its chief drawback is its brittleness, according to Hu.
Michael Gaynes of IBM’s Thomas J. Watson Research Center reported on his company’s two ICECool projects for the Defense Advanced Research Projects Agency, developing 3DICs that could run cooler in data-center servers.
The last day of the conference coincided with a convention devoted to the Star Trek television series in the adjacent hotel ballroom. Attendees dressed as Klingons and starship crew members mingled with the 3DIC technologists in the hotel lobby, all dreaming and thinking about the future.
By Ed Korczynski, Sr. Technical Editor
The future of 3D memory will be in application-specific packages and systems. That is how innovation continues when simple 2D scaling reaches atomic-limits, and deep work on applications is now part of what global research and development (R&D) consortium Imec does. Imec is now 30 years old, and the annual Imec Technology Forum held in the first week of June in Brussels, Belgium included fun birthday celebrations and very serious discussions of the detailed R&D needed to push nanoelectronics systems into health-care, energy, and communications markets.
3D memory will generally cost more than 2D memory, so generally a system must demand high speed or small size to mandate 3D. Communications devices and cloud servers need high speed memory. Mobile and portable personalized health monitors need low power memory. In most cases, the optimum solution does not necessarily need more bits, but perhaps faster bits or more reliable bits. This is why the Hybrid Memory Cube (HMC) provides >160Gb/sec data transfer with Through-Silicon Vias (TSV) through 3D stacked DRAM layers.
“We’re not adding 70-80% more bits like we used to per generation, or even the 40% recently,” explained Mark Durcan, chief executive officer of Micron Technology. “DRAM bits will only grow at the low to mid-20%.” With those numbers come hopes of more stability and less volatility in the DRAM business. Likewise, despite the bit growth rates of the recent past, NAND is moving to 30-40% bit-increase per new ‘generation.’
“Moore’s Law is not over, it’s just slowing,” declared Durcan. “With NAND, we’re moving from planar to 3D, and the innovation is that there are different ways of doing 3D.” Figure 1 shows the six different options that Micron defines for 3D NAND. Micron plans for future success in the memory business to be not just about bit-growth, but about application-specific memory solutions.
E. S. Jung, executive vice president Samsung Electronics, presented an overview of how “Samsung’s Breaking the Limits of Semiconductor Technology for the Future” at the Imec forum. Samsung Semiconductor announced it’s first DRAM product in 1984, and has been improving it’s capabilities in design and manufacturing ever since. Samsung also sees the future of memory chips as part of application-specific systems, and suggests that all of the innovation in end-products we envision for the future cannot occur without semiconductor memory.
Samsung’s world leading 3D vertical-NAND (VNAND) chips are based on simultaneous innovation in three different aspects of materials and design:
1) Material changed from floating-gate,
2) Rotated structure from horizontal to vertical (and use Gate All Around), and
3) Stacked layers.
To accomplish these results, partners were needed from OEM and specialty-materials suppliers during the R&D of the special new hard-mask process needed to be able to form 2.5B vias with extremely high aspect-ratios.
Rick Gottscho, executive vice president of the global products group Lam Research Corp., in an exclusive interview with SST/SemiMD, explained that with proper control of hardmask deposition and etch processes the inherent line-edge-roughness (LER) of photoresist (PR) can be reduced. This sort of integrated process module can be developed independently by an OEM like Lam Research, but proving it in a device structure with other complex materials interactions requires collaboration with other leading researchers, and so Lam Research is now part of a new ‘Supplier Hub’ relationship at Imec.
Luc Van den hove, president and chief executive officer of Imec, commented, “we have been working with equipment and materials suppliers form the beginning, but we’re upgrading into this new ‘Supplier Hub.’ In the past most of the development occurred at the suppliers’ facilities and then results moved to Imec. Last year we announced a new joint ‘patterning center’ with ASML, and they’re transferring about one hundred people from Leuven. Today we announced a major collaboration with Lam Research. This is not a new relationship, since we’ve been working with Lam for over 20 years, but we’re stepping it up to a new level.”
Commitment, competence, and compromise are all vital to functional collaboration according to Aart J. de Geus, chairman and co-chief executive officer of Synopsys. Since he has long lead a major electronic design automation (EDA) company, de Geus has seen electronics industry trends over the 30 years that Imec has been running. Today’s advanced systems designs require coordination among many different players within the electronics industry ecosystem (Figure 2), with EDA and manufacturing R&D holding the center of innovation.
“The complexity of what is being built is so high that the guarantee that what has been built will work is a challenge,” cautioned de Geus. Complexity in systems is a multiplicative function of the number of components, not a simple summation. Consequently, design verification is the greatest challenge for complex System-on-Chips (SoC). Faster simulation has always been the way to speed up verification, and future hardware and software need co-optimization. “How do you debug this, because that is 70% of the design time today when working with SoCs containing re-used IP? This will be one of the limiters in terms of product schedules,” advised de Geus.
Whether HMC stacks of DRAM, VNAND, or newer memory technologies such as spintronics or Resistive RAM (RRAM), nanoscale electronic systems will use 3D memories to reduce volume and signal delays. “Today we’re investigating all of the technologies needed to advance IC manufacturing below 10nm,” said Van den hove. The future of 3D memories will be complex, but industry R&D collaboration is preparing the foundation to be able to build such complex structures.
DISCLAIMER: Ed Korczynski has or had a consulting relationship with Lam Research.
By Sara Ver-Bruggen, contributing editor
In launching the iPod music player, Apple bumped consumption of NAND flash – a type of non-volatile storage device – driving down cost and paving the way for the growth of the memory technology into what is now a multibillion dollar market, supplying cost-effective storage for smart phones, tablets and other consumer electronic gadgets that do not have high density requirements.
The current iteration of NAND flash technology, 2D – or planar – NAND, is reaching its limits. In August 2013, South Korean consumer electronics brand Samsung announced the launch of its 3D NAND storage technology, in the form of a 24-layer, 128 GB chip. In 2014, memory chipmakers Micron and also SK Hynix will follow suit, heralding the arrival of a much-anticipated and debated technology during various industry conferences in recent years. Other companies, including Sandisk, are all working on 3D NAND flash technology.
Like floors in a tower block, in 3D NAND devices memory cells are stacked on top of each other, as opposed to being spread out on a two-dimensional (2D), horizontal grid like bungalows. Over the last few decades as 2D NAND technology has scaled, the X and Y dimensions have shrunk in order to go to each chip generation. But scaling, as process nodes dip below 20nm and on the path towards 10nm, is proving challenging as physical constraints begin to impinge on the performance of the basic memory cell design. While 2D NAND has yet to hit a wall, it is a matter of time.
Transition to mass production
But despite the potential of 3D NAND and announcements by the leading players in the industry, transferring 3D NAND technology into mass production is very challenging to do. As Jim Handy, from Objective Analysis, points out: “The entire issue of 3D NAND is its phenomenal complexity, and that is why no one has yet shipped a 3D NAND chip yet.” Mass production of Samsung’s device will happen this year. With 3D NAND there is the potential for vertical scaling, going from 16-bit-tall strings to string heights of more than 128 bits.
But while 3D NAND does not require leading-edge lithography, eventually resulting in manufacturing costs that are lower than they would be for the extension of planar NAND, new deposition and etch technologies are required for high-aspect-ratio etch processes. This “staircase” etching requires very precise contact landing. In 3D NAND manufacturing depositing layers of uniform thickness across the entire wafer presents issues with pull-back etching for these “stair steps” that currently increase the lithography load more than was originally anticipated.
“Everything in 3D is a significant challenge. With vertical scaling the challenges include etching high aspect ratio holes, with the aspect ratio doubling with each doubling of layers. These holes must have absolutely parallel walls or scaling and device operation may be compromised. If the layers are thinned then the atomic-layer deposition (ALD) of the layers must be able to apply a constant thickness layer across the entire wafer, which is also true of the layers that are deposited on the walls of the hole,” according to Handy.
Indeed, while the best combination of cost, power and performance will be found in 3D NAND architectures, there still remain issues concerning cost, especially. These issues, in the context of their respective memory technology roadmaps, were discussed by memory chipmakers, including Sandisk, SK Hynix and Micron, at a forum organized and sponsored by semiconductor industry equipment manufacturer Applied Materials in December 2013, while the equipment supplier provided some in-depth discussion on 3D NAND manufacturing considerations and challenges. The session was hosted by Gill Lee, Senior Director and Principal Member of Technical Staff Silicon Systems Group at Applied Materials.
Sandisk plays its 2D hand for as long as possible
Ritu Shrivastava, Vice President Technology Development, at Sandisk Corporation, set out the challenge. “Whenever you talk about technology, it has to be in relation to the objectives of your company. In our case we have a $38 billion total available market projected to 2016 and any technology choices that we make have to serve that market.” Examples of products he was referring to include smart phones and tablets. “Our goal is to choose technologies that are most cost-effective and deliver in terms of performance.”
Sandisk has a joint NAND fab investment with Toshiba and the two have had a 128 GB 2D NAND flash chip using 19 nm lithography in production for a while now. They have also previously announced plans to build a semiconductor fab for 16-17 nm flash memory.
”One of our goals is to extend the life of 2D NAND technologies as far as possible because it reflects the huge investment that we have made in fabs and the technology, over the number of years,” said Shrivastava. “Of course, 3D NAND is extremely important and when it becomes cost-effective then it will move into production.” Sandisk plans to start producing its 3D NAND chips in 2016.
“We are travelling in what we think is the lowest cost path in every technology generation, going from 19 nm to 1Y where we at the limit with lithography, and then we will scale to 1Z, which is our next-generation 2D NAND technology. We believe that this scaling path gives us the lowest cost structure in each of the nodes and in terms of cumulative investment.”
But it is not just achieving the smallest die size, it is the cost involved in scaling. Capital equipment investment is what determines success in the market, according to Shrivastava. “Even though we are saying that 3D NAND is a reality there are a couple of things that we need to keep in mind. It leverages existing infrastructure, which is good, but there are still a lot of challenges. 3D NAND devices use TFT as opposed to the floating gate devices commonly used in 2D NAND chips. New controller schemes and boards will be required also.”
So while, according to Shrivastava, 3D NAND is looking very promising, there is a big ‘but’ for a company such as Sandisk, which produces some of the most cost-competitive flash memory devices on the market. “2D NAND still continues to be more cost-effective than 3D NAND and 3D NAND is not yet proven in volume manufacturing. Every new technology takes some time. Getting to mass manufacturing will take time. Our goal is to extend 2D NAND as long as possible, continue to work on 3D NAND and introduce it when it becomes cost-effective.”
Shrivastava sees 2D and 3D NAND technologies co-existing for the rest of the decade. Beyond 3D NAND the company is developing a 3D resistive RAM (RRAM) as the future technology beyond 3D NAND.
From 3D DRAM to 3D NAND
Next Chuck Dennison, Senior Director Process Integration, from Micron, provided an overview of where the company is today in terms of its own NAND memory technology roadmap.
“Our current generation is 16nm NAND that is now in production and we’re showing that it is getting to be a very competitive and very cost-effective technology,” according to Dennison. Micron’s new 16nm NAND process provides the greatest number of bits per sq mm at the lowest cost of any multilayer cell (MLC) device. Eight of these die can hold 128 GB of data. The 16nm storage technology will be released on next-generation solid state drives (SSDs) during 2014. SSDs consist of interconnected flash memory chips as opposed to platters with a magnetic coating used in conventional hard disk drives (HDDs).
“Our next node is a 256 GB class of the NAND memory. Technically it could be extended before taking the full step to 3D NAND.”
Today NAND is the lowest cost-per-bit memory technology and this continued cost-per-bit reduction is really driving the whole of the NAND industry, according to Dennison. It is why NAND replaced DRAM in terms of total dollars and has continued to proliferate across various applications, and is responsible for continued innovation in portable consumer electronics, such as tablets, where so much functionality enabling photography, video recording, storage of an entire music library, and so on, can be packed into one device.
Outlining Micron’s technology scaling path, Dennison explained: “We went to high-K/metal gate to 20 nm and we used the same technology to extend us to 16nm. From there, the company is moving to a vertical channel 3D NAND for a 256 GB class.
“In terms of capital expenditure (CapEx) per wafer it all looks very cost-effective, with a little bit of transition going to 20 nm,” explained Dennison, because of the high-K metal gate, but with minimal increase going to 16nm. “But when you go to 3D NAND it is expensive, per wafer. So if you are increasing your wafer costs by X amount you need a much higher amount of GB per cm sq, so the density we are choosing to go with is a 256 GB class. And when you start actively looking at 3D NAND there are a lot similarities between 3D NAND and DRAM,” he explained, referring to the stacked capacitor of DRAM. “There is a lot planarization, you are etching very high aspect ratio contacts where you need to be very controlled, in terms of how you define your control and CD uniformity. Then there are a lot of additional modules requiring ALD deposition. So we think that there is a lot of opportunity to utilize our DRAM expertise.”
He outlined an inflection point going from 16nm, again. “We’re transitioning to go to the 256 GB density. We think that when we do this it will make financial sense and it will be a cost-effective solution despite the high Capex. And then from there we will continue. With the majority, or bulk, of the market we’ll see vertical NAND continuing to scale with a couple of us scaling fast for that market.”
Dennison also touched on longer term advances in classes of flash memory, in the form of 3D cross-point technology. These are memories stacked in cross-point arrays over CMOS logic to enable memory technology with speed features akin to DRAM but the density and cost effectiveness of NAND. The 3D stacked memory arrays in 3D cross-point technology would make these devices suitable, for future, in very high density computing and even biological systems.
“But, to conclude, NAND will not be replaced and will continue to be the lowest cost, it’s going to be the largest market in tablets, phones and so on. It’s not the best memory technology – it has poor cycling endurance and it has a terrible latency – but it is very low cost at very high density so it is the most cost-effective solution. We think that 3D cross-point absolutely has a market in terms of displacing DRAM and will selectively displace some NAND in very high performance applications but we will stay with NAND and go to 3D NAND.”
Soek-Kiu Lee, VP and Head of the Flash Device Technology Group, at SK Hynix brought the audience up to speed on his company’s NAND technology. Every year SK Hynix has increased bit density per area by around 50%. The company’s 16nm 64 GB MLC NAND flash, based on floating gate technology, has been in production since mid-2013 with SK Hynix now entering full scale mass production of 16nm chips. SK Hynix will start to ship samples of its 3D NAND chips this year with mass production happening later in 2014.
Like Shrivastava, Lee expects that 2D NAND and 3D NAND will co-exist and compete with each other in terms of reliability, performance and density, for some time and that the big challenges facing the transition to 3D NAND architectures include stabilization of multi-stack patterning to improve yields, better metrology and defect monitoring in the 3D structure itself.
Head for heights
Lastly, Applied Materials was able to provide some insight into manufacturing the more complex structures that moving to 3D NAND device architecture entails. Very simplistically, to make 3D NAND flash devices requires building extremely tall multilayer structures. Every layer in the device requires an insulating layer, so – for example – a 32-layer device is really a 64-layer device. As a result of this, aspect ratios of the structure being etched are getting to be very high and the challenge that this poses is nothing less than a game-changer for etch and deposition, according to Applied Materials’ Vice President, Advanced Technology Group Etch Business Unit, Bradley Howard.
“Historically, if you look at how scaling has gone, it has been limited by lithography on getting to the next node down, now we getting to the point where scaling is being driven by deposition and etching because as the scaling is now going in a vertical direction you’ve eased out the design rules.” The reality is that lithography is still important, Howard said, listing off control, good uniformity and other factors. ‘Everything that you had to have from lithography before still needs to be there but it just does not need to be the limiting factor for scaling.”
High aspect ratios present lots of challenges. Standard photolithography will not hold up for the long etches required for etching such deep features so hard mask layers are needed. “Depositioning is transitioning from single layer depositions in typically thinner films to multilayer stacks where you go and deposit alternating stacks of films and then also very thick films for both device and the hard mask,” said Howard.
Howard addressed the gates axis, an alternating stack of materials built up with alternating layers. “You need to have very precise control and very low defectivity. Historically, if you had a defect come in on a film it affected that bit, or that area. Now if you get a defect that gets deposited on your first layer down at the bottom it becomes a propagating defect that goes up the entire stack and it is going up in regions , which means that the defect density on deposition is becoming more important.”
Howard then moved on to hard masks. “We are going to have thicker hard masks because the aspect ratios of what you are trying to etch are getting very extreme as well as the amount of depth you have to etch. Having a micron or a micron-and-a-half of hard mask is not unusual. In effect, the hard mask that you are forming is its own high aspect ratio feature and then it is forming a high aspect ratio feature below it. In addition, there are various challenges on the isolation on getting the gap filled between the features and also into these very complex three dimensional structures.
“On the etch side high aspect ratio is really the key. There are multiple features, contacts in the array, there are contacts coming out of the staircase, and 60: 1 aspect ratios are becoming the common target here.
“At the edge of the array access still has to be made at each one of the layers, so a staircase structure is made to enable different landing pads for contacts to come down. But some of the contacts – towards the top – are very shallow and the ones at the bottom are extremely deep.
“You might think it might be achieved by doing a litho step and an etch step and a litho step and an etch step and doing that 32, 64, or whatever number of times, but what happens is that you are starting out with a feature and you etch down into the feature then you pull back the resist and then you etch again and then you pull back the resist and so you start to form your ‘steps’ that way and you do that as many times as you can get away with, depending on the amount of resist that you have. So, you can envision that you are trying to pull this resist back really fast. The problem is the resist is now determining the CD for the cell, so you need to have good control in place.” Howard summarized the challenges as being about sequential processes for both deposition and etching, thick films – whether it be the alternating stack of films or the thick films that are done to separate out the different arrays – and, finally, defect densities – especially with deposition – which are becoming more critical than ever before because of the additive effect on the deposition.
Dr Ritu Shrivastava, Vice President Technology Development, at SanDisk Corporation
Chuck Dennison, Senior Director, Process Integration, at Micron
Dr Soek-Kiu Lee, VP and Head of the Flash Device Technology Group, at SK Hynix
Hang-Ting Liu, Deputy Director Nanotechnology R&D Division, at Macronix International Co.
Dr Bradley Howard, Vice President, Advanced Technology Group Etch Business Unit, at Applied Materials
Zvi Or-Bach, President and CEO of MonolithIC 3D weighs in on the battle of Intel vs TSMC in the foundry space, after conflicting stories appeared. One said that Intel had a huge pricing advantage over TSMC, and a second story noted TSMC’s boast that it was “far superior” to Intel and Samsung as a partner fab.
Adele Hars looks back at 2013 from the SOI perspective. In this “Part 2” post, she focuses on developments that last year brought in the areas of RF-SOI and SOI-FinFETs. Part 1 focused on the general SOI picture. Stayed tuned for a look at 2014.
Phil Garrou reports on some of the key 3DIC presentations from the IEEE Internal Electron Devices Meeting (IEDM), held in December in Washington, D.C. , focusing on papers from Micron, TSMC, Tohoku Univ., NC State and ASET. He said that Micron’s Naga Chandrasekaran addressed challenges in future memory manufacturing for both front end 3D NAND and back end 3DIC stacking, noting that he does not see any of the newer memory technologies making inroads against conventional DRAM or NAND in the next decade.
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.