Posts Tagged ‘Microchip’
SEMATECH announced this week that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet lithography, pushing the technology another significant step toward readiness for high-volume manufacturing.
University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.
GlobalFoundries this week introduced an optimized semiconductor manufacturing platform aimed specifically at meeting the stringent and evolving needs of the automotive industry.
Peregrine Semiconductor announced shipment of the first RF switches built on the UltraCMOS 10 technology platform.
BASF inaugurated a new Electronic Materials Sampling and Development facility in Hillsboro, Oregon. The new facility is a strategic step towards establishing a North American footprint to supply materials for semiconductor manufacturing applications related to the electronics industry.
Veeco Instruments Inc. has appointed Shubham Maheshwari, 42, as its new Executive Vice President, Finance and Chief Financial Officer (CFO). Mr. Maheshwari replaces David D. Glass, who announced his retirement from Veeco last December.
Avago Technologies Limited and LSI Corporation announced Avago has completed its acquisition of LSI Corporation for $11.15 per share in an all-cash transaction valued at approximately $6.6 billion.
Microchip Technology Inc., a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, this week introduced a new parallel Flash memory device.
The Semiconductor Industry Association announced that worldwide sales of semiconductors reached $78.47 billion during the first quarter of 2014, marking the industry’s highest-ever first quarter sales.
Qualcomm elected Harish Manwani to board of directors. Manwani brings more than 35 years of consumer product and global management experience, and currently serves as the Chief Operating Officer at Unilever PLC.
Graphene meets heat waves; UT Dallas technology could make night vision, thermal imaging affordable; Breakthrough in OLED technology
A new spin on spintronics; Novel solid-state nanomaterial platform enables terahertz photonics; Novel crumpling method takes flat graphene from 2-D to 3-D
The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.
Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.
In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.
Certain measurement methodologies can be inaccurate even if they’re precise, and there are known errors associated with certain system parameters.
The etch loading effect is the dominant factor that impacts final CD control at advanced nodes with shrinking critical dimension.
A look at ways to simplify the optical and resist model calibration and to speed up the entire process.
Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing.
Testing interposer-based versions of stacked die and future versions using through-silicon vias.